bcm63xx/u-boot/arch/arm/include/asm/io.h, branch master

arm: asm: io.h: define readX_relaxed and writeX_relaxed

2019-04-22T15:55:58Z

This patch port the function readX_relaxed and writeX_relaxed from kernel 4.18. Signed-off-by: Philippe Reynes

arm: implement {in, out}_{16, 32} and {clr, set, clrset}bits_{16, 32}

2018-12-07T13:13:46Z

Signed-off-by: Álvaro Fernández Rojas

arm: Use asm-generic/io.h

2017-10-03T01:52:20Z

Convert the arm architecture to make use of the new asm-generic/io.h to provide address mapping functions. As the generic implementations are suitable for arm this is primarily a matter of removing code. This has only been build-tested, feedback from architecture maintainers is welcome. Signed-off-by: Paul Burton Cc: Albert Aribaud Reviewed-by: Simon Glass

ARM: Rework and correct barrier definitions

2016-08-05T11:23:57Z

As part of testing booting Linux kernels on Rockchip devices, it was discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for some cases incomplete isb definitions. This was causing a failure to boot of the Linux kernel. In order to solve this problem as well as cover any corner cases that we may also have had a number of changes are made in order to consolidate things. First, now becomes the source of isb/dsb/dmb definitions. This however introduces another complexity. Due to needing to build SPL for 32bit tegra with -march=armv4 we need to borrow the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add a comment about it. Now that we can always know what the target CPU is capable off we can get always do the correct thing for the barrier. The final part of this is that need to be consistent everywhere and call isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the function names in others. Reviewed-by: Stephen Warren Tested-by: Stephen Warren Acked-by: Ziyuan Xu Acked-by: Sandy Patterson Reported-by: Ziyuan Xu Reported-by: Sandy Patterson Signed-off-by: Tom Rini

arm, nds32, sh: remove useless ioremap()/iounmap() defines

2016-07-14T22:22:25Z

These defines are valid only when iomem_valid_addr is defined, but I do not see such defines anywhere. Remove. Signed-off-by: Masahiro Yamada

arm: add missing writes[bwql], reads[bwql].

2016-04-10T15:18:41Z

ARM defines __raw_writes[bwql], __raw_reads[bwql] in arch io.h but not the writes[bwql], reads[bwql] needed by some drivers. Signed-off-by: Purna Chandra Mandal

Data types defined for 64 bit physical address

2015-10-29T17:33:57Z

Data types and I/O functions have been defined for 64 bit physical addresses in arm. Signed-off-by: Aneesh Bansal Reviewed-by: York Sun

arm: ls102xa: Add Freescale LS102xA SoC support

2014-09-08T17:30:32Z

The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale. Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability. Signed-off-by: Alison Wang Signed-off-by: Jason Jin Signed-off-by: Jingchang Lu Signed-off-by: Prabhakar Kushwaha

ARM:asm:io.h use static inline

2014-08-29T19:50:43Z

When compiling u-boot with W=1 the extern inline void for read* is likely causing the most noise. gcc / clang will warn there is never a actual declaration for these functions. Instead of declaring these extern make them static inline so it is actually declared. cc: Albert ARIBAUD Signed-off-by: Jeroen Hofstee

driver/ddr: Fix DDR4 driver for ARM

2014-07-22T23:25:54Z

Previously the driver was only tested on Power SoCs. Different barrier instructions are needed for ARM SoCs. Signed-off-by: York Sun