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<title>bcm63xx/u-boot/arch/arm/lib, branch master</title>
<subtitle>Broadcom-s U-Boot</subtitle>
<id>https://git.openwrt.org/project/bcm63xx/u-boot/atom?h=master</id>
<link rel='self' href='https://git.openwrt.org/project/bcm63xx/u-boot/atom?h=master'/>
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<updated>2019-05-18T12:15:35Z</updated>
<entry>
<title>CONFIG_SPL_SYS_[DI]CACHE_OFF: add</title>
<updated>2019-05-18T12:15:35Z</updated>
<author>
<name>Trevor Woerner</name>
</author>
<published>2019-05-03T13:41:00Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=1001502545ff0125c39232cf0e7f26d9213ab55f'/>
<id>urn:sha1:1001502545ff0125c39232cf0e7f26d9213ab55f</id>
<content type='text'>
While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances
where these configuration items are conditional on SPL. This commit adds SPL
variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates
the configurations as required.

Acked-by: Alexey Brodkin &lt;abrodkin@synopsys.com&gt;
Signed-off-by: Trevor Woerner &lt;trevor@toganlabs.com&gt;
[trini: Make the default depend on the setting for full U-Boot, update
more zynq hardware]
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>arm: zimage: add barebox image magic number</title>
<updated>2019-05-10T00:21:59Z</updated>
<author>
<name>Christoph Fritz</name>
</author>
<published>2019-05-03T11:19:49Z</published>
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<id>urn:sha1:02c038ddb30fa52bb3f9fc9c80ad0776398b70a7</id>
<content type='text'>
For chainboot configurations or test environments, this patch allows
booting barebox images by using command bootz.

Signed-off-by: Christoph Fritz &lt;chf.fritz@googlemail.com&gt;
</content>
</entry>
<entry>
<title>arm: add a separate stack for TPL</title>
<updated>2019-05-08T09:34:12Z</updated>
<author>
<name>Kever Yang</name>
</author>
<published>2019-04-02T12:41:21Z</published>
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<id>urn:sha1:a0a0d04f3218507aaa29b4fdd45f37d819fb0a32</id>
<content type='text'>
TPL stack may different from SPL and sys stack, add support for
separate one when the board defines it.

Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>arm: remove ARCH_ROCKCHIP macro in common code</title>
<updated>2019-05-08T09:34:12Z</updated>
<author>
<name>Kever Yang</name>
</author>
<published>2019-05-06T03:21:13Z</published>
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<id>urn:sha1:dc23c27aa5ac7672bc8206e0f46e9aceab1f0bb7</id>
<content type='text'>
This is fix to:
e2a12f590d rockchip: use 'arch-rockchip' as header file path

The V2 of origin patch set has fix this, but we merge V1 by
mistake, so lets correct it.

Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
</content>
</entry>
<entry>
<title>rockchip: arm: use 'arch-rockchip' for common header</title>
<updated>2019-04-30T22:00:05Z</updated>
<author>
<name>Kever Yang</name>
</author>
<published>2019-03-28T03:01:22Z</published>
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<id>urn:sha1:6916dad51104ca297c8037e15d9abcd1811117f5</id>
<content type='text'>
rockchip platform header file is in 'arch-rockchip'
instead of arch-$(SOC) for all SoCs.

Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</content>
</entry>
<entry>
<title>arm: arm64 32bit address relocation</title>
<updated>2019-04-22T22:13:24Z</updated>
<author>
<name>Ibai Erkiaga</name>
</author>
<published>2019-03-15T12:18:41Z</published>
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<id>urn:sha1:98ffbb78e12646a1d06236ad6a1893217f255aae</id>
<content type='text'>
Current relocation code is limited to 21bit PC-relative addressing
which might not be enough for bigger code sizes. The following patch
increases the addressing to 32bit PC-relative. This feature is
specially interesting if U-Boot is build without optimiation (-O0) as
the text section is increased significativelly.

Signed-off-by: Ibai Erkiaga &lt;ibai.erkiaga-elorza@xilinx.com&gt;
</content>
</entry>
<entry>
<title>arm: print information about loaded UEFI images</title>
<updated>2019-04-12T20:00:42Z</updated>
<author>
<name>Heinrich Schuchardt</name>
</author>
<published>2019-04-04T20:06:25Z</published>
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<id>urn:sha1:bba816569075be9bcede1ef5626336ee5d014de8</id>
<content type='text'>
If an exception occurs in a UEFI loaded image we need the start address of
the image to determine the relocation offset.

This patch adds the necessary lines after the registers in the crash dump
for armv8. A possible output would be:

UEFI image [0x00000000bffe6000:0x00000000bffe631f] pc=0x138 '/\snp.efi'

With the offset 0x138 we can now find the relevant instruction in the
disassembled 'snp.efi' binary.

Signed-off-by: Heinrich Schuchardt &lt;xypron.glpk@gmx.de&gt;
</content>
</entry>
<entry>
<title>arm: lib: bootm: Push the Starting kernel print to the end</title>
<updated>2019-03-22T12:35:50Z</updated>
<author>
<name>Keerthy</name>
</author>
<published>2019-02-20T12:47:22Z</published>
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<id>urn:sha1:6dad56d733b0334f55a10276e4a3bccc8ca32e43</id>
<content type='text'>
Push the Starting kernel print to the end just before the
dm_remove_devices call.

Signed-off-by: Keerthy &lt;j-keerthy@ti.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>ARM: cache: Fix incorrect bitwise operation</title>
<updated>2019-02-28T19:21:46Z</updated>
<author>
<name>Marek Vasut</name>
</author>
<published>2019-02-19T00:43:51Z</published>
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<id>urn:sha1:86dc480d73776e6628ea39a5429f160ffdc2ec85</id>
<content type='text'>
The loop implemented in the code is supposed to check whether the
PL310 operation register has any bit from the mask set. Currently,
the code checks whether the PL310 operation register has any bit
set AND whether the mask is non-zero, which is incorrect. Fix the
conditional.

Signed-off-by: Marek Vasut &lt;marex@denx.de&gt;
Cc: Dalon Westergreen &lt;dwesterg@gmail.com&gt;
Cc: Dinh Nguyen &lt;dinguyen@kernel.org&gt;
Cc: Tom Rini &lt;trini@konsulko.com&gt;
Fixes: 93bc21930a1b ("armv7: add PL310 support to u-boot")
Reviewed-by: Simon Goldschmidt &lt;simon.k.r.goldschmidt@gmail.com&gt;
Reviewed-by: Dinh Nguyen &lt;dinguyen@kernel.org&gt;
</content>
</entry>
<entry>
<title>arch: arm: lib: Flush L3 after relocation to DDR</title>
<updated>2019-02-19T04:56:43Z</updated>
<author>
<name>Meenakshi Aggarwal</name>
</author>
<published>2019-02-18T18:38:30Z</published>
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<id>urn:sha1:b3b7706b2f507d449ce2ee364a12dc30ee4c215a</id>
<content type='text'>
Flush L3 cache after uboot relocated to DDR.

Signed-off-by: Meenakshi Aggarwal &lt;meenakshi.aggarwal@nxp.com&gt;
Signed-off-by: Udit Kumar &lt;udit.kumar@nxp.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Reviewed-by: Prabhakar Kushwaha &lt;prabhakar.kushwaha@nxp.com&gt;
</content>
</entry>
</feed>
