bcm63xx/u-boot/arch/arm/mach-sunxi, branch master

Merge branch 'master' of git://git.denx.de/u-boot-sunxi

2019-05-20T17:53:51Z

- H6 WDT reset fix (Clément) - H6 SPL_TEXT_BASE fixes (Clément, Jonas) - NPI-M1+ emac enablment (Emmanuel)

arm: sunxi: h6: fix reset using r_wdog

2019-05-20T16:54:47Z

Some H6 boards have a watchdog which didn't make the SoC reboot properly. Reason is still unknown but several people have test it. Chen-Yu Tsai : Pine H64 = H6 V200-AWIN H6448BA 7782 => OK OrangePi Lite 2 = H6 V200-AWIN H8068BA 61C2 => KO Martin Ayotte : Pine H64 = H8069BA 6892 => OK OrangePi 3 = HA047BA 69W2 => KO OrangePi One Plus = H7310BA 6842 => KO OrangePi Lite2 = H6448BA 6662 => KO Clément Péron: Beelink GS1 = H6 V200-AWIN H7309BA 6842 => KO After the series of result, Icenowy try to reach Allwinner about this issue but they seems not interested to investigate it. As we don't have the ARIS coproc to do power management and watchdogis the only solution to reset the board. So, Change from watchdog to R_watchdog to allow a reboot on all H6 boards. Signed-off-by: Clément Péron Reviewed-by: Jagan Teki

CONFIG_SPL_SYS_[DI]CACHE_OFF: add

2019-05-18T12:15:35Z

While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin Signed-off-by: Trevor Woerner [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini

arm: sunxi: Enable DM_MMC and DM_SCSI

2019-04-17T09:04:45Z

- Enable DM_MMC if MMC defined - Enable DM_SCSI if SCSI defined globally through Allwinner platform, the effected SoC families and boards will make use of MMC and SCSI subsystems in driver-model. Tested DM_MMC in one board from A64, H6, H5, H3, R40, A83T, A20, A10 SoCs. Tested-by: Pablo Sebastián Greco # BPI-M2-Ultra Signed-off-by: Jagan Teki

sunxi: Allow booting from 128KB SD/eMMC offset

2019-04-10T10:04:32Z

On modern Allwinner SoCs (tested: H2+, A64, H5, H6) the BootROM can actually load the SPL also from sector 256 (128KB) of an SD card or eMMC chip. For more details, see [1]. In this case the boot source indicator (written at offset 0x28 of SRAM A1) has bit 4 set, so it's 0x10 for SD card and 0x12 for eMMC. Add those new values to the existing boot source check to allow booting the SPL from those "high" disk offsets as well. For this to work, the value of CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR needs to be adjusted, for instance to 0x140 (right after the high SPL). Doing this dynamically sounds desirable, but looks nasty to implement. [1] https://groups.google.com/forum/#!topic/linux-sunxi/MaiijyaAFjk Signed-off-by: Andre Przywara Acked-by: Maxime Ripard

arm: sunxi: Enable DRAM ODT by default on H3/H5

2019-04-10T10:04:32Z

Most of the boards we support with H3/H5 enable DRAM on-die termination, which is consistent with the high DRAM clocks that are used. Make it the default (like it's done for other similar platforms) instead of defining it in each defconfig. Signed-off-by: Paul Kocialkowski Reviewed-by: Jagan Teki

arm: sunxi: Set the default DRAM ZQ value to 3881979 on H3/H5

2019-04-10T10:04:32Z

Most H3/H5 boards we support have the DRAM ZQ value set to 3881979, which is also consistent with the default set for the R40. Make this value the default on H3/H5 instead of 123. Signed-off-by: Paul Kocialkowski Reviewed-by: Jagan Teki

arm: sunxi: Allow per-platform DRAM ZQ configuration on sun8i

2019-04-10T10:04:32Z

A few sun8i platforms define specific default DRAM ZQ values, but they are not taken in account because of MACH_SUN8I being used for the 123 default first. Replace MACH_SUN8I with the list of platforms that don't have specific DRAM ZQ values, to avoid overwriting the default for those that do. Signed-off-by: Paul Kocialkowski Acked-by: Jagan Teki

sunxi: dram_sun8i: Fix A33 memory initialization

2019-04-10T10:02:59Z

While the exact problem is not known, based on discussion between Philipp Tomsich and André Przywara it is guessed that exit self-refresh timing is not set with correct value. There may be implicit enter or exit Self-Refresh anywhere as part of some training phase. In ZynqMP register guide [1], which is close to the various Allwinner DRAM controllers, tXSDLL is bits [14:8], while the non-DLL tXS is bits [6:0]: Self refresh exit delay. So it could be safely increased and it only affects the time after the self-refresh “exit”, which happens only after (re-)initialisation. There was no document for cpu in question so based on oscilloscope readings [2][3] and observed result by comparing allwinner architecture. So set it same as Allwinner H5 silicon. Before this patch, failure rate of was 7%. This was tested on A33 allwinner cpu, dual rank connection connected with two MT41K512M16HA-125:A memory model. Memory is configured as DDR3 1.5V And also this is tested in A33-OLinuXino dev board. [1] https://www.xilinx.com/html_docs/registers/ug1087/ddrc___dramtmg8.html [2] https://ibb.co/R70zmyS [3] https://ibb.co/HVVCGQ8 Signed-off-by: Michael Trimarchi Signed-off-by: Shyam Saini Acked-by: Jagan Teki

arm: sunxi: Enable DM_MMC on required SoCs

2019-04-08T20:35:15Z

Enabling DM_MMC is forcing CONFIG_BLK=y so if any board which uses SCSI must need to enable DM_SCSI otherwise SCSI reads on that particular target making invalid reading to the disk drive. Allwinner platform do support SCSI on A10, A20 and R40 SoC's out of these only A10 have DM_SCSI enabled. So enabling DM_MMC on A20, R40 would eventually end-up with scsi disk read failures like [1] So, enable DM_MMC in all places of respective SoC's instead of enabling them globally to Allwinner platform. Now, DM_MMC is enabled in Allwinner SoC's except A20 and R40. [1] https://lists.denx.de/pipermail/u-boot/2019-April/364057.html Reported-by: Pablo Sebastián Greco Signed-off-by: Jagan Teki