bcm63xx/u-boot/arch/mips/lib, branch master

arch: mips: Update initrd_start and initrd_end

2019-05-03T14:42:23Z

Microsemi SoC defines CONFIG_SYS_SDRAM_BASE to be 0x80000000, which represents the start of kseg0 and represents a virtual address. Meaning that the initrd_start and initrd_end point somewhere kseg0. When these parameters are passed to linux kernel through DT they are pointing somewhere in kseg0 which is a virtual address but linux kernel expects the addresses to be physical addresses(in kuseg) because it is converting the physical address to a virtual one. Therefore update the uboot to pass the physical address of initrd_start and initrd_end by converting them using the function virt_to_phys before setting up the DT. Signed-off-by: Horatiu Vultur Reviewed-by: Daniel Schwierzeck

bootm: mips: Remove boot_reloc_ramdisk

2019-04-12T15:32:50Z

Remove the function boot_reloc_ramdisk in the file arch/mips/lib/bootm because it is relocating again the ramdisk. The function do_bootm_states() already relocates the ramdisk even if it is a legacy uImage or a FIT image. The relocation in the function do_bootm_states() was introduce in the commit c2e7e72bb9f0cb47d024997b381cb64786eb5402 ("bootm: relocate ramdisk if CONFIG_SYS_BOOT_RAMDISK_HIGH set") Signed-off-by: Horatiu Vultur Reviewed-by: Daniel Schwierzeck

MIPS: cache: remove config option CONFIG_SYS_MIPS_CACHE_MODE

2018-09-22T19:04:10Z

Caches should be configured to mode CONF_CM_CACHABLE_NONCOHERENT (or CONF_CM_CACHABLE_COW when a CM is available). There is no need to make this configurable. Signed-off-by: Daniel Schwierzeck

MIPS: cache: make index base address configurable

2018-09-22T19:02:03Z

The index base address used for the cache initialisation is currently hard-coded to CKSEG0. Make this value configurable if a MIPS system needs to have a different address (e.g. in SRAM or ScratchPad RAM). Signed-off-by: Daniel Schwierzeck

MIPS: cache: optimise changing of k0 CCA mode

2018-09-22T19:02:03Z

Changing the Cache Coherency Algorithm (CCA) for kernel mode requires executing from KSEG1. Thus do a jump from KSEG0 to KSEG1 before changing the CCA mode. Jump back to KSEG0 afterwards. Signed-off-by: Daniel Schwierzeck

MIPS: cache: reimplement dcache_[status, enable, disable]

2018-09-22T19:02:03Z

Those functions are not needed during cache init and can be implemented in C. Only support the safe disabling of caches when this is required for booting an OS. Reenabling caches is much harder to implement if an optional coherency manager must be supported. As there is no real use-case anyway, dcache_enable is implemented with an error message. Signed-off-by: Daniel Schwierzeck

SPDX: Convert all of our single license tags to Linux Kernel style

2018-05-07T13:34:12Z

When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini

fdt: Implement weak arch_fixup_fdt()

2018-02-18T19:53:38Z

Only ARM and in some configs MIPS really implement arch_fixup_fdt(). Others just use the same boilerplate which is not good by itself, but what's worse if we try to build with disabled CONFIG_CMD_BOOTM and enabled CONFIG_OF_LIBFDT we'll hit an unknown symbol which was apparently implemented in arch/xxx/lib/bootm.c. Now with weak arch_fixup_fdt() right in image-fdt.c where it is used we get both items highlighted above fixed. Signed-off-by: Alexey Brodkin Cc: Daniel Schwierzeck Cc: Simon Glass Cc: York Sun Cc: Stefan Roese Reviewed-by: Tom Rini Reviewed-by: Daniel Schwierzeck

MIPS: Break out of cache loops for unimplemented caches

2017-11-28T20:59:30Z

If we run on a CPU which doesn't implement a particular cache then we would previously get stuck in an infinite loop, executing a cache op on the first "line" of the missing cache & then incrementing the address by 0. This was being avoided for the L2 caches, but not for the L1s. Fix this by generalising the check for a zero line size & avoiding the cache op loop when this is the case. Signed-off-by: Paul Burton Cc: Daniel Schwierzeck Cc: u-boot@lists.denx.de

MIPS: Clear instruction hazards in flush_cache()

2017-11-28T20:59:30Z

When writing code, for example during relocation, we ensure that the icache has a coherent view of the new instructions with a call to flush_cache(). This handles the bulk of the work to ensure the new instructions will execute as expected, however it does not ensure that the CPU pipeline doesn't already contain instructions taken from a stale view of the affected memory. This could theoretically be a problem for relocation, but in practice typically isn't because we sync caches for enough code after the entry point of the newly written code that by the time the CPU pipeline might possibly fetch any of it we'll have long ago written it back & invalidated any stale icache entries. This is however a problem for shorter regions of code. In preparation for later patches which write shorter segments of code, ensure any instruction hazards are cleared by flush_cache() by introducing & using a new instruction_hazard_barrier() function which makes use of the jr.hb instruction to clear the hazard. Signed-off-by: Paul Burton Cc: Daniel Schwierzeck Cc: u-boot@lists.denx.de