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<title>bcm63xx/u-boot/arch/mips/mach-mscc, branch master</title>
<subtitle>Broadcom-s U-Boot</subtitle>
<id>https://git.openwrt.org/project/bcm63xx/u-boot/atom?h=master</id>
<link rel='self' href='https://git.openwrt.org/project/bcm63xx/u-boot/atom?h=master'/>
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<updated>2019-05-03T14:42:23Z</updated>
<entry>
<title>net: mscc: ocelot: Update network driver for pcb120</title>
<updated>2019-05-03T14:42:23Z</updated>
<author>
<name>Horatiu Vultur</name>
</author>
<published>2019-04-24T09:27:57Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=6390da4a5770e59ac220c1b0412a66d2c861a547'/>
<id>urn:sha1:6390da4a5770e59ac220c1b0412a66d2c861a547</id>
<content type='text'>
Update Ocelot network driver to have support also for pcb120.

Signed-off-by: Horatiu Vultur &lt;horatiu.vultur@microchip.com&gt;
</content>
</entry>
<entry>
<title>MSCC: delete obsolete reference to MSCC_BITBANG_SPI_GPIO</title>
<updated>2019-05-03T14:42:23Z</updated>
<author>
<name>Robert P. J. Day</name>
</author>
<published>2019-04-17T20:13:45Z</published>
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<id>urn:sha1:feda3b44a999f25bcadaa8b345c740ea05c0bd22</id>
<content type='text'>
Remove "select MSCC_BITBANG_SPI_GPIO" since Kbuild option was deleted
back in commit ace9c103df2875d2b435dbd7b36618020edfd1c0:

  commit ace9c103df2875d2b435dbd7b36618020edfd1c0
  Author: Lars Povlsen &lt;lars.povlsen@microchip.com&gt;
  Date:   Tue Jan 8 10:38:35 2019 +0100

    mips: gpio: mscc: Obsoleted gpio-mscc-bitbang-spi.c
</content>
</entry>
<entry>
<title>mips: mscc: serval: Fix reset</title>
<updated>2019-05-03T14:42:23Z</updated>
<author>
<name>Horatiu Vultur</name>
</author>
<published>2019-04-15T09:56:36Z</published>
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<id>urn:sha1:72e224b864baa4905b9c5997223baa3e65725be7</id>
<content type='text'>
In case the ddr training was failing, it couldn't reset, it was just
hanging. Therefore reimplement it, so when ddr training is failing
it would call _machine_restart, which power downs the DDR and does
a force reset.

Signed-off-by: Horatiu Vultur &lt;horatiu.vultur@microchip.com&gt;
</content>
</entry>
<entry>
<title>net: Add MSCC ServalT network driver.</title>
<updated>2019-04-12T15:32:52Z</updated>
<author>
<name>Horatiu Vultur</name>
</author>
<published>2019-04-08T08:31:36Z</published>
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<id>urn:sha1:746f2d3e8bf4961b9f5558c21bc67a61b2b89eee</id>
<content type='text'>
Add network driver for Microsemi Ethernet switch.
It is present on ServalT SoCs.

Signed-off-by: Horatiu Vultur &lt;horatiu.vultur@microchip.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
</entry>
<entry>
<title>MSCC: Add board support for Serval SoC family.</title>
<updated>2019-01-23T17:28:09Z</updated>
<author>
<name>Horatiu Vultur</name>
</author>
<published>2019-01-23T15:39:45Z</published>
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<id>urn:sha1:a834cb817fb1a11607ea8e6394235843be079fdd</id>
<content type='text'>
Add board support and configuration for Jaguar2 SoC family.
The detection of the board type is based on the phy ids.

Signed-off-by: Horatiu Vultur &lt;horatiu.vultur@microchip.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
</entry>
<entry>
<title>MSCC: Add support for Serval SoC family.</title>
<updated>2019-01-23T17:28:09Z</updated>
<author>
<name>Horatiu Vultur</name>
</author>
<published>2019-01-23T15:39:42Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=1895b87e84d75272218a7db1d3454265fcf6e791'/>
<id>urn:sha1:1895b87e84d75272218a7db1d3454265fcf6e791</id>
<content type='text'>
As Ocelot, Servalt, Luton and Jaguar2, this family of SoCs are
found in Microsemi Switches solution.

Signed-off-by: Horatiu Vultur &lt;horatiu.vultur@microchip.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
</entry>
<entry>
<title>MSCC: Add support for Servalt SoC family.</title>
<updated>2019-01-23T17:27:26Z</updated>
<author>
<name>Horatiu Vultur</name>
</author>
<published>2019-01-17T14:33:27Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=055125171a39aecd5814bfb0c39233699338b647'/>
<id>urn:sha1:055125171a39aecd5814bfb0c39233699338b647</id>
<content type='text'>
As Ocelot, Luton and Jaguar2, this family of SoCs are found
in Microsemi Switches solution.

Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Signed-off-by: Horatiu Vultur &lt;horatiu.vultur@microchip.com&gt;
</content>
</entry>
<entry>
<title>MSCC: Add board support for Jaguar2 SOC family</title>
<updated>2019-01-16T12:56:43Z</updated>
<author>
<name>Horatiu Vultur</name>
</author>
<published>2019-01-12T17:57:00Z</published>
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<id>urn:sha1:c75c908316983eb729ce7e6449959dcabd58413b</id>
<content type='text'>
Add board support and configuration for Jaguar2 SOC family.
The detection of the board type in this family is based on the phy ids.

Signed-off-by: Horatiu Vultur &lt;horatiu.vultur@microchip.com&gt;
</content>
</entry>
<entry>
<title>MSCC: Add support for Jaguar2 SOC family</title>
<updated>2019-01-16T12:56:43Z</updated>
<author>
<name>Horatiu Vultur</name>
</author>
<published>2019-01-12T17:56:56Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=e7a0de2c317e75accfa53c2dd17f521462ccd830'/>
<id>urn:sha1:e7a0de2c317e75accfa53c2dd17f521462ccd830</id>
<content type='text'>
As the Ocelot and Luton SoCs, this family of SoCs are found
in Microsemi Switches solution.

Signed-off-by: Horatiu Vultur &lt;horatiu.vultur@microchip.com&gt;
</content>
</entry>
<entry>
<title>mips: spi: mscc: Add fast bitbang SPI driver</title>
<updated>2019-01-16T12:56:43Z</updated>
<author>
<name>Lars Povlsen</name>
</author>
<published>2019-01-08T09:38:33Z</published>
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<id>urn:sha1:fd6e0b05252dd20579129d420442ef017287e89d</id>
<content type='text'>
This patch add a new SPI driver for MSCC SOCs that does not sport the
designware SPI hardware controller.

Performance gain: 7.664 seconds vs. 17.633 for 1 Mbyte write.

Signed-off-by: Lars Povlsen &lt;lars.povlsen@microchip.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
</entry>
</feed>
