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<title>bcm63xx/u-boot/arch/mips, branch master</title>
<subtitle>Broadcom-s U-Boot</subtitle>
<id>https://git.openwrt.org/project/bcm63xx/u-boot/atom?h=master</id>
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<updated>2019-07-05T15:12:27Z</updated>
<entry>
<title>mips: mt76xx: Implement new d-cache fix in last_stage_init()</title>
<updated>2019-07-05T15:12:27Z</updated>
<author>
<name>Stefan Roese</name>
</author>
<published>2019-05-28T06:11:37Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=9814fb272f59fc07c0856a6e034e34b361cade18'/>
<id>urn:sha1:9814fb272f59fc07c0856a6e034e34b361cade18</id>
<content type='text'>
With commit 06985289d452 ("watchdog: Implement generic watchdog_reset()
version") the init sequence has changed in arch_misc_init(), resulting
in a re-appearance of the d-cache issue on MT7688 boards (e.g. gardena).
When this happens, the first (or sometimes later ones as well) TFTP
command hangs and does not complete correctly. This leads to the
assumption that the d-cache is not in a clean state once the ethernet
driver is called (d-cache is used here for the buffers). The old work-
around with the cache flush somehow does not work any more now with
the new code change.

Unfortunately adding CONFIG_SYS_MALLOC_CLEAR_ON_INIT also did not fix
this issue. With v2019.07-rc3 it shows again. The time of accessing
the data seems to be very important here. It needs to be "very late"
in the boot process.

Testing has shown, that copying a 64KiB area in DDR at a very late
bootup time, directly before calling into the prompt, fixes this issue.
Flushing of the complete d-cache does not seem to necessary, as this
copy alone seems to fix this problem.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
</entry>
<entry>
<title>mips: mt76xx: Remove cache workaround and select SYS_MALLOC_CLEAR_ON_INIT</title>
<updated>2019-05-24T13:55:17Z</updated>
<author>
<name>Stefan Roese</name>
</author>
<published>2019-05-23T05:55:54Z</published>
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<id>urn:sha1:f913eab9b95c01c96b9e17eba853a99eb8ddb41a</id>
<content type='text'>
With commit 06985289d452 ("watchdog: Implement generic watchdog_reset()
version") the init sequence has changed in arch_misc_init(), resulting
in a re-appearance of the d-cache issue on MT7688 boards (e.g. gardena).
When this happens, the first (or sometimes later ones as well) TFTP
command hangs and does not complete correctly. This leads to the
assumption that the d-cache is not in a clean state once the ethernet
driver is called (d-cache is used here for the buffers). The old work-
around with the cache flush somehow does not work any more now with
the new code change.

To fix this issue, this patch now removes the old workaround and selects
CONFIG_SYS_MALLOC_CLEAR_ON_INIT for ARCH_MTMIPS. With this option the
complete malloc area is initialized with zeros (cache lines are touched).
Testing has shown that this also fixes the issue on the MT7688 boards.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Suggested-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Cc: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
</entry>
<entry>
<title>net: mscc: ocelot: Update DTS for Luton pcb90</title>
<updated>2019-05-03T14:46:36Z</updated>
<author>
<name>Horatiu Vultur</name>
</author>
<published>2019-05-01T11:17:00Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=5c629b1b69f780540e6e3bcc57d29438749f97c5'/>
<id>urn:sha1:5c629b1b69f780540e6e3bcc57d29438749f97c5</id>
<content type='text'>
Update device tree for luton to add support for luton pcb90.
This pcb has 24 ports from which 12 ports are connected to
SerDes6G.

Signed-off-by: Horatiu Vultur &lt;horatiu.vultur@microchip.com&gt;
</content>
</entry>
<entry>
<title>mips: rename mach-mt7620 to mach-mtmips</title>
<updated>2019-05-03T14:43:11Z</updated>
<author>
<name>Weijie Gao</name>
</author>
<published>2019-04-30T03:13:58Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=16b94903e2462a8983322bbc865c0617b9e02b79'/>
<id>urn:sha1:16b94903e2462a8983322bbc865c0617b9e02b79</id>
<content type='text'>
Currently mach-mt7620 contains only support for mt7628. To avoid confusion,
rename mach-mt7620 to mach-mtmips, which means MediaTek MIPS platforms.
MT7620 and MT7628 should be distinguished by SOC_MT7620 and SOC_MT7628
because they do not share the same lowlevel codes.

Dependencies of four drivers are changed to SOC_MT7628 as these drivers
are only used by MT7628.

Cc: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
Reviewed-by: Stefan Roese &lt;sr@denx.de&gt;
Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</content>
</entry>
<entry>
<title>net: mscc: ocelot: Update DTS for Ocelot pcb120.</title>
<updated>2019-05-03T14:42:24Z</updated>
<author>
<name>Horatiu Vultur</name>
</author>
<published>2019-04-24T09:27:59Z</published>
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<id>urn:sha1:8c211af8f8c0617c40ccf4f0df557e4fbf6073ea</id>
<content type='text'>
Update device tree for ocelot to add support for ocelot pcb120.

Signed-off-by: Horatiu Vultur &lt;horatiu.vultur@microchip.com&gt;
</content>
</entry>
<entry>
<title>net: mscc: ocelot: Update network driver for pcb120</title>
<updated>2019-05-03T14:42:23Z</updated>
<author>
<name>Horatiu Vultur</name>
</author>
<published>2019-04-24T09:27:57Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=6390da4a5770e59ac220c1b0412a66d2c861a547'/>
<id>urn:sha1:6390da4a5770e59ac220c1b0412a66d2c861a547</id>
<content type='text'>
Update Ocelot network driver to have support also for pcb120.

Signed-off-by: Horatiu Vultur &lt;horatiu.vultur@microchip.com&gt;
</content>
</entry>
<entry>
<title>arch: mips: Update initrd_start and initrd_end</title>
<updated>2019-05-03T14:42:23Z</updated>
<author>
<name>Horatiu Vultur</name>
</author>
<published>2019-04-24T15:21:29Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=6943cc9732202b9c65990cff9f74cea6b8173e09'/>
<id>urn:sha1:6943cc9732202b9c65990cff9f74cea6b8173e09</id>
<content type='text'>
Microsemi SoC defines CONFIG_SYS_SDRAM_BASE to be 0x80000000, which
represents the start of kseg0 and represents a virtual address. Meaning
that the initrd_start and initrd_end point somewhere kseg0.
When these parameters are passed to linux kernel through DT
they are pointing somewhere in kseg0 which is a virtual address but linux
kernel expects the addresses to be physical addresses(in kuseg) because
it is converting the physical address to a virtual one.

Therefore update the uboot to pass the physical address of initrd_start
and initrd_end by converting them using the function virt_to_phys before
setting up the DT.

Signed-off-by: Horatiu Vultur &lt;horatiu.vultur@microchip.com&gt;
Reviewed-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
</entry>
<entry>
<title>MSCC: delete obsolete reference to MSCC_BITBANG_SPI_GPIO</title>
<updated>2019-05-03T14:42:23Z</updated>
<author>
<name>Robert P. J. Day</name>
</author>
<published>2019-04-17T20:13:45Z</published>
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<id>urn:sha1:feda3b44a999f25bcadaa8b345c740ea05c0bd22</id>
<content type='text'>
Remove "select MSCC_BITBANG_SPI_GPIO" since Kbuild option was deleted
back in commit ace9c103df2875d2b435dbd7b36618020edfd1c0:

  commit ace9c103df2875d2b435dbd7b36618020edfd1c0
  Author: Lars Povlsen &lt;lars.povlsen@microchip.com&gt;
  Date:   Tue Jan 8 10:38:35 2019 +0100

    mips: gpio: mscc: Obsoleted gpio-mscc-bitbang-spi.c
</content>
</entry>
<entry>
<title>net: mscc: serval: Add ethernet nodes for Serval</title>
<updated>2019-05-03T14:42:23Z</updated>
<author>
<name>Horatiu Vultur</name>
</author>
<published>2019-04-11T12:11:34Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=4788704dd803ca7122710d9daf0ca4b337745dfc'/>
<id>urn:sha1:4788704dd803ca7122710d9daf0ca4b337745dfc</id>
<content type='text'>
Add ethernet nodes for Serval SoCs family. There are 2 pcb in this
family: pcb105 and pcb106.

Signed-off-by: Horatiu Vultur &lt;horatiu.vultur@microchip.com&gt;
</content>
</entry>
<entry>
<title>mips: mscc: serval: Fix reset</title>
<updated>2019-05-03T14:42:23Z</updated>
<author>
<name>Horatiu Vultur</name>
</author>
<published>2019-04-15T09:56:36Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=72e224b864baa4905b9c5997223baa3e65725be7'/>
<id>urn:sha1:72e224b864baa4905b9c5997223baa3e65725be7</id>
<content type='text'>
In case the ddr training was failing, it couldn't reset, it was just
hanging. Therefore reimplement it, so when ddr training is failing
it would call _machine_restart, which power downs the DDR and does
a force reset.

Signed-off-by: Horatiu Vultur &lt;horatiu.vultur@microchip.com&gt;
</content>
</entry>
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