bcm63xx/u-boot/arch/powerpc/cpu/mpc85xx/release.S, branch master

powerpc: mpc85xx: Improve Work-around for Erratum A005125

2018-05-09T14:17:51Z

Work-around for Erratum A005125 must be applied to all cores. Signed-off-by: Yoshihisa Morizumi Signed-off-by: Takuma Ueba Reviewed-by: York Sun

SPDX: Convert all of our single license tags to Linux Kernel style

2018-05-07T13:34:12Z

When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini

powerpc: mpc85xx: Implement CPU erratum A-007907 for secondary cores

2017-10-23T21:02:48Z

Commit 06ad970b53a3 ("powerpc: mpc85xx: Implemente workaround for CPU erratum A-007907") clears L1CSR2 for the boot core, but other cores don't run through the workaround. Add similar code for secondary cores to clear DCSTASHID field in L1CSR2 register. Signed-off-by: York Sun

remove unnecessary version.h includes

2015-03-24T14:50:50Z

Various files are needlessly rebuilt every time due to the version and build time changing. As version.h is not actually needed, remove the include. Signed-off-by: Rob Herring Cc: Albert Aribaud Cc: Stefano Babic Cc: Minkyu Kang Cc: Marek Vasut Cc: Tom Warren Cc: Michal Simek Cc: Macpaul Lin Cc: Wolfgang Denk Cc: York Sun Cc: Stefan Roese Cc: Nobuhiro Iwamatsu Cc: Simon Glass Cc: Philippe Reynes Cc: Eric Jarrige Cc: "David Müller" Cc: Phil Edworthy Cc: Robert Baldyga Cc: Torsten Koschorrek Cc: Anatolij Gustschin Reviewed-by: Linus Walleij Reviewed-by: Łukasz Majewski

PPC: 85xx: Remove IVOR reset

2014-04-23T00:58:45Z

There is no need to set IVORs to anything but their default values, so let's leave them where they are. Suggested-by: Scott Wood Signed-off-by: Alexander Graf Acked-by: Scott Wood [York Sun: Add back $(obj)start.S section in mpc8572ds/Makefile] Reviewed-by: York Sun

Remove obsolete _LINUX_CONFIG_H macro

2014-01-24T21:59:07Z

Commit 643aae1406c93ddc64fcf8c136b47cdffd9c8ccd deleted include/linux/config.h but missed to delete _LINUX_CONFIG_H macro. It is no longer used at all. Signed-off-by: Masahiro Yamada

powerpc/mpc85xx: Workaround for A-005812

2013-08-09T19:41:40Z

Erratum A-005812 Incorrect reservation clearing in Write Shadow mode can result in invalid atomic operations. For u-boot, this erratum only impacts SoCs running in write shadow mode. Signed-off-by: York Sun

Add GPL-2.0+ SPDX-License-Identifier to source files

2013-07-24T13:44:38Z

Signed-off-by: Wolfgang Denk [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini

powerpc/chassis2: Change core numbering scheme

2013-05-24T21:54:11Z

To align with chassis generation 2 spec, all cores are numbered in sequence. The cores may reside across multiple clusters. Each cluster has zero to four cores. The first available core is numbered as core 0. The second available core is numbered as core 1 and so on. Core clocks are generated by each clusters. To identify the cluster of each core, topology registers are examined. Cluster clock registers are reorganized to be easily indexed. Signed-off-by: York Sun Signed-off-by: Andy Fleming

powerpc/mpc85xx: Fix PIR parsing for chassis2

2013-05-14T21:00:29Z

The PIR parsing algorithm we used is not only for E6500. It applies to all SoCs with chassis 2. Signed-off-by: York Sun Signed-off-by: Andy Fleming