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<title>bcm63xx/u-boot/arch/riscv/cpu/generic/cpu.c, branch master</title>
<subtitle>Broadcom-s U-Boot</subtitle>
<id>https://git.openwrt.org/project/bcm63xx/u-boot/atom?h=master</id>
<link rel='self' href='https://git.openwrt.org/project/bcm63xx/u-boot/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/'/>
<updated>2019-02-27T01:12:33Z</updated>
<entry>
<title>riscv: Rename cpu/qemu to cpu/generic</title>
<updated>2019-02-27T01:12:33Z</updated>
<author>
<name>Anup Patel</name>
</author>
<published>2019-02-25T08:14:10Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=fdff1f96a6505bccb258f5b52e6c94c7e0b29512'/>
<id>urn:sha1:fdff1f96a6505bccb258f5b52e6c94c7e0b29512</id>
<content type='text'>
The QEMU CPU support under arch/riscv is pretty much generic
and works fine for SiFive Unleashed as well. In fact, there
will be quite a few RISC-V SOCs for which QEMU CPU support
will work fine.

This patch renames cpu/qemu to cpu/generic to indicate the
above fact. If there are SOC specific errata workarounds
required in cpu/generic then those can be done at runtime
in cpu/generic based on CPU vendor specific DT compatible
string.

Signed-off-by: Anup Patel &lt;anup.patel@wdc.com&gt;
Reviewed-by: Alexander Graf &lt;agraf@suse.de&gt;
Reviewed-by: Lukas Auer &lt;lukas.auer@aisec.fraunhofer.de&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
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</entry>
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