bcm63xx/u-boot/arch/riscv/cpu/start.S, branch master

riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled

2019-05-09T08:46:46Z

This patch will fix prior_stage_fdt_address write failure problem, when AE350 boots from flash. When AE350 boots from flash, prior_stage_fdt_address will be flash address, we shall avoid it to be written. Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Bin Meng Reviewed-by: Lukas Auer

riscv: Introduce CONFIG_XIP to support booting from flash

2019-05-09T08:46:46Z

When U-Boot boots from flash, during the boot process, hart_lottery and available_harts_lock variable addresses point to flash which is not writable. This causes boot failures on AE350. Introduce a config option CONFIG_XIP to support such configuration. Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Lukas Auer Reviewed-by: Bin Meng

riscv: hang if relocation of secondary harts fails

2019-04-08T01:44:26Z

Print an error message and hang if smp_call_function() returns an error, indicating that relocation of the secondary harts has failed. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Anup Patel

riscv: do not rely on hart ID passed by previous boot stage

2019-04-08T01:44:26Z

RISC-V U-Boot expects the hart ID to be passed to it via register a0 by the previous boot stage. Machine mode firmware such as BBL and OpenSBI do this when starting their payload (U-Boot) in supervisor mode. If U-Boot is running in machine mode, this task must be handled by the boot ROM. Explicitly populate register a0 with the hart ID from the mhartid CSR to avoid possible problems on RISC-V processors with a boot ROM that does not handle this task. Suggested-by: Rick Chen Signed-off-by: Lukas Auer Reviewed-by: Anup Patel Reviewed-by: Atish Patra Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Rick Chen Tested-by: Rick Chen

riscv: add support for multi-hart systems

2019-04-08T01:44:26Z

On RISC-V, all harts boot independently. To be able to run on a multi-hart system, U-Boot must be extended with the functionality to manage all harts in the system. All harts entering U-Boot are registered in the available_harts mask stored in global data. A hart lottery system as used in the Linux kernel selects the hart U-Boot runs on. All other harts are halted. U-Boot can delegate functions to them using smp_call_function(). Every hart has a valid pointer to the global data structure and a 8KiB stack by default. The stack size is set with CONFIG_STACK_SIZE_SHIFT. Signed-off-by: Lukas Auer Reviewed-by: Anup Patel Reviewed-by: Bin Meng Tested-by: Bin Meng

riscv: save hart ID in register tp instead of s0

2019-04-08T01:44:26Z

The hart ID passed by the previous boot stage is currently stored in register s0. If we divert the control flow inside a function, which is required as part of multi-hart support, the function epilog may not be called, clobbering register s0. Save the hart ID in the unallocatable register tp instead to protect the hart ID. Signed-off-by: Lukas Auer Reviewed-by: Bin Meng Reviewed-by: Rick Chen Reviewed-by: Anup Patel

riscv: delay initialization of caches and debug UART

2019-04-08T01:44:26Z

Move the initialization of the caches and the debug UART until after board_init_f_init_reserve. This is in preparation for SMP support, where code prior to this point will be executed by all harts. This ensures that initialization will only be performed once on the main hart running U-Boot. Signed-off-by: Lukas Auer Reviewed-by: Anup Patel Reviewed-by: Bin Meng

riscv: Save boot hart id to the global data

2018-12-18T01:56:27Z

At present the hart id passed via a0 in the U-Boot entry is saved to s0 at the beginning but does not preserve later. Save it to the global data structure so that it can be used later. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer Reviewed-by: Anup Patel

riscv: Move trap handler codes to mtrap.S

2018-12-18T01:56:27Z

Currently the M-mode trap handler codes are in start.S. For future extension, move them to a separate file mtrap.S. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer Reviewed-by: Anup Patel

riscv: ax25-ae350: Pass dtb address to u-boot with a1 register

2018-12-05T06:14:16Z

ax25-ae350 use CONFIG_OF_BOARD via a2 and CONFIG_SYS_SDRAM_BASE to boot from ram which allow the board to override the fdt address originally. But after this patch riscv: save hart ID and device tree passed by prior boot stage It provide prior_stage_fdt_address which offer a temporary memory address to keep the dtb address passing from loader(gdb) to u-boot with a1. So passing via a2 and CONFIG_SYS_SDRAM_BASE is redundant and can be removed. And it also somehow may corrupted BBL if it was be arranged in CONFIG_SYS_SDRAM_BASE. In board_fdt_blob_setup() When boting from ram: prior_stage_fdt_address will be use to reserved dtb temporarily. When booting from ROM: dtb will be pre-burned in CONFIG_SYS_FDT_BASE, if it is flash base. Or CONFIG_SYS_FDT_BASE maybe a memory map space (NOT RAM or ROM) which is provided by HW. Signed-off-by: Rick Chen Cc: Greentime Hu