bcm63xx/u-boot/arch/riscv, branch master

riscv: Add Microchip MPFS Icicle board support

2019-06-05T05:19:24Z

This patch adds Microchip MPFS Icicle board support. For now, NS16550 serial driver is only enabled. The Microchip MPFS Icicle defconfig by default builds U-Boot for M-Mode with SMP support. Signed-off-by: Padmarao Begari Reviewed-by: Bin Meng Reviewed-by: Lukas Auer

CONFIG_SPL_SYS_[DI]CACHE_OFF: add

2019-05-18T12:15:35Z

While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by: Alexey Brodkin Signed-off-by: Trevor Woerner [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by: Tom Rini

CONFIG_SYS_[DI]CACHE_OFF: convert to Kconfig

2019-05-18T12:15:34Z

CONFIG_SYS_[DI]CACHE_OFF had been partially converted to Kconfig parameters; only for the ARC architecture. This patch turns these two parameters into Kconfig items everywhere else they are found. All of the include/configs/* and defconfig changes in this patch are for arm machines only. The Kconfig changes for arc, nds32, riscv, and xtensa have been included since these symbols are found in code under arch/{arc,nds32,riscv,xtensa}, however, no currently-defined include/configs/* or defconfigs for these architectures exist which include these symbols. These results have been confirmed with tools/moveconfig.py. Acked-by: Alexey Brodkin Signed-off-by: Trevor Woerner [trini: Re-migrate for a few more boards] Signed-off-by: Tom Rini

RISCV: image: Add booti support

2019-05-09T08:47:52Z

This patch adds booti support for RISC-V Linux kernel. The existing bootm method will also continue to work as it is. It depends on the following kernel patch which adds the header to the flat Image. Gzip compressed Image (Image.gz) support is not enabled with this patch. https://patchwork.kernel.org/patch/10925543/ Tested on HiFive Unleashed and QEMU. Signed-off-by: Atish Patra Reviewed-by: Tom Rini Tested-by: Karsten Merker Reviewed-by: Marek Vasut

riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled

2019-05-09T08:46:46Z

This patch will fix prior_stage_fdt_address write failure problem, when AE350 boots from flash. When AE350 boots from flash, prior_stage_fdt_address will be flash address, we shall avoid it to be written. Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Bin Meng Reviewed-by: Lukas Auer

riscv: Introduce CONFIG_XIP to support booting from flash

2019-05-09T08:46:46Z

When U-Boot boots from flash, during the boot process, hart_lottery and available_harts_lock variable addresses point to flash which is not writable. This causes boot failures on AE350. Introduce a config option CONFIG_XIP to support such configuration. Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Lukas Auer Reviewed-by: Bin Meng

dts: switch spi-flash to jedec, spi-nor compatible

2019-04-12T05:24:27Z

There is no reason not to use the Linux "jedec,spi-nor" binding in U-Boot dts files. This compatible has been added in sf_probe, let use it. This patch switches to jedec,spi-nor when spi-flash is used in the DTS and DTSI files, and removed spi-flash when jedec,spi-nor is already present. The x86 dts are switched in a separate commit since it depends on a change in fdtdec. Signed-off-by: Neil Armstrong Acked-by: Stefan Roese Reviewed-by: Simon Goldschmidt Reviewed-by: Evgeniy Paltsev Reviewed-by: Rick Chen Reviewed-by: Patrick Delaunay Reviewed-by: Jagan Teki

riscv: dts: fix CONFIG_DEFAULT_DEVICE_TREE failure

2019-04-08T01:46:00Z

It occurs since commit 27cb7300ffda ("Ensure device tree DTS is compiled"). More details can refer to 89c2b5c02049aea746b1edee0b4e1d8519dec2f4 ARM: fix arch/arm/dts/Makefile Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Bin Meng Reviewed-by: Lukas Auer

riscv: dts: ae350 support SMP

2019-04-08T01:45:08Z

Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Bin Meng Reviewed-by: Lukas Auer

riscv: ax25: Andes specific cache shall only support in M-mode

2019-04-08T01:45:08Z

Limit the cache configuration only can be supported in M mode. It can not be manipulated in S mode. Signed-off-by: Rick Chen Cc: Greentime Hu Reviewed-by: Bin Meng Reviewed-by: Lukas Auer