<feed xmlns='http://www.w3.org/2005/Atom'>
<title>bcm63xx/u-boot/arch/x86/lib, branch master</title>
<subtitle>Broadcom-s U-Boot</subtitle>
<id>https://git.openwrt.org/project/bcm63xx/u-boot/atom?h=master</id>
<link rel='self' href='https://git.openwrt.org/project/bcm63xx/u-boot/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/'/>
<updated>2019-06-22T14:26:22Z</updated>
<entry>
<title>x86: Revert "Don't set up MTRRs in SPL"</title>
<updated>2019-06-22T14:26:22Z</updated>
<author>
<name>Andy Shevchenko</name>
</author>
<published>2019-06-18T16:06:34Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=7ce74b70b9ac23276a47cc86c26028b6b6009c2f'/>
<id>urn:sha1:7ce74b70b9ac23276a47cc86c26028b6b6009c2f</id>
<content type='text'>
This breaks Intel Edison to work. It gets laggish and unable to boot kernel.

Reverts commit 665cb18ea64aabbeb03d27a4c92ddec1baccb87a for now
till better solution will be proposed.

Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Acked-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>Fix spelling of available.</title>
<updated>2019-05-09T23:52:55Z</updated>
<author>
<name>Vagrant Cascadian</name>
</author>
<published>2019-05-03T22:28:37Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=048a92ea54355756292aa49a4cf88518a98ec37a'/>
<id>urn:sha1:048a92ea54355756292aa49a4cf88518a98ec37a</id>
<content type='text'>
Signed-off-by: Vagrant Cascadian &lt;vagrant@debian.org&gt;
</content>
</entry>
<entry>
<title>x86: Add a simple TPL implementation</title>
<updated>2019-05-08T05:02:18Z</updated>
<author>
<name>Simon Glass</name>
</author>
<published>2019-05-02T16:52:12Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=7c03caf6fac19cfef049ec84d813e87481d48d69'/>
<id>urn:sha1:7c03caf6fac19cfef049ec84d813e87481d48d69</id>
<content type='text'>
Add the required CPU code so that TPL builds correctly. Also update the
SPL code to deal with being booted from TPL.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Don't generate a bootstage report in SPL</title>
<updated>2019-05-08T05:02:16Z</updated>
<author>
<name>Simon Glass</name>
</author>
<published>2019-04-26T03:59:07Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=bf4d8beb126788bfd71da2645c26987516c26d10'/>
<id>urn:sha1:bf4d8beb126788bfd71da2645c26987516c26d10</id>
<content type='text'>
This report is normally generated by U-Boot proper. Correct the condition
here so that it respects the Kconfig options for bootstage.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Don't set up MTRRs in SPL</title>
<updated>2019-05-08T05:02:16Z</updated>
<author>
<name>Simon Glass</name>
</author>
<published>2019-04-26T03:59:06Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=665cb18ea64aabbeb03d27a4c92ddec1baccb87a'/>
<id>urn:sha1:665cb18ea64aabbeb03d27a4c92ddec1baccb87a</id>
<content type='text'>
The MTRRs are normally set up in U-Boot proper, so avoid setting them up
in SPL as well.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: mrccache: Add more debugging</title>
<updated>2019-05-08T05:02:14Z</updated>
<author>
<name>Simon Glass</name>
</author>
<published>2019-04-26T03:58:59Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=079b38ba0485eb745cdcdac7e74986d77d2c13e2'/>
<id>urn:sha1:079b38ba0485eb745cdcdac7e74986d77d2c13e2</id>
<content type='text'>
When the MRC cache fails to save it is useful to have some debugging info
to indicate what when wrong. Add some more debug() calls.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Support saving MRC data from SPL</title>
<updated>2019-05-08T05:02:14Z</updated>
<author>
<name>Simon Glass</name>
</author>
<published>2019-04-26T03:58:57Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=9a67994e0132f0a078de6ab7c11a049dbb5c365c'/>
<id>urn:sha1:9a67994e0132f0a078de6ab7c11a049dbb5c365c</id>
<content type='text'>
When SPL is used to set up the memory controller we want to save the MRC
data in SPL to avoid needing to pass it up to U-Boot proper to save. Add a
function to handle that.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Update a stale comment about ifdtool</title>
<updated>2019-05-08T05:02:10Z</updated>
<author>
<name>Simon Glass</name>
</author>
<published>2019-04-26T03:58:44Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=11b7cc37f15ae0f27987da5a037e6603e068f20c'/>
<id>urn:sha1:11b7cc37f15ae0f27987da5a037e6603e068f20c</id>
<content type='text'>
We use binman to build the x86 image now. Update a comment which still
refers to ifdtool.

Signed-off-by: Simon Glass &lt;sjg@chromium.org&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Make sure i8254 is setup correctly before generating beeps</title>
<updated>2019-03-11T14:55:01Z</updated>
<author>
<name>Bin Meng</name>
</author>
<published>2019-02-26T09:52:19Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=7d0a53a40cee6e40c173b782f26f5a2317cf39b5'/>
<id>urn:sha1:7d0a53a40cee6e40c173b782f26f5a2317cf39b5</id>
<content type='text'>
The i8254 timer control IO port (0x43) should be setup correctly
by using PIT counter 2 to generate beeps, however in U-Boot other
codes like TSC driver utilizes PIT for TSC frequency calibration
and configures the counter 2 to a different mode that does not
beep. Fix this by always ensuring the PIT counter 2 is correctly
initialized so that the i8254 beeper driver works as expected.

Signed-off-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>x86: acpi: Not every platform has serial console a first device</title>
<updated>2019-03-10T00:17:00Z</updated>
<author>
<name>Andy Shevchenko</name>
</author>
<published>2019-02-28T15:19:54Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=edf18a83f8dc993279947cfc7faaba7dedf1ad82'/>
<id>urn:sha1:edf18a83f8dc993279947cfc7faaba7dedf1ad82</id>
<content type='text'>
We may not do an assumption that current console device is always a first
of UCLASS_SERIAL one.

For example, on properly described Intel Edison board the console UART
is a third one.

Use current serial device as described in global data.

Fixes: a61cbad78e67 ("dm: serial: Adjust serial_getinfo() to use proper API")
Cc: Simon Glass &lt;sjg@chromium.org&gt;
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Reviewed-by: Bin Meng &lt;bmeng.cn@gmail.com&gt;
</content>
</entry>
</feed>
