bcm63xx/u-boot/arch/x86, branch masterBroadcom-s U-Boothttps://git.openwrt.org/project/bcm63xx/u-boot/atom?h=master2019-06-22T14:27:13Zwatchdog: tangier: Convert to use WDT class2019-06-22T14:27:13ZAndy Shevchenko2019-06-21T10:28:08Zurn:sha1:c974a3d1550557f246c98480083651c0a502e7e7
Convert legacy driver to use watchdog class.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Stefan Roese <sr@denx.de>
x86: Revert "Don't set up MTRRs in SPL"2019-06-22T14:26:22ZAndy Shevchenko2019-06-18T16:06:34Zurn:sha1:7ce74b70b9ac23276a47cc86c26028b6b6009c2f
This breaks Intel Edison to work. It gets laggish and unable to boot kernel.
Reverts commit 665cb18ea64aabbeb03d27a4c92ddec1baccb87a for now
till better solution will be proposed.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
x86: coreboot: make it possible to process unhandled tags2019-05-19T08:17:33ZChristian Gmeiner2019-04-17T12:42:05Zurn:sha1:b52e9f0cb748d2a2ae26db62072294b9cccdb86f
coreboot makes it possible to add own entries into coreboot's
table at a per mainboard basis. As there might be some custom
ones it makes sense to provide a way to process them.
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Fix spelling of available.2019-05-09T23:52:55ZVagrant Cascadian2019-05-03T22:28:37Zurn:sha1:048a92ea54355756292aa49a4cf88518a98ec37a
Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
x86: samus: Update device tree for verified boot2019-05-08T05:02:19ZSimon Glass2019-05-08T03:41:14Zurn:sha1:3dc13cc3a05643a8764f9f455fff54f45b0fcd14
Add nvdata drivers for the TPM and RTC as used on samus. These are needed
for Chromium OS verified boot on samus.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
x86: samus: Update device tree for SPL2019-05-08T05:02:19ZSimon Glass2019-05-08T03:41:13Zurn:sha1:969ed0124289f89421b3bf36b1055ca93d900203
Add tags to allow required nodes to be present in SPL / TPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
x86: Add a simple TPL implementation2019-05-08T05:02:18ZSimon Glass2019-05-02T16:52:12Zurn:sha1:7c03caf6fac19cfef049ec84d813e87481d48d69
Add the required CPU code so that TPL builds correctly. Also update the
SPL code to deal with being booted from TPL.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
x86: Add a way to jump from TPL to SPL2019-05-08T05:02:18ZSimon Glass2019-05-02T16:52:27Zurn:sha1:49dffb7a074e9b9d2c27a303798c0e6bc5eea3ba
When TPL finishes it needs to jump to SPL with the stack set up correctly.
Add a function to handle this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
x86: broadwell: Update PCH to work in TPL2019-05-08T05:02:18ZSimon Glass2019-05-02T16:52:26Zurn:sha1:bfeeb8d863de070b1f9a2cf17f5e491557c5ecb5
The early init should only happen once. Update the probe method to
deal with TPL, SPL and U-Boot proper.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
x86: Fix device-tree indentation2019-05-08T05:02:17ZSimon Glass2019-05-02T16:52:21Zurn:sha1:e766d9f1835e6ad6a2a3080c4abb2e5175b156e8
With the use of a phandle we can outdent the device tree nodes a little.
Fix this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>