bcm63xx/u-boot/board/dhelectronics, branch master

ARM: imx: dh-imx6: Convert SPI support to DM

2019-06-11T08:42:48Z

Enable DM SPI and SF support on DHCOM iMX6 PDK2. Convert board code to match the DM support. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Ludwig Zenz Cc: Stefano Babic

ARM: imx: dh-imx6: Convert SATA support to DM

2019-06-11T08:42:48Z

Enable DM SATA support on DHCOM iMX6 PDK2. Convert board code to match the DM support. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Ludwig Zenz Cc: Stefano Babic

ARM: imx: dh-imx6: Convert SD/MMC support to DM

2019-06-11T08:42:48Z

Enable DM block and DM MMC support on DHCOM iMX6 PDK2. Convert board code to match the DM support. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Ludwig Zenz Cc: Stefano Babic

ARM: imx: dh-imx6: Enable DM GPIO

2019-06-11T08:42:48Z

Enable DM GPIO support on DHCOM iMX6 PDK2 and fix up board code where applicable. Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Ludwig Zenz Cc: Stefano Babic

ARM: imx6: DHCOM i.MX6 PDK: use Kconfig for inclusion of DDR calibration

2019-04-25T17:16:24Z

The four x16 DDR3 are wired in T-topology. From NXP AN4467: 'Although not required, T-Topologies may also benefit from performing Write Leveling as there are package delays on both the processor and DDR devices that can be de-skewed by performing Write Leveling. Therefore, Freescale recommends determining Write Leveling calibration parameters for all boards, regardless of topology used.' That is why write level calibration is also done. Signed-off-by: Ludwig Zenz

ARM: imx6: update 1GB DDR3 calibration for DHCOM i.MX6qd PDK

2019-04-25T17:16:24Z

The existing calibration values were found to be incorrect in comparison to newly determined values. The new values were generated with the help of 5 boards. They have been determined with the NXP Utility 'DDR Stress Test (2.9.0)'. Signed-off-by: Ludwig Zenz

ARM: imx6: DHCOM i.MX6 PDK: ddr init for 32bit bus and 4GBit chips

2018-07-23T09:02:14Z

Support 1GIB + 2GIB DDR3 with 64bit bus width and 512MIB + 1GIB with 32bit bus width Signed-off-by: Ludwig Zenz

ARM: imx6: configure ddrcode pins in spl DHCOM i.MX6 PDK

2018-07-23T09:02:03Z

Preperation for conditional DDR3 initialization based on GPIO codes. Signed-off-by: Ludwig Zenz

Revert "ARM: imx6: Disable DDR DRAM calibration DHCOM i.MX6 PDK"

2018-07-23T09:01:41Z

This reverts commit a637fe6f27fd4c19ef9f43a5f871c244581422ac. The DDR DRAM calibration was enhanced by write leveling correction code. It can be used with T-topology now. Signed-off-by: Ludwig Zenz

SPDX: Convert all of our single license tags to Linux Kernel style

2018-05-07T13:34:12Z

When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini