Broadcom-s U-Boot https://git.openwrt.org/project/bcm63xx/u-boot/atom?h=master 2019-06-11T08:42:48Z 2019-06-11T08:42:48Z Parthiban Nallathambi 2019-04-10T14:35:32Z urn:sha1:d2d1191843e4265a1228a2f2b319f9cd31854de2 Extend PHYTEC phyBOARD-i.MX6UL for phyCORE-i.MX6UL SoM (PCL063) with eMMC on SoM. CPU: Freescale i.MX6ULL rev1.0 792 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 38C Reset cause: POR Model: Phytec phyBOARD-i.MX6ULL-Segin SBC Board: PHYTEC phyCORE-i.MX6ULL DRAM: 256 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial@02020000 Out: serial@02020000 Err: serial@02020000 Net: FEC0 Working: - Eth0 - i2C - MMC/SD - eMMC - UART (1 & 5) - USB (host & otg) Signed-off-by: Parthiban Nallathambi <parthitce@gmail.com> 2019-06-11T08:42:48Z Parthiban Nallathambi 2019-04-07T18:32:42Z urn:sha1:a443c8212c204372ac1c374010055f6690ede7b9 u-boot,dm-spl property is specific to U-Boot, so created one for i.MX6ULL platforms. Signed-off-by: Parthiban Nallathambi <parthitce@gmail.com> 2019-01-28T11:47:27Z Martyn Welch 2018-12-11T11:34:46Z urn:sha1:0963060c9912c404280e5540018d02777b3400af Port for the PHYTEC phyBOARD-i.MX6UL-Segin single board computer. Based on the PHYTEC phyCORE-i.MX6UL SOM (PCL063). CPU: Freescale i.MX6UL rev1.2 528 MHz (running at 396 MHz) CPU: Industrial temperature grade (-40C to 105C) at 44C Reset cause: POR Board: PHYTEC phyCORE-i.MX6UL I2C: ready DRAM: 256 MiB NAND: 512 MiB MMC: FSL_SDHC: 0 In: serial Out: serial Err: serial Net: FEC0 Working: - Eth0 - i2C - MMC/SD - NAND - UART (1 & 5) - USB (host & otg) Signed-off-by: Martyn Welch <martyn.welch@collabora.com>