<feed xmlns='http://www.w3.org/2005/Atom'>
<title>bcm63xx/u-boot/board/seeed, branch master</title>
<subtitle>Broadcom-s U-Boot</subtitle>
<id>https://git.openwrt.org/project/bcm63xx/u-boot/atom?h=master</id>
<link rel='self' href='https://git.openwrt.org/project/bcm63xx/u-boot/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/'/>
<updated>2018-11-18T15:02:23Z</updated>
<entry>
<title>mips: mt76xx: linkit-smart-7688: Use ioremap_nocache to get address</title>
<updated>2018-11-18T15:02:23Z</updated>
<author>
<name>Stefan Roese</name>
</author>
<published>2018-10-09T06:59:15Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=8bd197770621df19e3eacd3ef83f9616b15b126f'/>
<id>urn:sha1:8bd197770621df19e3eacd3ef83f9616b15b126f</id>
<content type='text'>
Use the correct function to get the uncached address to access the SoC
registers.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
Cc: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
</entry>
<entry>
<title>MAINTAINERS: Update some entries for missed boards</title>
<updated>2018-09-30T17:00:37Z</updated>
<author>
<name>Tom Rini</name>
</author>
<published>2018-09-30T14:24:45Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=2c1e16b9d2e3a6138acf4ffd9866e47ddbe6d453'/>
<id>urn:sha1:2c1e16b9d2e3a6138acf4ffd9866e47ddbe6d453</id>
<content type='text'>
Signed-off-by: Tom Rini &lt;trini@konsulko.com&gt;
</content>
</entry>
<entry>
<title>mips: Add LinkIt Smart 7688 support</title>
<updated>2018-09-23T12:27:19Z</updated>
<author>
<name>Stefan Roese</name>
</author>
<published>2018-08-16T13:27:30Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=b02f76a83541fe9fe3a2918039b26fc133699c17'/>
<id>urn:sha1:b02f76a83541fe9fe3a2918039b26fc133699c17</id>
<content type='text'>
The LinkIt Smart 7688 modules have a MT7688 SoC with 128 MiB of RAM
and 32 MiB of flash (SPI NOR).

This patch also includes 2 targets. One is the target that can be
programmed into the SPI NOR flash and a 2nd target "xxx-ram" is
added to support loading and booting via an already running U-Boot
version. This allows easy development and testing without the
need to flash the image each time.

Signed-off-by: Stefan Roese &lt;sr@denx.de&gt;
[fixed and regenerated defconfig files]
Signed-off-by: Daniel Schwierzeck &lt;daniel.schwierzeck@gmail.com&gt;
</content>
</entry>
</feed>
