Broadcom-s U-Boot https://git.openwrt.org/project/bcm63xx/u-boot/atom?h=master 2019-06-05T16:14:02Z 2019-06-05T16:14:02Z Jean-Jacques Hiblot 2019-05-23T12:07:23Z urn:sha1:c5646270d1783982fc76eff831e5f3e63cb626cd This is required for proper operation of the 8-bit data transfers. This fixes transient errors seen on BeagleBone Black. Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> 2019-05-08T22:27:00Z Murali Karicheri 2019-02-25T20:27:34Z urn:sha1:89bf9f1162d7420e8b41ad729608add8f0cdc83b This add pinmux configuration for rgmii interface so that network driver can be supported on K2G ICE boards. The pinmux configurations for this are generated using the pinmux tool at https://dev.ti.com/pinmux/app.html#/default As this required some BUFFER_CLASS definitions, same is re-used from the linux defnitions in include/dt-bindings/pinctrl/keystone.h Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> 2019-05-08T22:27:00Z Murali Karicheri 2019-02-25T20:27:33Z urn:sha1:63200d8457209783300bf44a200298e12d23bf2d This patch updates pinmux configuration for K2G GP EVM based on data generated by the pinmux tool at https://dev.ti.com/pinmux/app.html#/default Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> 2019-05-05T12:48:50Z Brad Griffis 2019-04-29T04:29:33Z urn:sha1:5adcbe064357948435e04774a34c814d65e6d2e0 Remove the RDLVL_MASK, RDLVLGATE_MASK, WRLVL_MASK & enable PHY_INVERT_CLKOUT to enable Hardware leveling for am437x as recommended by EMIF Tools app note: http://www.ti.com/lit/an/sprac70/sprac70.pdf Signed-off-by: Brad Griffis <bgriffis@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> 2019-05-05T12:48:50Z Vignesh Raghavendra 2019-04-22T16:13:33Z urn:sha1:c14f3c31112653f5c5a34b748e9defbd3bc5a8ef AM654 SoC is IO coherent wrt A53 cores, therefore enable SYS_DISABLE_DCACHE_OPS to avoid cache operations in A53 SPL/U-Boot. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> 2019-05-03T11:23:17Z Paul Barker 2019-04-25T14:12:00Z urn:sha1:bb7b45a356376b52dd4d3a3acc2dde1fcfa75c4e In commit ad6054f1fe128f797b6eb2964afca6674b584785 where support for the Sancloud BeagleBone Enhanced (BBE) was added, new conditional configuration of either MII pin muxing or RGMII pin muxing is done depending on the board type. However, the old call to set up MII pin muxing was not removed. This may result in misconfiguration of the pin muxing for the BBE or duplicate configuration for other boards and so we remove this obsolete call. Signed-off-by: Paul Barker <paul.barker@sancloud.co.uk> 2019-04-12T12:05:55Z Faiz Abbas 2019-03-18T08:24:41Z urn:sha1:55f8b70fee856f7fc2ccf452e3533814e98a1ac6 With DM_ETH enabled in am335x devices, remove all the unused non-DM code. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> 2019-04-12T12:05:54Z Faiz Abbas 2019-03-18T08:24:37Z urn:sha1:0229c9330d2b34141f77584de417136d5c8088fc The SPL image overflows when cpsw dt nodes are added and SPL_OF_CONTROL is enabled. Use static platdata instead to save space. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> 2019-04-12T12:05:51Z Lokesh Vutla 2019-03-08T06:17:35Z urn:sha1:5582c03565190f364cca775ad4a4cc6b12fd0165 Create a ft_board_setup() api that gets called as part of DT fixup before jumping to kernel. In this ft_board_setup() call fdt_fixup_msmc_ram that update msmc sram node. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> 2019-04-12T12:05:49Z Franklin S Cooper Jr 2019-02-27T07:59:36Z urn:sha1:b3b2a9ea3e63aff50467d4bdefc48274705a77e9 If SW 8 pins 0 and 1 indicate that NAND should be enabled then the pins pinmux must be reconfigured for NAND mode. Therefore, enable NAND by reconfiguring the pinmux. Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com> Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>