Broadcom-s U-Boot https://git.openwrt.org/project/bcm63xx/u-boot/atom?h=master 2019-04-25T17:16:24Z 2019-04-25T17:16:24Z Parthiban Nallathambi 2019-04-17T22:04:09Z urn:sha1:d8d33b6d4dd2ecd2ea2a3d3ece9e22528d8fd15c Port for the DART-6UL Evaluation Kit SBC. Based on the variscite DART-6UL iMX6ULL SoM. CPU: Freescale i.MX6ULL rev1.1 900 MHz (running at 396 MHz) CPU: Commercial temperature grade (0C to 95C) at 43C Reset cause: POR Model: Variscite DART-6UL Evaluation Kit Board: Variscite DART-6UL Evaluation Kit DRAM: 512 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial@02020000 Out: serial@02020000 Err: serial@02020000 Net: FEC0 Working: - Eth0 - i2c - MMC/SD - eMMC - USB host - UART 1 Note: LCDIF porting needs DM_VIDEO https://lists.denx.de/pipermail/u-boot/2019-April/365506.html Signed-off-by: Parthiban Nallathambi <parthitce@gmail.com>