bcm63xx/u-boot/drivers/clk/Kconfig, branch master

clk: create meson directory and move related drivers

2019-04-23T09:19:09Z

In order to support the Amlogic G12A clock controller, re-architect the clock files into a meson directory. No functionnal changes. MAINTAINERS entry is also updated. Signed-off-by: Jerome Brunet Signed-off-by: Neil Armstrong

clk: Add SiFive FU540 PRCI clock driver

2019-02-27T01:12:33Z

Add driver code for the SiFive FU540 PRCI IP block. This IP block handles reset and clock control for the SiFive FU540 device and implements SoC-level clock tree controls and dividers. Based on code written by Wesley Terpstra found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of: https://github.com/riscv/riscv-linux Boot and PLL rate change were tested on a SiFive HiFive Unleashed board. Signed-off-by: Paul Walmsley Signed-off-by: Atish Patra Signed-off-by: Anup Patel Reviewed-by: Alexander Graf

clk: Add Allwinner A64 CLK driver

2019-01-18T16:49:08Z

Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki Acked-by: Maxime Ripard

clk: imx: add clk driver for i.MX8QXP

2018-10-22T10:59:01Z

Add clk driver for i.MX8QXP. This basic version supports clk enable/disable/get_rate/set_rate operations for I2C, ENET, SDHC0 and UART clocks. Signed-off-by: Peng Fan Signed-off-by: Anatolij Gustschin Cc: Stefano Babic

clk: Add support for Arm's Versatile Express OSC clock generators

2018-09-30T17:00:34Z

The Arm Versatile Express and Juno development boards contain an OSC clock generator that can be accessed through the Versatile Express config bus. The generators are quite often being controlled by some MCU and the config bus offers a uniform way of exposing them. Signed-off-by: Liviu Dudau Reviewed-by: Heiko Schocher

clk: Add MPC83xx clock driver

2018-09-18T06:01:18Z

Add a clock driver for the MPC83xx architecture. Signed-off-by: Mario Six

clk: Introduce TI System Control Interface (TI SCI) clock driver

2018-09-11T12:32:55Z

Some TI Keystone 2 and K3 family of SoCs contain a system controller (like the Power Management Micro Controller (PMMC) on 66AK2G SoCs and the Device Management and Security Controller on AM65x SoCs) that manage the low-level device control (like clocks, resets etc) for the various hardware modules present on the SoC. These device control operations are provided to the host processor OS through a communication protocol called the TI System Control Interface (TI SCI) protocol. This patch adds a clock driver that communicates to the system controller over the TI SCI protocol for performing clock management of various devices present on the SoC. Various clock functionality is achieved by the means of different TI SCI device operations provided by the TI SCI framework. This code is loosely based on the drivers/clk/keystone/sci-clk.c driver of the Linux kernel. Reviewed-by: Tom Rini Signed-off-by: Andreas Dannenberg Signed-off-by: Vignesh R Signed-off-by: Lokesh Vutla

clk: Kconfig: Ascending order to sub directiory kconfigs

2018-08-10T06:12:35Z

sourcing of sub directiory kconfig files are not in proper order, so keep them in ascending order. Signed-off-by: Jagan Teki Reviewed-by: Joe Hershberger

clk: Add Actions Semi OWL clock support

2018-07-09T19:25:31Z

This commit adds Actions Semi OWL family base clock and S900 SoC specific clock support. For S900 peripheral clock support, only UART clock has been added for now. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Simon Glass

driver: clk: Add support for clocks on Armada 37xx

2018-05-14T08:00:15Z

The drivers are based on Linux driver by Gregory Clement. The TBG clocks support only the .get_rate method. - since setting rate is not supported, the driver computes the rates when probing and so subsequent calls to the .get_rate method do not read the corresponding registers again The peripheral clocks support methods .get_rate, .enable and .disable. - the .set_parent method theoretically could be supported on some clocks (the parent would have to be one of the TBG clocks) - the .set_rate method would have to try all the divider values to find the best approximation of a given rate, and it doesn't seem like this should be needed in U-Boot, therefore not implemented Signed-off-by: Marek Behun Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese