bcm63xx/u-boot/drivers/clk/Makefile, branch master

clk: create meson directory and move related drivers

2019-04-23T09:19:09Z

In order to support the Amlogic G12A clock controller, re-architect the clock files into a meson directory. No functionnal changes. MAINTAINERS entry is also updated. Signed-off-by: Jerome Brunet Signed-off-by: Neil Armstrong

clk: Add fixed-factor clock driver

2019-02-27T01:12:33Z

This patch adds fixed-factor clock driver which derives clock rate by dividing (div) and multiplying (mult) fixed factors to a parent clock. Signed-off-by: Atish Patra Signed-off-by: Anup Patel Reviewed-by: Simon Glass

clk: Add SiFive FU540 PRCI clock driver

2019-02-27T01:12:33Z

Add driver code for the SiFive FU540 PRCI IP block. This IP block handles reset and clock control for the SiFive FU540 device and implements SoC-level clock tree controls and dividers. Based on code written by Wesley Terpstra found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of: https://github.com/riscv/riscv-linux Boot and PLL rate change were tested on a SiFive HiFive Unleashed board. Signed-off-by: Paul Walmsley Signed-off-by: Atish Patra Signed-off-by: Anup Patel Reviewed-by: Alexander Graf

clk: Add Allwinner A64 CLK driver

2019-01-18T16:49:08Z

Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki Acked-by: Maxime Ripard

Merge tag 'u-boot-amlogic-20181126' of git://git.denx.de/u-boot-amlogic

2018-11-29T20:16:58Z

Cleanup and update towards support for Amlogic Meson AXG SoCs : - mmc: meson-gx: Add AXG compatible - net: designware: add meson meson compatibles - Amlogic Meson cleanup for AXG SoC support

clk: MediaTek: add clock driver for MT7629 SoC.

2018-11-29T04:04:51Z

This patch adds clock modules for MediaTek SoCs: - Shared part: a common driver which contains the general operations for plls, muxes, dividers and gates so that we can reuse it in future. - Specific SoC part: the group of structures used to hold the hardware configuration for each SoC. We take MT7629 as an example to demonstrate how to implement driver if any other MediaTek chips would like to use it. Signed-off-by: Ryder Lee Reviewed-by: Simon Glass

clk: Add clock driver for AXG

2018-11-26T13:40:52Z

This patch adds a minimal clock driver for the Amlogic AXG SoC to handle the basic gates and PLLs. Signed-off-by: Neil Armstrong

drivers: cosmetic: Convert SPDX license tags to Linux Kernel style

2018-10-28T13:26:39Z

Complete in the drivers directory the work started with commit 83d290c56fab ("SPDX: Convert all of our single license tags to Linux Kernel style"). Reviewed-by: Simon Glass Signed-off-by: Patrick Delaunay

clk: imx: add clk driver for i.MX8QXP

2018-10-22T10:59:01Z

Add clk driver for i.MX8QXP. This basic version supports clk enable/disable/get_rate/set_rate operations for I2C, ENET, SDHC0 and UART clocks. Signed-off-by: Peng Fan Signed-off-by: Anatolij Gustschin Cc: Stefano Babic

clk: Add support for Arm's Versatile Express OSC clock generators

2018-09-30T17:00:34Z

The Arm Versatile Express and Juno development boards contain an OSC clock generator that can be accessed through the Versatile Express config bus. The generators are quite often being controlled by some MCU and the config bus offers a uniform way of exposing them. Signed-off-by: Liviu Dudau Reviewed-by: Heiko Schocher