bcm63xx/u-boot/drivers/clk/sunxi/Makefile, branch master

clk: sunxi: Add Allwinner A80 CLK driver

2019-01-18T16:49:09Z

Add initial clock driver for Allwinner A80. - Implement UART bus clocks via ccu_clk_gate table for A80, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for A80, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki

clk: sunxi: Add Allwinner H6 CLK driver

2019-01-18T16:49:09Z

Add initial clock driver for Allwinner H6. - Implement UART bus clocks via ccu_clk_gate table for H6, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for H6, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki Reviewed-by: Andre Przywara

clk: sunxi: Add Allwinner V3S CLK driver

2019-01-18T16:49:09Z

Add initial clock driver for Allwinner V3S. - Implement USB bus and USB clocks via ccu_clk_gate table for V3S, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for V3S, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki Acked-by: Maxime Ripard

clk: sunxi: Add Allwinner R40 CLK driver

2019-01-18T16:49:09Z

Add initial clock driver for Allwinner R40. - Implement USB bus and USB clocks via ccu_clk_gate for R40, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for R40, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki Acked-by: Maxime Ripard

clk: sunxi: Add Allwinner A83T CLK driver

2019-01-18T16:49:09Z

Add initial clock driver for Allwinner A83T. - Implement USB bus and USB clocks via ccu_clk_gate table for A83T, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for A83T, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki Acked-by: Maxime Ripard

clk: sunxi: Add Allwinner A23/A33 CLK driver

2019-01-18T16:49:09Z

Add initial clock driver for Allwinner A23/A33. - Implement USB bus and USB clocks via ccu_clk_gate table for A23/A33, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for A23/A33, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki Acked-by: Maxime Ripard

clk: sunxi: Add Allwinner A31 CLK driver

2019-01-18T16:49:09Z

Add initial clock driver for Allwinner A31. - Implement USB ahb1 and USB clocks via ccu_clk_gate table for A31, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB ahb1 and USB resets via ccu_reset table for A31, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki Acked-by: Maxime Ripard

clk: sunxi: Add Allwinner A10s/A13 CLK driver

2019-01-18T16:49:08Z

Add initial clock driver for Allwinner A10s/A13. - Implement USB ahb and USB clocks via ccu_clk_gate table for A10s/A13, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB resets via ccu_reset table for A10s/A13, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki Acked-by: Maxime Ripard

clk: sunxi: Add Allwinner A10/A20 CLK driver

2019-01-18T16:49:08Z

Add initial clock driver for Allwinner A10/A20. - Implement USB ahb and USB clocks via ccu_clk_gate table for A10/A20, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB resets via ccu_reset table for A10/A20, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki Acked-by: Maxime Ripard

clk: sunxi: Add Allwinner H3/H5 CLK driver

2019-01-18T16:49:08Z

Add initial clock driver for Allwinner H3/H5. - Implement USB bus and USB clocks via ccu_clk_gate table for H3/H5, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for H3/H5, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki Acked-by: Maxime Ripard