bcm63xx/u-boot/drivers/clk/sunxi, branch master

clk: sunxi: r40: Fix GMAC reset reg offset

2019-04-16T10:59:00Z

GMAC reset reg offset added by below commit seems to assume it as EMAC but R40 indeed using GMAC. "clk: sunxi: Implement EMAC, GMAC clocks, resets" (sha1: 68620c9698f109c1f001f80d282138a5c67cabef) So, fix by updating the reg offset for RST_BUS_GMAC. Signed-off-by: Jagan Teki

clk: sunxi: a10: Add CLK_AHB_GMAC

2019-04-01T16:15:15Z

CLK_AHB_GMAC was suppose to be part of previous commit "clk: sunxi: Implement A10 EMAC clocks" add it so-that we can get rid of sunxi_set_gate warning on boot message. Signed-off-by: Jagan Teki

clk: sunxi: h3: Implement EPHY CLK and RESET

2019-03-09T07:46:35Z

EPHY CLK and RESET is available in Allwinner H3 EMAC via mdio-mux node of internal PHY. Add the respective clock and reset reg and bits. Cc: Joe Hershberger Signed-off-by: Jagan Teki Acked-by: Joe Hershberger

clk: sunxi: Implement EMAC, GMAC clocks, resets

2019-03-09T07:46:35Z

- Implement EMAC, GMAC clocks via ccu_clk_gate for all supported Allwinner SoCs. - Implement EMAC, GMAC resets via ccu_reset for all supported Allwinner SoCs. Cc: Joe Hershberger Signed-off-by: Jagan Teki Acked-by: Joe Hershberger

clk: sunxi: Implement A10 EMAC clocks

2019-03-09T07:46:35Z

Implement EMAC clocks via ccu_clk_gate for Allwinner A10 SoC. Which would eventually used in sunxi_emac.c driver. Signed-off-by: Jagan Teki

clk: sunxi: Implement SPI clocks, resets

2019-03-04T12:38:56Z

- Implement SPI AHB, MOD clocks via ccu_clk_gate for all supported Allwinner SoCs - Implement SPI resets via ccu_reset for all supported Allwinner SoCs. Signed-off-by: Jagan Teki Reviewed-by: Andre Przywara

sunxi: clk: enable clk and reset for CCU devices

2019-01-30T12:51:35Z

Some Allwinner clock devices have parent clocks and reset gates itself, which need to be activated for them to work. Add some code to just assert all resets and enable all clocks given. This should enable the A80 MMC config clock, which requires both to be activated. The full CCU devices typically don't require resets, and have just fixed clocks as their parents. Since we treat both as optional and enabling fixed clocks is a NOP, this works for all cases, without the need to differentiate between those clock types. Signed-off-by: Andre Przywara Acked-by: Jagan Teki

sunxi: clk: A80: add MMC clock support

2019-01-29T18:03:08Z

The A80 handles resets and clock gates for the MMC devices differently, outside of the CCU IP block. Consequently we have a separate clock device with a separate binding for that. Implement that with the respective clock gates and resets to allow the A80 taking part in the DM_MMC game. Signed-off-by: Andre Przywara [jagan: fix a80 mmc clock config compatible] Signed-off-by: Jagan Teki Reviewed-by: Jagan Teki

sunxi: clk: add MMC gates/resets

2019-01-29T18:00:11Z

Add the MMC clock gates and reset bits for all the Allwinner SoCs. This allows them to be used by the MMC driver. We don't advertise the mod clock yet, as this is still handled by the MMC driver. Signed-off-by: Andre Przywara [jagan: add V3S, A80 gates/resets] Signed-off-by: Jagan Teki Reviewed-by: Jagan Teki

clk: sunxi: Add Allwinner A80 CLK driver

2019-01-18T16:49:09Z

Add initial clock driver for Allwinner A80. - Implement UART bus clocks via ccu_clk_gate table for A80, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for A80, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki