bcm63xx/u-boot/drivers/clk, branch master

Merge tag 'u-boot-stm32-20190606' of https://github.com/pchotard/u-boot

2019-06-11T21:22:22Z

- Add Ethernet support for STM32MP1 - Add saveenv support for STM32MP1 - Add STM32MP1 Avenger96 board support - Add SPI driver suport for STM32MP1 - Add watchdog support for STM32MP1 - Update power supply check via USB TYPE-C for STM32MP1 discovery board

clk: imx8qm: fix usdhc2 clocks

2019-06-11T08:42:48Z

Trying to bring up uSDHC2 the following error message was observed: MMC: imx8_clk_set_rate(Invalid clk ID #60) imx8_clk_set_rate(Invalid clk ID #60) usdhc@5b030000 - probe failed: -22 This commit fixes this by properly setting resp. clocks. Signed-off-by: Marcel Ziswiler Reviewed-by: Max Krummenacher

stm32mp1: clk: use the correct identifier for ethck

2019-06-06T15:40:18Z

ETHCK_K is the identifier the kernel clock for ETH in kernel binding, selected by ETHKSELR / gated by ETHCKEN = BIT(7). U-Boot driver need to use the same identifier, so change ETHCK to ETHCK_K. Signed-off-by: Patrick Delaunay Signed-off-by: Christophe Roullier

clk: stm32mp1: Add SPI1 clock entry

2019-06-06T15:40:17Z

Add missing SPI1 clock needed by SPI1 instance. Signed-off-by: Patrice Chotard

clk: sifive: Add clock driver for GEMGXL MGMT

2019-06-01T18:33:17Z

This adds a clock driver to support the GEMGXL management IP block found in FU540 SoCs to control GEM TX clock operation mode for 10/100/1000 Mbps. Signed-off-by: Bin Meng Reviewed-by: Lukas Auer Tested-by: Lukas Auer

Merge tag 'rockchip-for-v2019.07-rc3' of git://git.denx.de/u-boot-rockchip

2019-05-31T11:17:09Z

- some fix for rk3399-puma; - rockchip script make_fit_atf.py cleanup - Enable TPL for rk3399 orangepi and nanopi4; - add support for rk3399 boards: Nanopi NEO4, Rockpro64, Rock PI 4;

clk: meson-g12a: Add PCIE PLL support

2019-05-31T07:57:49Z

The G12A PCIE PLL clock was introduced in Linux 5.2-rc1, and is needed for USB to operate, add basic support for it and associated gates. Signed-off-by: Neil Armstrong

rockchip: clk: rk3399: allow requests for all UART clocks

2019-05-30T10:22:35Z

This patch adds the rate for UART1 and UART3 the same way as already implemented for UART0 and UART2. This is required for boards, which have their console output on these UARTs. Signed-off-by: Christoph Muellner Reviewed-by: Simon Glass Reviewed-by: Kever Yang

clk: stm32mp1: add set_rate for DDRPHYC clock

2019-05-23T09:36:47Z

Add the DDRPHYC support for clk_set_rate, used in DDR interactive mode Signed-off-by: Patrick Delaunay

mpc83xx_clk: Add enable method

2019-05-21T05:52:34Z

Some DM drivers have hardcoded clk_enable calls when handling clocks (for example the fsl_esdhc driver). To work with these drivers, add an enable method to the MCP83xx clock driver (which does nothing, because the clocks are always enabled). Signed-off-by: Mario Six