bcm63xx/u-boot/drivers/ddr, branch master

mpc83xx: Get rid of CONFIG_SYS_DDR_SDRAM_BASE

2019-05-21T05:52:33Z

CONFIG_SYS_DDR_SDRAM_BASE is set to the same value as CONFIG_SYS_SDRAM_BASE on all existing boards. Just use CONFIG_SYS_SDRAM_BASE instead. Signed-off-by: Mario Six

arm: socfpga: Move Stratix 10 SDRAM driver to DM

2019-05-06T10:44:17Z

Convert Stratix 10 SDRAM driver to device model. Get rid of call to socfpga_per_reset() and use reset framework. SPL is changed from calling function in SDRAM driver directly to just probing UCLASS_RAM. Move sdram_s10.h from arch to driver/ddr/altera directory. Signed-off-by: Ley Foon Tan

ddr: altera: Compile ALTERA SDRAM in SPL only

2019-05-06T10:44:17Z

Compile ALTERA_SDRAM driver in SPL only. Rename ALTERA_SDRAM to SPL_ALTERA_SDRAM. Signed-off-by: Ley Foon Tan

ddr: imx8m: hide i.MX8M DDR options from device driver entry

2019-04-25T17:20:04Z

Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan

ddr: altera: Stratix10: Add ECC memory scrubbing

2019-04-17T20:20:17Z

Scrub memory content if ECC is enabled and it is not from warm reset boot. Enable icache and dcache before scrub memory and use "DC ZVA" instruction to clear memory to zeros. This instruction writes a cache line at a time and it can prevent false ECC error trigger if write cache line partially. Signed-off-by: Ley Foon Tan

ddr: altera: Stratix10: Add multi-banks DRAM size check

2019-04-17T20:20:17Z

Stratix 10 maps dram from 0 to 128GB. There is a 2GB hole in the memory for peripherals and other IO from 2GB to 4GB. However the dram controller ignores upper address bits for smaller dram configurations. Example: a 4GB dram maps to multiple locations, every 4GB on the address. Signed-off-by: Dalon Westergreen Signed-off-by: Ley Foon Tan

ddr: altera: stratix10: Move SDRAM size check to SDRAM driver

2019-04-17T20:20:17Z

Move SDRAM size check to SDRAM driver. sdram_calculate_size() is called in SDRAM initialization already, avoid calling twice in size check function. Signed-off-by: Ley Foon Tan

arm: socfpga: move gen5 SDR driver to DM

2019-04-17T20:20:16Z

To clean up reset handling for socfpga gen5, port the DDR driver to DM using UCLASS_RAM and implement proper reset handling. This gets us rid of one ad-hoc call to socfpga_per_reset(). The gen5 driver is implemented in 2 distinct files. One of it (containing the calibration training) is not touched much and is kept at using hard coded addresses since the code grows even more otherwise. SPL is changed from calling hard into the DDR driver code to just probing UCLASS_RESET and UCLASS_RAM. It is happy after finding a RAM driver after that. Signed-off-by: Simon Goldschmidt

arm: mvebu: Add Marvell's integrated CPUs

2019-04-12T05:04:18Z

Marvell's switch chips with integrated CPUs (collectively referred to as MSYS) share common ancestry with the Armada SoCs. Some of the IP blocks (e.g. xor) are located at different addresses and DFX server exists as a separate target on the MBUS (on Armada-38x it's just part of the core complex registers). Signed-off-by: Chris Packham Reviewed-by: Stefan Roese Signed-off-by: Stefan Roese

mv_ddr: ddr3: only use active chip-selects when tuning ODT

2019-03-19T08:22:05Z

Inactive chip-selects will give invalid values for read_sample so don't consider them when trying to determine the overall min/max read sample. Signed-off-by: Chris Packham [https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/18] Signed-off-by: Chris Packham Signed-off-by: Stefan Roese