<feed xmlns='http://www.w3.org/2005/Atom'>
<title>bcm63xx/u-boot/drivers/fpga, branch master</title>
<subtitle>Broadcom-s U-Boot</subtitle>
<id>https://git.openwrt.org/project/bcm63xx/u-boot/atom?h=master</id>
<link rel='self' href='https://git.openwrt.org/project/bcm63xx/u-boot/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/'/>
<updated>2019-05-10T20:48:11Z</updated>
<entry>
<title>spl: socfpga: Implement fpga bitstream loading with socfpga loadfs</title>
<updated>2019-05-10T20:48:11Z</updated>
<author>
<name>Tien Fong Chee</name>
</author>
<published>2019-05-07T09:42:30Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=1085bb3cbaf8321fdc8d0eaa367192433bd51d44'/>
<id>urn:sha1:1085bb3cbaf8321fdc8d0eaa367192433bd51d44</id>
<content type='text'>
Add support for loading FPGA bitstream to get DDR up running before
U-Boot is loaded into DDR. Boot device initialization, generic firmware
loader and SPL FAT support are required for this whole mechanism to work.

Signed-off-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
</content>
</entry>
<entry>
<title>ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading</title>
<updated>2019-05-10T20:48:11Z</updated>
<author>
<name>Tien Fong Chee</name>
</author>
<published>2019-05-07T09:42:28Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=0a42a132a4b846031df2c4a7d04692240ed34843'/>
<id>urn:sha1:0a42a132a4b846031df2c4a7d04692240ed34843</id>
<content type='text'>
Add FPGA driver to support program FPGA with FPGA bitstream loading from
filesystem. The driver are designed based on generic firmware loader
framework. The driver can handle FPGA program operation from loading FPGA
bitstream in flash to memory and then to program FPGA.

Signed-off-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
</content>
</entry>
<entry>
<title>ARM: socfpga: Moving the watchdog reset to the for-loop status polling</title>
<updated>2019-05-10T20:48:10Z</updated>
<author>
<name>Tien Fong Chee</name>
</author>
<published>2019-05-07T09:42:27Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=c1cf5391807640159edcd363ea1cbaf226a56b58'/>
<id>urn:sha1:c1cf5391807640159edcd363ea1cbaf226a56b58</id>
<content type='text'>
Current watchdog reset is misplaced after for-loop status polling, so
this poses a risk that watchdog can't be reset timely if polling taking
longer than watchdog timeout. This patch moving the watchdog reset
into polling to ensure the watchdog can be reset timely.

Signed-off-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
</content>
</entry>
<entry>
<title>ARM: socfpga: Cleaning up and ensuring consistent format messages in driver</title>
<updated>2019-05-10T20:48:10Z</updated>
<author>
<name>Tien Fong Chee</name>
</author>
<published>2019-05-07T09:42:26Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=f4b53b24d04fb223a6d5332c3744b955c462326d'/>
<id>urn:sha1:f4b53b24d04fb223a6d5332c3744b955c462326d</id>
<content type='text'>
Ensure all the debug messages are always prefix with "FPGA: " and comment
beginning with uppercase letter.

Signed-off-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
</content>
</entry>
<entry>
<title>arm: zynq: Add an info message about post config</title>
<updated>2019-04-16T09:51:34Z</updated>
<author>
<name>Siva Durga Prasad Paladugu</name>
</author>
<published>2019-03-23T10:31:36Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=31f7ce7f9bfd41c996b33f7568718462bbfe5b45'/>
<id>urn:sha1:31f7ce7f9bfd41c996b33f7568718462bbfe5b45</id>
<content type='text'>
Post configuration cant be run at u-boot as u-boot
didn't has any info about the design.So,this patch
adds an info message that post config was not run
and needs to be run manually if needed.

Signed-off-by: Siva Durga Prasad Paladugu &lt;siva.durga.paladugu@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>fpga: Replace char * with const char * for filename</title>
<updated>2019-04-16T09:51:33Z</updated>
<author>
<name>Tien Fong Chee</name>
</author>
<published>2019-02-15T07:57:07Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=3003c445b3cb1d1ca7e2304bfa3e2faf2ae02f80'/>
<id>urn:sha1:3003c445b3cb1d1ca7e2304bfa3e2faf2ae02f80</id>
<content type='text'>
Ensure the string for filename is always constant, otherwise it can be
corrupted by the writing.

Signed-off-by: Tien Fong Chee &lt;tien.fong.chee@intel.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>ARM: socfpga: stratix10: Return valid error code from FPGA driver</title>
<updated>2019-02-18T12:00:54Z</updated>
<author>
<name>Ang, Chee Hong</name>
</author>
<published>2019-02-18T04:07:50Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=5097ba6177bad8c7e09b50149cacd6fd5020f0c8'/>
<id>urn:sha1:5097ba6177bad8c7e09b50149cacd6fd5020f0c8</id>
<content type='text'>
This patch prevent the Stratix 10 FPGA driver incorrectly return the
transaction ID as the mailbox error code. It should always return the
actual mailbox error code from SDM firmware.

Signed-off-by: Ang, Chee Hong &lt;chee.hong.ang@intel.com&gt;
</content>
</entry>
<entry>
<title>fpga: zynqmp: show an error message when FPGA programming fails</title>
<updated>2019-01-24T09:03:43Z</updated>
<author>
<name>Luca Ceresoli</name>
</author>
<published>2019-01-11T16:09:45Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=8df324a20b45f3a15a166797a2d5a5d447337891'/>
<id>urn:sha1:8df324a20b45f3a15a166797a2d5a5d447337891</id>
<content type='text'>
When FPGA programming fails, it does so silently, unless debugging
code is enabled. This makes it hard to detect problems in production
environments.

Print the error message unconditionally so the error doesn't go
unnoticed.

Signed-off-by: Luca Ceresoli &lt;luca@lucaceresoli.net&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
</content>
</entry>
<entry>
<title>arm: socfpga: stratix10: Add Stratix10 FPGA into FPGA device table</title>
<updated>2018-12-20T16:12:25Z</updated>
<author>
<name>Ang, Chee Hong</name>
</author>
<published>2018-12-20T02:35:15Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=877ec6ebbd247d54706e8f18a5d0c85da229a163'/>
<id>urn:sha1:877ec6ebbd247d54706e8f18a5d0c85da229a163</id>
<content type='text'>
Enable 'fpga' command in u-boot. User will be able to use the FPGA
command to program the FPGA on Stratix10 SoC.

Signed-off-by: Ang, Chee Hong &lt;chee.hong.ang@intel.com&gt;
</content>
</entry>
<entry>
<title>arm: socfpga: stratix10: Add Stratix 10 FPGA Reconfiguration Driver</title>
<updated>2018-12-20T16:12:25Z</updated>
<author>
<name>Ang, Chee Hong</name>
</author>
<published>2018-12-20T02:35:14Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=c41e660b6bb4405fb511c7af29aad4271f6b39a8'/>
<id>urn:sha1:c41e660b6bb4405fb511c7af29aad4271f6b39a8</id>
<content type='text'>
Enable FPGA reconfiguration support for Stratix 10 SoC.

Signed-off-by: Ang, Chee Hong &lt;chee.hong.ang@intel.com&gt;
</content>
</entry>
</feed>
