bcm63xx/u-boot/drivers/net/zynq_gem.c, branch masterBroadcom-s U-Boothttps://git.openwrt.org/project/bcm63xx/u-boot/atom?h=master2019-04-16T09:52:02Znet: gem: Remove phy autodetection code2019-04-16T09:52:02ZMichal Simek2019-03-29T08:25:09Zurn:sha1:c19d4c72aa7026c82c1b1a310c3bb26e1e7a8f1d
There is no reason to detect phy when core is doing it for us.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
net: zynq_gem: Modify phy supported features after max-speed was set2019-04-16T09:52:02ZSiva Durga Prasad Paladugu2019-03-27T12:09:59Zurn:sha1:51c019ff8cb530b96fca037dd5728cce255cb6e5
The phydev supported features were reset in phy_set_supported() so,
move the setting of driver supported features after this so that it
wont lost in phy_set_supported().
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
zynq-gem: Use appropriate cache flush/invalidate for RX and TX2019-01-24T09:03:42ZStefan Theil2018-12-17T08:12:30Zurn:sha1:10598580612cbaee2298bddd77e9a51df5a2943d
The cache was only flushed before *transmitting* packets, but not
when receiving them, leading to an issue where new packets were
handed to the receive handler with old contents in cache. This
only happens when a lot of packets are received without sending
packages every now and then. Also flushing the receive buffers
in the transmit function makes no sense and can be removed.
Signed-off-by: Stefan Theil <stefan.theil@mixed-mode.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
net: zynq_gem: Add check for 64-bit dma support by hardware2018-12-03T15:22:06ZSiva Durga Prasad Paladugu2018-11-26T10:57:39Zurn:sha1:5f68f44c14ab93ffc44a9285e0970cba467276c6
This patch throws an error if 64-bit support is expected
but DMA hardware is not capable of 64-bit support. It also
prints a debug message if DMA is capable of 64-bit but not
using it.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
net: zynq_gem: Added 64-bit addressing support2018-12-03T15:22:01ZVipul Kumar2018-11-26T10:57:38Zurn:sha1:9a7799f4f4426e690d8c5ab69e6ac34e51029036
This patch adds 64-bit addressing support for zynq gem.
This means it can perform send and receive operations on
64-bit address buffers.
Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <monstr@monstr.eu>
net: gem: Do not setup any clock for Xilinx SoC Versal2018-10-16T14:53:24ZMichal Simek2018-08-22T14:18:34Zurn:sha1:3dc80934f4651a3ef243a393be04b1f7f71daf24
Xilinx SoC Versal is using fixed clock where setting rate is not supported.
That's why workaround the driver till real clock driver is supported.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
net: zynq_gem: Add support for fixed-link phy2018-09-27T05:59:26ZMichal Simek2018-09-20T07:42:27Zurn:sha1:3888c8d1979289efe685fe29276aed4d4b685975
Based on dt-specs fixed-link doesn't require phy-handle to be used.
Fix driver to only read phy related setting when phy-handle is found.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
net: zynq_gem: Fix reading of max-speed property2018-09-26T08:15:00ZSiva Durga Prasad Paladugu2018-09-04T13:38:53Zurn:sha1:f213dbbdeca6d2444bfe90d9b422de056bc4d369
max-speed property is part of phynode and it has to be
read using ofnode_read_u32_default(). This fixes the issue
of incorrect max-speed read from DT.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
net: zynq_gem: convert to use livetree2018-07-26T19:08:23ZSiva Durga Prasad Paladugu2018-07-16T12:55:45Zurn:sha1:26026e695afa794ac018a09e79a48120d322b60d
This patch updates the zynq gem driver to support livetree.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Vipul Kumar <vipul.kumar@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
drivers: net: zynq_gem: fix phy dt node setting2018-07-26T19:08:23ZGrygorii Strashko2018-07-05T17:02:52Zurn:sha1:41080e180c2249a0da586b3e79f15ae7515b8a18
Now zynq_gem driver will overwrite UCLASS_ETH node when PHY is
connected and configured which is not correct.
Use struct phydev->node instead.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Tested-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>