<feed xmlns='http://www.w3.org/2005/Atom'>
<title>bcm63xx/u-boot/drivers/pinctrl/renesas, branch master</title>
<subtitle>Broadcom-s U-Boot</subtitle>
<id>https://git.openwrt.org/project/bcm63xx/u-boot/atom?h=master</id>
<link rel='self' href='https://git.openwrt.org/project/bcm63xx/u-boot/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/'/>
<updated>2019-05-07T03:41:32Z</updated>
<entry>
<title>pinctrl: renesas: Add RZ/A1 R7S72100 pin control driver</title>
<updated>2019-05-07T03:41:32Z</updated>
<author>
<name>Marek Vasut</name>
</author>
<published>2019-05-04T12:17:10Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=cbde9dea09e807777a20ee8df9eb862aa03142d1'/>
<id>urn:sha1:cbde9dea09e807777a20ee8df9eb862aa03142d1</id>
<content type='text'>
Add pin control driver for RZ/A1 SoC. The IP is very different
from the R-Car Gen2/Gen3 one already present in the tree, hence
a custom driver.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Chris Brandt &lt;chris.brandt@renesas.com&gt;
Cc: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: renesas: Remove sh_pfc_config_mux_for_gpio()</title>
<updated>2019-05-04T17:26:49Z</updated>
<author>
<name>Marek Vasut</name>
</author>
<published>2019-04-21T20:46:25Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=5403bec1cb530f8c4aa97a1cd7f9f860716c8c1f'/>
<id>urn:sha1:5403bec1cb530f8c4aa97a1cd7f9f860716c8c1f</id>
<content type='text'>
This function is now replaced by common pin controller GPIO configuration
functionality, drop it.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Alex Kiernan &lt;alex.kiernan@gmail.com&gt;
Cc: Christoph Muellner &lt;christoph.muellner@theobroma-systems.com&gt;
Cc: Eugeniu Rosca &lt;roscaeugeniu@gmail.com&gt;
Cc: Patrice Chotard &lt;patrice.chotard@st.com&gt;
Cc: Patrick DELAUNAY &lt;patrick.delaunay@st.com&gt;
Cc: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: renesas: Implement gpio_request_enable/gpio_disable_free</title>
<updated>2019-05-04T17:26:49Z</updated>
<author>
<name>Marek Vasut</name>
</author>
<published>2019-04-21T20:46:25Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=89ba7c5a8cf3cdef34f5acef4184f35e63439759'/>
<id>urn:sha1:89ba7c5a8cf3cdef34f5acef4184f35e63439759</id>
<content type='text'>
Implement the gpio_request_enable/gpio_disable_free callbacks to let
the GPIO driver call the pin control framework and let it reconfigure
pins as GPIOs.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Alex Kiernan &lt;alex.kiernan@gmail.com&gt;
Cc: Christoph Muellner &lt;christoph.muellner@theobroma-systems.com&gt;
Cc: Eugeniu Rosca &lt;roscaeugeniu@gmail.com&gt;
Cc: Patrice Chotard &lt;patrice.chotard@st.com&gt;
Cc: Patrick DELAUNAY &lt;patrick.delaunay@st.com&gt;
Cc: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: renesas: Set pin type in sh_pfc_config_mux_for_gpio</title>
<updated>2019-05-04T17:26:49Z</updated>
<author>
<name>Marek Vasut</name>
</author>
<published>2019-04-21T20:46:25Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=50e6901fec0bd7dbfb2e39e750119ee0c78160c5'/>
<id>urn:sha1:50e6901fec0bd7dbfb2e39e750119ee0c78160c5</id>
<content type='text'>
Add missing cfg-&gt;type = PINMUX_TYPE_GPIO upon successfully setting pin
as a GPIO to retain the pin configuration information.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Alex Kiernan &lt;alex.kiernan@gmail.com&gt;
Cc: Christoph Muellner &lt;christoph.muellner@theobroma-systems.com&gt;
Cc: Eugeniu Rosca &lt;roscaeugeniu@gmail.com&gt;
Cc: Patrice Chotard &lt;patrice.chotard@st.com&gt;
Cc: Patrick DELAUNAY &lt;patrick.delaunay@st.com&gt;
Cc: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Cc: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: renesas: Synchronize Gen3 tables with Linux 5.0</title>
<updated>2019-04-09T16:19:10Z</updated>
<author>
<name>Marek Vasut</name>
</author>
<published>2019-03-04T21:39:51Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=8719ca81136474277d117975082c48a19d307b30'/>
<id>urn:sha1:8719ca81136474277d117975082c48a19d307b30</id>
<content type='text'>
Synchronize R-Car Gen3 pin control tables with Linux 5.0,
commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 .

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: renesas: Synchronize Gen2 tables with Linux 5.0</title>
<updated>2019-04-09T16:19:10Z</updated>
<author>
<name>Marek Vasut</name>
</author>
<published>2019-03-04T21:26:28Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=a6a743df242a50fe40272235fdaf2c4ba2e800f0'/>
<id>urn:sha1:a6a743df242a50fe40272235fdaf2c4ba2e800f0</id>
<content type='text'>
Synchronize R-Car Gen2 pin control tables with Linux 5.0,
commit 1c163f4c7b3f621efff9b28a47abb36f7378d783 .

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: renesas: Add TDSEL fixup for H2/E2 ES1.0 SoCs</title>
<updated>2019-04-09T16:19:10Z</updated>
<author>
<name>Marek Vasut</name>
</author>
<published>2019-03-04T21:29:30Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=37929ca84b1c28d71028ec530358332c1f064bec'/>
<id>urn:sha1:37929ca84b1c28d71028ec530358332c1f064bec</id>
<content type='text'>
Linux 5.0, commit 1c163f4c7b3f621efff9b28a47abb36f7378d783,
has a TDSEL fix for R8A7790 H2 and R8A7794 E2 SoCs, implement
similar fix for U-Boot. The difference here is that the SoC
ES matching has to be implemented manually.

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: renesas: Add R8A77965 pin control tables</title>
<updated>2019-04-09T16:19:10Z</updated>
<author>
<name>Marek Vasut</name>
</author>
<published>2019-03-04T00:32:44Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=c6435c317a7853fdde20a67af01e810a87e3d989'/>
<id>urn:sha1:c6435c317a7853fdde20a67af01e810a87e3d989</id>
<content type='text'>
Add pin control tables for R8A77965 from Linux 5.0 .

Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: renesas: r8a77990: Reivse USB ID pin name</title>
<updated>2019-03-04T00:46:05Z</updated>
<author>
<name>Hiroyuki Yokoyama</name>
</author>
<published>2019-02-13T05:23:46Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=65eef78cdbea3107fff9b29193b28f1c9f197545'/>
<id>urn:sha1:65eef78cdbea3107fff9b29193b28f1c9f197545</id>
<content type='text'>
Since the datasheet Rev.1.00 has an error about the USB ID pin name,
this patch revises it.

Signed-off-by: Hiroyuki Yokoyama &lt;hiroyuki.yokoyama.vx@renesas.com&gt;
Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: renesas: r8a77990: Fix MOD_SEL0 bit3 when using TX0</title>
<updated>2019-03-04T00:46:05Z</updated>
<author>
<name>Hiroyuki Yokoyama</name>
</author>
<published>2019-02-13T03:41:04Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=bf93f24c30bd63d94eea2fa35465e51efadf14cd'/>
<id>urn:sha1:bf93f24c30bd63d94eea2fa35465e51efadf14cd</id>
<content type='text'>
According to the R-Car Gen3 Hardware Manual Errata for Rev 1.50,
the MOD_SEL0 bit3 is set to 0 when TX0_A pin function is selected,
and the MOD_SEL0 bit3 is set to 1 when TX0_B pin function is
selected.

Signed-off-by: Hiroyuki Yokoyama &lt;hiroyuki.yokoyama.vx@renesas.com&gt;
Signed-off-by: Marek Vasut &lt;marek.vasut+renesas@gmail.com&gt;
Cc: Nobuhiro Iwamatsu &lt;iwamatsu@nigauri.org&gt;
</content>
</entry>
</feed>
