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<title>bcm63xx/u-boot/drivers/reset/Kconfig, branch master</title>
<subtitle>Broadcom-s U-Boot</subtitle>
<id>https://git.openwrt.org/project/bcm63xx/u-boot/atom?h=master</id>
<link rel='self' href='https://git.openwrt.org/project/bcm63xx/u-boot/atom?h=master'/>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/'/>
<updated>2019-04-23T21:57:24Z</updated>
<entry>
<title>reset: add reset driver for HiSilicon platform</title>
<updated>2019-04-23T21:57:24Z</updated>
<author>
<name>Shawn Guo</name>
</author>
<published>2019-03-20T07:32:39Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=f5e6c168c174cff74201ef58d99b27229ca0e4c2'/>
<id>urn:sha1:f5e6c168c174cff74201ef58d99b27229ca0e4c2</id>
<content type='text'>
It adds a Driver Model compatible reset driver for HiSlicon platform.
The driver implements a custom .of_xlate function, and uses .data field
as reset register offset and .id field as bit shift.

Signed-off-by: Shawn Guo &lt;shawn.guo@linaro.org&gt;
Acked-by: Joe Hershberger &lt;joe.hershberger@ni.com&gt;
</content>
</entry>
<entry>
<title>reset: Add Allwinner RESET driver</title>
<updated>2019-01-18T16:49:08Z</updated>
<author>
<name>Jagan Teki</name>
</author>
<published>2019-01-18T16:48:13Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=99ba4308701c51dcf425dbef42c6f87fcc9c42a2'/>
<id>urn:sha1:99ba4308701c51dcf425dbef42c6f87fcc9c42a2</id>
<content type='text'>
Add common reset driver for all Allwinner SoC's.

Since CLK and RESET share common DT compatible, it is CLK driver
job is to bind the reset driver. So add CLK bind call on respective
SoC driver by passing ccu map descriptor so-that reset deassert,
deassert operations held based on ccu reset table defined from
CLK driver.

Select DM_RESET via CLK_SUNXI, this make hidden section of RESET
since CLK and RESET share common DT compatible and code.

Signed-off-by: Jagan Teki &lt;jagan@amarulasolutions.com&gt;
Acked-by: Maxime Ripard &lt;maxime.ripard@bootlin.com&gt;
</content>
</entry>
<entry>
<title>reset: MedaiTek: add reset controller driver for MediaTek SoCs</title>
<updated>2019-01-14T22:43:18Z</updated>
<author>
<name>Weijie Gao</name>
</author>
<published>2018-12-20T08:12:51Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=3e066bcaefb51adcf5c0594d42abe145f701dbeb'/>
<id>urn:sha1:3e066bcaefb51adcf5c0594d42abe145f701dbeb</id>
<content type='text'>
This patch adds reset controller driver for MediaTek SoCs.

Signed-off-by: Ryder Lee &lt;ryder.lee@mediatek.com&gt;
Signed-off-by: Weijie Gao &lt;weijie.gao@mediatek.com&gt;
</content>
</entry>
<entry>
<title>reset: Introduce TI System Control Interface (TI SCI) reset driver</title>
<updated>2018-09-11T12:32:55Z</updated>
<author>
<name>Andreas Dannenberg</name>
</author>
<published>2018-08-27T10:27:41Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=65c8a79811baa10944cebb34dcec6c0695f13197'/>
<id>urn:sha1:65c8a79811baa10944cebb34dcec6c0695f13197</id>
<content type='text'>
Some TI Keystone 2 and K3 family of SoCs contain a system controller
(like the Power Management Micro Controller (PMMC) on 66AK2G SoCs and
the Device Management and Security Controller on AM65x SoCs) that manage
the low-level device control (like clocks, resets etc) for the various
hardware modules present on the SoC. These device control operations are
provided to the host processor OS through a communication protocol
called the TI System Control Interface (TI SCI) protocol.

This patch adds a reset driver that communicates to the system
controller over the TI SCI protocol for performing reset management of
various devices present on the SoC. Various reset functionalities are
achieved by the means of different TI SCI device operations provided by
the TI SCI framework.

This code is loosely based on the drivers/reset/reset-ti-sci.c driver of
the Linux kernel.

Reviewed-by: Tom Rini &lt;trini@konsulko.com&gt;
Signed-off-by: Andreas Dannenberg &lt;dannenberg@ti.com&gt;
Signed-off-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
</content>
</entry>
<entry>
<title>reset: socfpga: add reset driver for SoCFPGA platform</title>
<updated>2018-04-17T09:39:49Z</updated>
<author>
<name>Dinh Nguyen</name>
</author>
<published>2018-04-04T22:18:20Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=2ac718821a88885bd749976ff3ce6f853f2da0c9'/>
<id>urn:sha1:2ac718821a88885bd749976ff3ce6f853f2da0c9</id>
<content type='text'>
Add a DM compatible reset driver for the SoCFPGA platform.

Signed-off-by: Dinh Nguyen &lt;dinguyen@kernel.org&gt;
</content>
</entry>
<entry>
<title>reset: Add Amlogic Meson Reset Controller</title>
<updated>2018-04-10T15:52:16Z</updated>
<author>
<name>Neil Armstrong</name>
</author>
<published>2018-03-29T12:55:25Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=20367bb560f0bc3243ccac234ca7ae2ba8f94a5f'/>
<id>urn:sha1:20367bb560f0bc3243ccac234ca7ae2ba8f94a5f</id>
<content type='text'>
The Amlogic Meson SoCs embeds up to 256 reset lines, add the corresponding
driver.

Signed-off-by: Neil Armstrong &lt;narmstrong@baylibre.com&gt;
</content>
</entry>
<entry>
<title>reset: stm32: adapt driver for stm32mp1</title>
<updated>2018-03-19T20:14:22Z</updated>
<author>
<name>Patrick Delaunay</name>
</author>
<published>2018-03-12T09:46:14Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=a7519b3324258312558685bccaf8eb0dd039ac0c'/>
<id>urn:sha1:a7519b3324258312558685bccaf8eb0dd039ac0c</id>
<content type='text'>
- move to livetree and allow to get address to parent
- add stm32mp1 compatible for probe

Signed-off-by: Patrick Delaunay &lt;patrick.delaunay@st.com&gt;
</content>
</entry>
<entry>
<title>rockchip: reset: support a (common) rockchip reset drivers</title>
<updated>2018-01-09T10:13:32Z</updated>
<author>
<name>Elaine Zhang</name>
</author>
<published>2017-12-19T10:22:37Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=760188c1aa5b8b474340d3e090b4adc9400c2238'/>
<id>urn:sha1:760188c1aa5b8b474340d3e090b4adc9400c2238</id>
<content type='text'>
Create driver to support the soft reset (i.e. peripheral)
of all Rockchip SoCs.

Example of usage:
i2c driver:
	ret = reset_get_by_name(dev, "i2c", &amp;reset_ctl);
	if (ret) {
		error("reset_get_by_name() failed: %d\n", ret);
	}

	reset_assert(&amp;reset_ctl);
	udelay(50);
	reset_deassert(&amp;reset_ctl);

i2c dts node:
resets = &lt;&amp;cru SRST_P_I2C1&gt;, &lt;&amp;cru SRST_I2C1&gt;;
reset-names = "p_i2c", "i2c";

Signed-off-by: Elaine Zhang &lt;zhangqing@rock-chips.com&gt;
Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Acked-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
Reviewed-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
[Fixed commit tag:]
Signed-off-by: Philipp Tomsich &lt;philipp.tomsich@theobroma-systems.com&gt;
</content>
</entry>
<entry>
<title>dm: reset: add stm32 reset driver</title>
<updated>2017-09-22T11:40:01Z</updated>
<author>
<name>Patrice Chotard</name>
</author>
<published>2017-09-13T16:00:07Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=23a06416858d839ee62dc00562be956be6d84bd2'/>
<id>urn:sha1:23a06416858d839ee62dc00562be956be6d84bd2</id>
<content type='text'>
This driver is adapted from linux drivers/reset/reset-stm32.c
It's compatible with STM32 F4/F7/H7 SoCs.

This driver doesn't implement .of_match as it's binded
by MFD RCC driver.

To add support for each SoC family, a SoC's specific
include/dt-binfings/mfd/stm32xx-rcc.h file must be added.

This patch only includes stm32h7-rcc.h dedicated for STM32H7 SoCs.
Other SoCs support will be added in the future.

Signed-off-by: Patrice Chotard &lt;patrice.chotard@st.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
<entry>
<title>dm: reset: add BCM6345 reset driver</title>
<updated>2017-05-10T14:16:09Z</updated>
<author>
<name>Álvaro Fernández Rojas</name>
</author>
<published>2017-05-03T13:10:21Z</published>
<link rel='alternate' type='text/html' href='https://git.openwrt.org/project/bcm63xx/u-boot/commit/?id=18393f70f6854e80d34b3b12d3a9eca84bae0a45'/>
<id>urn:sha1:18393f70f6854e80d34b3b12d3a9eca84bae0a45</id>
<content type='text'>
This is a simplified version of linux/arch/mips/bcm63xx/reset.c

Signed-off-by: Álvaro Fernández Rojas &lt;noltari@gmail.com&gt;
Reviewed-by: Simon Glass &lt;sjg@chromium.org&gt;
</content>
</entry>
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