plat/bcm/include/pmc_addr_6813.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2019 Broadcom Ltd.
   4  */
   5 /*
   6 <:copyright-BRCM:2019:DUAL/GPL:standard
   7
   8    Copyright (c) 2019 Broadcom
   9    All Rights Reserved
  10
  11 Unless you and Broadcom execute a separate written software license
  12 agreement governing use of this software, this software is licensed
  13 to you under the terms of the GNU General Public License version 2
  14 (the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php,
  15 with the following added to such license:
  16
  17    As a special exception, the copyright holders of this software give
  18    you permission to link this software with independent modules, and
  19    to copy and distribute the resulting executable under terms of your
  20    choice, provided that you also meet, for each linked independent
  21    module, the terms and conditions of the license of that module.
  22    An independent module is a module which is not derived from this
  23    software.  The special exception does not apply to any modifications
  24    of the software.
  25
  26 Not withstanding the above, under no circumstances may you combine
  27 this software in any way with any other Broadcom software provided
  28 under a license other than the GPL, without Broadcom's express prior
  29 written consent.
  30
  31 :>
  32 */
  33
  34 #ifndef _6813_PMC_ADDR_H
  35 #define _6813_PMC_ADDR_H
  36
  37 #define PMB_BUS_MAX             2
  38 #define PMB_BUS_ID_SHIFT        12
  39
  40 #define PMB_BUS_PERIPH          0
  41 #define PMB_ADDR_PERIPH         (0 | PMB_BUS_PERIPH << PMB_BUS_ID_SHIFT)
  42 #define PMB_ZONES_PERIPH        4
  43
  44 #define PMB_BUS_CHIP_CLKRST     0
  45 #define PMB_ADDR_CHIP_CLKRST    (1 | PMB_BUS_CHIP_CLKRST << PMB_BUS_ID_SHIFT)
  46 #define PMB_ZONES_CHIP_CLKRST   0
  47
  48 #define PMB_BUS_PVTMON          1
  49 #define PMB_ADDR_PVTMON         (3 | PMB_BUS_PVTMON << PMB_BUS_ID_SHIFT)
  50 #define PMB_ZONES_PVTMON        0
  51
  52 #define PMB_BUS_CRYPTO          1
  53 #define PMB_ADDR_CRYPTO         (4 | PMB_BUS_CRYPTO << PMB_BUS_ID_SHIFT)
  54 #define PMB_ZONES_CRYPTO        0
  55
  56 #define PMB_BUS_USB30_2X        0
  57 #define PMB_ADDR_USB30_2X       (5 | PMB_BUS_USB30_2X << PMB_BUS_ID_SHIFT)
  58 #define PMB_ZONES_USB30_2X      4
  59
  60 #define PMB_BUS_PCIE1           1
  61 #define PMB_ADDR_PCIE1          (6 | PMB_BUS_PCIE1 << PMB_BUS_ID_SHIFT)
  62 #define PMB_ZONES_PCIE1         4
  63
  64 // referring to PCIEG3
  65 #define PMB_BUS_PCIE3           1
  66 #define PMB_ADDR_PCIE3          (7 | PMB_BUS_PCIE3 << PMB_BUS_ID_SHIFT)
  67 #define PMB_ZONES_PCIE3         1
  68
  69 #define PMB_BUS_MEMC            1
  70 #define PMB_ADDR_MEMC           (8 | PMB_BUS_MEMC << PMB_BUS_ID_SHIFT)
  71 #define PMB_ZONES_MEMC          1
  72
  73 #define PMB_BUS_XRDP            1
  74 #define PMB_ADDR_XRDP           (9 | PMB_BUS_XRDP << PMB_BUS_ID_SHIFT)
  75 #define PMB_ZONES_XRDP          1
  76
  77 #define PMB_BUS_PCIE2           1
  78 #define PMB_ADDR_PCIE2          (11 | PMB_BUS_PCIE2 << PMB_BUS_ID_SHIFT)
  79 #define PMB_ZONES_PCIE2         1
  80
  81 #define PMB_BUS_PCIE0           0
  82 #define PMB_ADDR_PCIE0          (12 | PMB_BUS_PCIE0 << PMB_BUS_ID_SHIFT)
  83 #define PMB_ZONES_PCIE0         1
  84
  85 #define PMB_BUS_ETH             1
  86 #define PMB_ADDR_ETH            (13 | PMB_BUS_ETH << PMB_BUS_ID_SHIFT)
  87 #define PMB_ZONES_ETH           1
  88
  89 #define PMB_BUS_MPM             1
  90 #define PMB_ADDR_MPM            (14 | PMB_BUS_MPM << PMB_BUS_ID_SHIFT)
  91 #define PMB_ZONES_MPM           1
  92
  93 #define PMB_BUS_XRDPPLL         0
  94 #define PMB_ADDR_XRDPPLL        (15 | PMB_BUS_XRDPPLL << PMB_BUS_ID_SHIFT)
  95 #define PMB_ZONES_XRDPPLL       0
  96
  97 #define PMB_BUS_PERIPH_ARS      0
  98 #define PMB_ADDR_PERIPH_ARS     (16 | PMB_BUS_PERIPH_ARS << PMB_BUS_ID_SHIFT)
  99 #define PMB_ZONES_PERIPH_ARS    0
 100
 101 #define PMB_BUS_PCIE0_UBUS_ARS  0
 102 #define PMB_ADDR_PCIE0_UBUS_ARS (17 | PMB_BUS_PCIE0_UBUS_ARS << PMB_BUS_ID_SHIFT)
 103 #define PMB_ZONES_PCIE0_UBUS_ARS 0
 104
 105 #define PMB_BUS_USB30_2X_ARS    0
 106 #define PMB_ADDR_USB30_2X_ARS   (18 | PMB_BUS_USB30_2X_ARS << PMB_BUS_ID_SHIFT)
 107 #define PMB_ZONES_USB30_2X_ARS  0
 108
 109 #define PMB_BUS_SYS_ARS         0
 110 #define PMB_ADDR_SYS_ARS        (19 | PMB_BUS_SYS_ARS << PMB_BUS_ID_SHIFT)
 111 #define PMB_ZONES_SYS_ARS       0
 112
 113 #define PMB_BUS_CRYPTO2_ARS     1
 114 #define PMB_ADDR_CRYPTO2_ARS    (20 | PMB_BUS_CRYPTO2_ARS << PMB_BUS_ID_SHIFT)
 115 #define PMB_ZONES_CRYPTO2_ARS   0
 116
 117 #define PMB_BUS_XRDP_ARS        1
 118 #define PMB_ADDR_XRDP_ARS       (21 | PMB_BUS_XRDP_ARS << PMB_BUS_ID_SHIFT)
 119 #define PMB_ZONES_XRDP_ARS      0
 120
 121 #define PMB_BUS_MPM_ARS         1
 122 #define PMB_ADDR_MPM_ARS        (22 | PMB_BUS_MPM_ARS << PMB_BUS_ID_SHIFT)
 123 #define PMB_ZONES_MPM_ARS       0
 124
 125 #define PMB_BUS_MEMC_ARS        1
 126 #define PMB_ADDR_MEMC_ARS       (23 | PMB_BUS_MEMC_ARS << PMB_BUS_ID_SHIFT)
 127 #define PMB_ZONES_MEMC_ARS      0
 128
 129 #define PMB_BUS_ETH_ARS         1
 130 #define PMB_ADDR_ETH_ARS        (24 | PMB_BUS_ETH_ARS << PMB_BUS_ID_SHIFT)
 131 #define PMB_ZONES_ETH_ARS       0
 132
 133 #define PMB_BUS_PCIE1_UBUS_ARS  1
 134 #define PMB_ADDR_PCIE1_UBUS_ARS (25 | PMB_BUS_PCIE1_UBUS_ARS << PMB_BUS_ID_SHIFT)
 135 #define PMB_ZONES_PCIE1_UBUS_ARS        0
 136
 137 #define PMB_BUS_PCIE3_ARS       1
 138 #define PMB_ADDR_PCIE3_ARS      (26 | PMB_BUS_PCIE3_ARS << PMB_BUS_ID_SHIFT)
 139 #define PMB_ZONES_PCIE3_ARS     0
 140
 141 #define PMB_BUS_MERLIN0_UBUS_ARS        1
 142 #define PMB_ADDR_MERLIN0_UBUS_ARS       (27 | PMB_BUS_MERLIN0_UBUS_ARS << PMB_BUS_ID_SHIFT)
 143 #define PMB_ZONES_MERLIN0_UBUS_ARS      0
 144
 145 #define PMB_BUS_MERLIN1_UBUS_ARS        1
 146 #define PMB_ADDR_MERLIN1_UBUS_ARS       (28 | PMB_BUS_MERLIN1_UBUS_ARS << PMB_BUS_ID_SHIFT)
 147 #define PMB_ZONES_MERLIN1_UBUS_ARS      0
 148
 149 #define PMB_BUS_MERLIN2_UBUS_ARS        1
 150 #define PMB_ADDR_MERLIN2_UBUS_ARS       (29 | PMB_BUS_MERLIN2_UBUS_ARS << PMB_BUS_ID_SHIFT)
 151 #define PMB_ZONES_MERLIN2_UBUS_ARS      0
 152
 153 #define PMB_BUS_ORION_PLL       1
 154 #define PMB_ADDR_ORION_PLL      (32 | PMB_BUS_ORION_PLL << PMB_BUS_ID_SHIFT)
 155 #define PMB_ZONES_ORION_PLL     0
 156 #define PMB_BUS_BIU_PLL         PMB_BUS_ORION_PLL
 157 #define PMB_ADDR_BIU_PLL        PMB_ADDR_ORION_PLL
 158 #define PMB_ZONES_BIU_PLL       PMB_ZONES_ORION_PLL
 159
 160 #define PMB_BUS_ORION_BPCM      1
 161 #define PMB_ADDR_ORION_BPCM     (33 | PMB_BUS_ORION_BPCM << PMB_BUS_ID_SHIFT)
 162 #define PMB_ZONES_ORION_BPCM    1
 163 #define PMB_BUS_BIU_BPCM        PMB_BUS_ORION_BPCM
 164 #define PMB_ADDR_BIU_BPCM       PMB_ADDR_ORION_BPCM
 165 #define PMB_ZONES_BIU_BPCM      PMB_ZONES_ORION_BPCM
 166
 167 #define PMB_BUS_ORION_CPU0      1
 168 #define PMB_ADDR_ORION_CPU0     (34 | PMB_BUS_ORION_CPU0 << PMB_BUS_ID_SHIFT)
 169 #define PMB_ZONES_ORION_CPU0    1
 170
 171 #define PMB_BUS_ORION_CPU1      1
 172 #define PMB_ADDR_ORION_CPU1     (35 | PMB_BUS_ORION_CPU1 << PMB_BUS_ID_SHIFT)
 173 #define PMB_ZONES_ORION_CPU1    1
 174
 175 #define PMB_BUS_ORION_CPU2      1
 176 #define PMB_ADDR_ORION_CPU2     (36 | PMB_BUS_ORION_CPU2 << PMB_BUS_ID_SHIFT)
 177 #define PMB_ZONES_ORION_CPU2    1
 178
 179 #define PMB_BUS_ORION_CPU3      1
 180 #define PMB_ADDR_ORION_CPU3     (37 | PMB_BUS_ORION_CPU3 << PMB_BUS_ID_SHIFT)
 181 #define PMB_ZONES_ORION_CPU3    1
 182
 183 #define PMB_BUS_ORION_NONCPU    1
 184 #define PMB_ADDR_ORION_NONCPU   (38 | PMB_BUS_ORION_NONCPU << PMB_BUS_ID_SHIFT)
 185 #define PMB_ZONES_ORION_NONCPU  1
 186
 187 #define PMB_BUS_ORION_ARS       1
 188 #define PMB_ADDR_ORION_ARS      (39 | PMB_BUS_ORION_ARS << PMB_BUS_ID_SHIFT)
 189 #define PMB_ZONES_ORION_ARS     0
 190
 191 #define PMB_BUS_ORION_ACEBIU_ARS        1
 192 #define PMB_ADDR_ORION_ACEBIU_ARS       (40 | PMB_BUS_ORION_ACEBIU_ARS << PMB_BUS_ID_SHIFT)
 193 #define PMB_ZONES_ORION_ACEBIU_ARS      0
 194 #endif