target/linux/ipq806x/patches-3.18/101-ARM-qcom-add-USB-nodes-to-ipq806x-ap148.patch

   1 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
   2 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
   3 @@ -109,5 +109,29 @@
   4                 sata@29000000 {
   5                         status = "ok";
   6                 };
   7 +
   8 +               phy@100f8800 {          /* USB3 port 1 HS phy */
   9 +                       status = "ok";
  10 +               };
  11 +
  12 +               phy@100f8830 {          /* USB3 port 1 SS phy */
  13 +                       status = "ok";
  14 +               };
  15 +
  16 +               phy@110f8800 {          /* USB3 port 0 HS phy */
  17 +                       status = "ok";
  18 +               };
  19 +
  20 +               phy@110f8830 {          /* USB3 port 0 SS phy */
  21 +                       status = "ok";
  22 +               };
  23 +
  24 +               usb30@0 {
  25 +                       status = "ok";
  26 +               };
  27 +
  28 +               usb30@1 {
  29 +                       status = "ok";
  30 +               };
  31         };
  32  };
  33 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
  34 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
  35 @@ -291,5 +291,90 @@
  36                         #clock-cells = <1>;
  37                         #reset-cells = <1>;
  38                 };
  39 +
  40 +               hs_phy_1: phy@100f8800 {
  41 +                       compatible = "qcom,dwc3-hs-usb-phy";
  42 +                       reg = <0x100f8800 0x30>;
  43 +                       clocks = <&gcc USB30_1_UTMI_CLK>;
  44 +                       clock-names = "ref";
  45 +                       #phy-cells = <0>;
  46 +
  47 +                       status = "disabled";
  48 +               };
  49 +
  50 +               ss_phy_1: phy@100f8830 {
  51 +                       compatible = "qcom,dwc3-ss-usb-phy";
  52 +                       reg = <0x100f8830 0x30>;
  53 +                       clocks = <&gcc USB30_1_MASTER_CLK>;
  54 +                       clock-names = "ref";
  55 +                       #phy-cells = <0>;
  56 +
  57 +                       status = "disabled";
  58 +               };
  59 +
  60 +               hs_phy_0: phy@110f8800 {
  61 +                       compatible = "qcom,dwc3-hs-usb-phy";
  62 +                       reg = <0x110f8800 0x30>;
  63 +                       clocks = <&gcc USB30_0_UTMI_CLK>;
  64 +                       clock-names = "ref";
  65 +                       #phy-cells = <0>;
  66 +
  67 +                       status = "disabled";
  68 +               };
  69 +
  70 +               ss_phy_0: phy@110f8830 {
  71 +                       compatible = "qcom,dwc3-ss-usb-phy";
  72 +                       reg = <0x110f8830 0x30>;
  73 +                       clocks = <&gcc USB30_0_MASTER_CLK>;
  74 +                       clock-names = "ref";
  75 +                       #phy-cells = <0>;
  76 +
  77 +                       status = "disabled";
  78 +               };
  79 +
  80 +               usb3_0: usb30@0 {
  81 +                       compatible = "qcom,dwc3";
  82 +                       #address-cells = <1>;
  83 +                       #size-cells = <1>;
  84 +                       clocks = <&gcc USB30_0_MASTER_CLK>;
  85 +                       clock-names = "core";
  86 +
  87 +                       ranges;
  88 +
  89 +                       status = "disabled";
  90 +
  91 +                       dwc3@11000000 {
  92 +                               compatible = "snps,dwc3";
  93 +                               reg = <0x11000000 0xcd00>;
  94 +                               interrupts = <0 110 0x4>;
  95 +                               phys = <&hs_phy_0>, <&ss_phy_0>;
  96 +                               phy-names = "usb2-phy", "usb3-phy";
  97 +                               tx-fifo-resize;
  98 +                               dr_mode = "host";
  99 +                       };
 100 +               };
 101 +
 102 +               usb3_1: usb30@1 {
 103 +                       compatible = "qcom,dwc3";
 104 +                       #address-cells = <1>;
 105 +                       #size-cells = <1>;
 106 +                       clocks = <&gcc USB30_1_MASTER_CLK>;
 107 +                       clock-names = "core";
 108 +
 109 +                       ranges;
 110 +
 111 +                       status = "disabled";
 112 +
 113 +                       dwc3@10000000 {
 114 +                               compatible = "snps,dwc3";
 115 +                               reg = <0x10000000 0xcd00>;
 116 +                               interrupts = <0 205 0x4>;
 117 +                               phys = <&hs_phy_1>, <&ss_phy_1>;
 118 +                               phy-names = "usb2-phy", "usb3-phy";
 119 +                               tx-fifo-resize;
 120 +                               dr_mode = "host";
 121 +                       };
 122 +               };
 123 +
 124         };
 125  };