1 From fe0ffa96c83e318d6b99fe31b5d121bdb05247f7 Mon Sep 17 00:00:00 2001
2 From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
3 Date: Tue, 24 May 2016 14:52:59 +0530
4 Subject: [PATCH 44/93] armv8: fsl-layerscape: Add support of GPIO structure
8 Layerscape supports GPIO registers to conrol GPIO singals.
10 Add support of GPIO structure to enable GPIO access.
12 Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
13 Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
15 .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 10 ++++++++++
16 1 file changed, 10 insertions(+)
18 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
19 index a264f9a..58c7205 100644
20 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
21 +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
23 #define CONFIG_SYS_PPFE_ADDR (CONFIG_SYS_IMMR + 0x3000000)
24 #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000)
25 #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
26 +#define CONFIG_SYS_GPIO1_ADDR (CONFIG_SYS_IMMR + 0x300000)
28 #define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000
30 @@ -650,6 +651,15 @@ struct ccsr_cci400 {
31 u8 res_e004[0x10000 - 0xe004];
34 +typedef struct ccsr_gpio {
44 #define SMMU_SCR0 (SMMU_BASE + 0x0)
45 #define SMMU_SCR1 (SMMU_BASE + 0x4)