uboot-mediatek: add build for BPi-R4
[openwrt/openwrt.git] / package / boot / uboot-mediatek / patches / 131-spi-mtk_spim-prevent-global-pll-clock-override.patch
1 From 41f225dae30ea6ddcff10f120a9e732f994d3a07 Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Nicol=C3=B2=20Veronese?= <nicveronese@gmail.com>
3 Date: Tue, 3 Oct 2023 23:46:52 +0200
4 Subject: [PATCH] spi: mtk_spim: prevent global pll clock override
5 MIME-Version: 1.0
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
8
9 With commit 793e6230118032a099ec42a1ea67f434721edcc0
10 a new system to calculate the SPI clocks has been added.
11
12 Unfortunately, the do_div macro overrides the global
13 priv->pll_clk_rate field. This will cause to have a reduced
14 clock rate on each subsequent SPI call.
15
16 Signed-off-by: Valerio 'ftp21' Mancini <ftp21@ftp21.eu>
17 Signed-off-by: Nicolò Veronese <nicveronese@gmail.com>
18 ---
19 drivers/spi/mtk_spim.c | 7 ++++---
20 1 file changed, 4 insertions(+), 3 deletions(-)
21
22 --- a/drivers/spi/mtk_spim.c
23 +++ b/drivers/spi/mtk_spim.c
24 @@ -409,7 +409,7 @@ static int mtk_spim_transfer_wait(struct
25 {
26 struct udevice *bus = dev_get_parent(slave->dev);
27 struct mtk_spim_priv *priv = dev_get_priv(bus);
28 - u32 sck_l, sck_h, clk_count, reg;
29 + u32 pll_clk, sck_l, sck_h, clk_count, reg;
30 ulong us = 1;
31 int ret = 0;
32
33 @@ -418,11 +418,12 @@ static int mtk_spim_transfer_wait(struct
34 else
35 clk_count = op->data.nbytes;
36
37 + pll_clk = priv->pll_clk_rate;
38 sck_l = readl(priv->base + SPI_CFG2_REG) >> SPI_CFG2_SCK_LOW_OFFSET;
39 sck_h = readl(priv->base + SPI_CFG2_REG) & SPI_CFG2_SCK_HIGH_MASK;
40 - do_div(priv->pll_clk_rate, sck_l + sck_h + 2);
41 + do_div(pll_clk, sck_l + sck_h + 2);
42
43 - us = CLK_TO_US(priv->pll_clk_rate, clk_count * 8);
44 + us = CLK_TO_US(pll_clk, clk_count * 8);
45 us += 1000 * 1000; /* 1s tolerance */
46
47 if (us > UINT_MAX)