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gpio-button-hotplug: add more buttons
[openwrt/openwrt.git] / package / kernel / lantiq / ltq-hcd / src / ifxusb_regs.h
1 /*****************************************************************************
2 ** FILE NAME : ifxusb_regs.h
3 ** PROJECT : IFX USB sub-system V3
4 ** MODULES : IFX USB sub-system Host and Device driver
5 ** SRC VERSION : 3.2
6 ** DATE : 1/Jan/2011
7 ** AUTHOR : Chen, Howard
8 ** DESCRIPTION : This file contains the data structures for accessing the IFXUSB core
9 ** registers.
10 ** The application interfaces with the USB core by reading from and
11 ** writing to the Control and Status Register (CSR) space through the
12 ** AHB Slave interface. These registers are 32 bits wide, and the
13 ** addresses are 32-bit-block aligned.
14 ** CSRs are classified as follows:
15 ** - Core Global Registers
16 ** - Device Mode Registers
17 ** - Device Global Registers
18 ** - Device Endpoint Specific Registers
19 ** - Host Mode Registers
20 ** - Host Global Registers
21 ** - Host Port CSRs
22 ** - Host Channel Specific Registers
23 **
24 ** Only the Core Global registers can be accessed in both Device and
25 ** Host modes. When the USB core is operating in one mode, either
26 ** Device or Host, the application must not access registers from the
27 ** other mode. When the core switches from one mode to another, the
28 ** registers in the new mode of operation must be reprogrammed as they
29 ** would be after a power-on reset.
30 ** FUNCTIONS :
31 ** COMPILER : gcc
32 ** REFERENCE : Synopsys DWC-OTG Driver 2.7
33 ** COPYRIGHT : Copyright (c) 2010
34 ** LANTIQ DEUTSCHLAND GMBH,
35 ** Am Campeon 3, 85579 Neubiberg, Germany
36 **
37 ** This program is free software; you can redistribute it and/or modify
38 ** it under the terms of the GNU General Public License as published by
39 ** the Free Software Foundation; either version 2 of the License, or
40 ** (at your option) any later version.
41 **
42 ** Version Control Section **
43 ** $Author$
44 ** $Date$
45 ** $Revisions$
46 ** $Log$ Revision history
47 *****************************************************************************/
48 /******************************************************************************
49 ** COPYRIGHT : Copyright (c) 2006
50 ** Infineon Technologies AG
51 ** Am Campeon 1-12, 85579 Neubiberg, Germany
52 **
53 ** This program is free software; you can redistribute it and/or modify
54 ** it under the terms of the GNU General Public License as published by
55 ** the Free Software Foundation; either version 2 of the License, or
56 ** (at your option) any later version.
57 **
58 ** HISTORY
59 ** $Date $Author $Comment
60 ** 10 NOV 2008 Wu Qi Ming Initial Version, to comply with COC
61 *******************************************************************************/
62
63
64 /*
65 * This file contains code fragments from Synopsys HS OTG Linux Software Driver.
66 * For this code the following notice is applicable:
67 *
68 * ==========================================================================
69 *
70 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
71 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
72 * otherwise expressly agreed to in writing between Synopsys and you.
73 *
74 * The Software IS NOT an item of Licensed Software or Licensed Product under
75 * any End User Software License Agreement or Agreement for Licensed Product
76 * with Synopsys or any supplement thereto. You are permitted to use and
77 * redistribute this Software in source and binary forms, with or without
78 * modification, provided that redistributions of source code must retain this
79 * notice. You may not view, use, disclose, copy or distribute this file or
80 * any information contained herein except pursuant to this license grant from
81 * Synopsys. If you do not agree with this notice, including the disclaimer
82 * below, then you are not authorized to use the Software.
83 *
84 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
85 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
86 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
87 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
88 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
89 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
90 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
91 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
92 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
93 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
94 * DAMAGE.
95 * ========================================================================== */
96
97
98 /*!
99 \defgroup IFXUSB_CSR_DEFINITION Control and Status Register bit-map definition
100 \ingroup IFXUSB_DRIVER_V3
101 \brief Data structures for accessing the IFXUSB core registers.
102 The application interfaces with the USB core by reading from and
103 writing to the Control and Status Register (CSR) space through the
104 AHB Slave interface. These registers are 32 bits wide, and the
105 addresses are 32-bit-block aligned.
106 CSRs are classified as follows:
107 - Core Global Registers
108 - Device Mode Registers
109 - Device Global Registers
110 - Device Endpoint Specific Registers
111 - Host Mode Registers
112 - Host Global Registers
113 - Host Port CSRs
114 - Host Channel Specific Registers
115
116 Only the Core Global registers can be accessed in both Device andHost modes.
117 When the USB core is operating in one mode, either Device or Host, the
118 application must not access registers from the other mode. When the core
119 switches from one mode to another, the registers in the new mode of operation
120 must be reprogrammed as they would be after a power-on reset.
121 */
122
123 /*!
124 \defgroup IFXUSB_CSR_DEVICE_GLOBAL_REG Device Mode Registers
125 \ingroup IFXUSB_CSR_DEFINITION
126 \brief Bit-mapped structure to access Device Mode Global Registers
127 */
128
129 /*!
130 \defgroup IFXUSB_CSR_DEVICE_EP_REG Device Mode EP Registers
131 \ingroup IFXUSB_CSR_DEFINITION
132 \brief Bit-mapped structure to access Device Mode EP Registers
133 There will be one set of endpoint registers per logical endpoint
134 implemented.
135 These registers are visible only in Device mode and must not be
136 accessed in Host mode, as the results are unknown.
137 */
138
139 /*!
140 \defgroup IFXUSB_CSR_DEVICE_DMA_DESC Device mode scatter dma descriptor strusture
141 \ingroup IFXUSB_CSR_DEFINITION
142 \brief Bit-mapped structure to DMA descriptor
143 */
144
145
146 /*!
147 \defgroup IFXUSB_CSR_HOST_GLOBAL_REG Host Mode Registers
148 \ingroup IFXUSB_CSR_DEFINITION
149 \brief Bit-mapped structure to access Host Mode Global Registers
150 */
151
152 /*!
153 \defgroup IFXUSB_CSR_HOST_HC_REG Host Mode HC Registers
154 \ingroup IFXUSB_CSR_DEFINITION
155 \brief Bit-mapped structure to access Host Mode Host Channel Registers
156 There will be one set of endpoint registers per host channel
157 implemented.
158 These registers are visible only in Host mode and must not be
159 accessed in Device mode, as the results are unknown.
160 */
161
162 /*!
163 \defgroup IFXUSB_CSR_PWR_CLK_GATING_REG Power and Clock Gating Control Register
164 \ingroup IFXUSB_CSR_DEFINITION
165 \brief Bit-mapped structure to Power and Clock Gating Control Register
166 */
167
168 /*!
169 \defgroup IFXUSB_CSR_CORE_GLOBAL_REG Core Global Registers
170 \ingroup IFXUSB_CSR_DEFINITION
171 \brief Bit-mapped structure to access Core Global Registers
172 */
173
174 /*!
175 \defgroup IFXUSB_CSR_CORE_GLOBAL_REG Core Global Registers
176 \ingroup IFXUSB_CSR_DEFINITION
177 \brief Bit-mapped structure to access Core Global Registers
178 */
179
180
181
182 /*!
183 \defgroup IFXUSB_CSR_ACCESS_MACROS Macros to manipulate CSRs
184 \ingroup IFXUSB_CSR_DEFINITION
185 \brief Macros to manipulate CSRs
186 */
187
188
189
190
191
192
193 /*!
194 \file ifxusb_regs.h
195 \ingroup IFXUSB_DRIVER_V3
196 \brief This file contains the data structures for accessing the IFXUSB core registers.
197 */
198
199
200 #ifndef __IFXUSB_REGS_H__
201 #define __IFXUSB_REGS_H__
202
203 /****************************************************************************/
204
205 #define MAX_PERIO_FIFOS 15 /** Maximum number of Periodic FIFOs */
206 #define MAX_TX_FIFOS 15 /** Maximum number of Periodic FIFOs */
207 #define MAX_EPS_CHANNELS 16 /** Maximum number of Endpoints/HostChannels */
208
209 /****************************************************************************/
210
211 //#define __RecordRegRW__
212
213 /*!
214 \fn static __inline__ uint32_t ifxusb_rreg( volatile uint32_t *_reg)
215 \brief Reads the content of a register.
216 \param _reg address of register to read.
217 \return contents of the register.
218 \ingroup IFXUSB_CSR_ACCESS_MACROS
219 */
220 static __inline__ uint32_t ifxusb_rreg( volatile uint32_t *_reg)
221 {
222 #ifdef __RecordRegRW__
223 uint32_t r;
224 r=*(_reg);
225 return (r);
226 #else
227 return (*(_reg));
228 #endif
229 };
230
231
232 /*!
233 \fn static __inline__ void ifxusb_wreg( volatile uint32_t *_reg, const uint32_t _value)
234 \brief Writes a register with a 32 bit value.
235 \param _reg address of register to write.
236 \param _value value to write to _reg.
237 \ingroup IFXUSB_CSR_ACCESS_MACROS
238 */
239 static __inline__ void ifxusb_wreg( volatile uint32_t *_reg, const uint32_t _value)
240 {
241 #ifdef __RecordRegRW__
242 printk(KERN_INFO "[W %p<-%08X]\n",_reg,_value);
243 #else
244 *(_reg)=_value;
245 #endif
246 };
247
248 /*!
249 \fn static __inline__ void ifxusb_mreg( volatile uint32_t *_reg, const uint32_t _clear_mask, const uint32_t _set_mask)
250 \brief Modifies bit values in a register. Using the
251 algorithm: (reg_contents & ~clear_mask) | set_mask.
252 \param _reg address of register to modify.
253 \param _clear_mask bit mask to be cleared.
254 \param _set_mask bit mask to be set.
255 \ingroup IFXUSB_CSR_ACCESS_MACROS
256 */
257 static __inline__ void ifxusb_mreg( volatile uint32_t *_reg, const uint32_t _clear_mask, const uint32_t _set_mask)
258 {
259 uint32_t v;
260 #ifdef __RecordRegRW__
261 uint32_t r;
262 v= *(_reg);
263 r=v;
264 r&=(~_clear_mask);
265 r|= _set_mask;
266 *(_reg)=r ;
267 printk(KERN_INFO "[M %p->%08X+%08X/%08X<-%08X]\n",_reg,r,_clear_mask,_set_mask,r);
268 #else
269 v= *(_reg);
270 v&=(~_clear_mask);
271 v|= _set_mask;
272 *(_reg)=v ;
273 #endif
274 };
275
276 /****************************************************************************/
277
278 /*!
279 \addtogroup IFXUSB_CSR_CORE_GLOBAL_REG
280 */
281 /*@{*/
282
283 /*! typedef ifxusb_core_global_regs_t
284 \brief IFXUSB Core registers .
285 The ifxusb_core_global_regs structure defines the size
286 and relative field offsets for the Core Global registers.
287 */
288 typedef struct ifxusb_core_global_regs
289 {
290 volatile uint32_t gotgctl; /*!< 000h OTG Control and Status Register. */
291 volatile uint32_t gotgint; /*!< 004h OTG Interrupt Register. */
292 volatile uint32_t gahbcfg; /*!< 008h Core AHB Configuration Register. */
293 volatile uint32_t gusbcfg; /*!< 00Ch Core USB Configuration Register. */
294 volatile uint32_t grstctl; /*!< 010h Core Reset Register. */
295 volatile uint32_t gintsts; /*!< 014h Core Interrupt Register. */
296 volatile uint32_t gintmsk; /*!< 018h Core Interrupt Mask Register. */
297 volatile uint32_t grxstsr; /*!< 01Ch Receive Status Queue Read Register (Read Only). */
298 volatile uint32_t grxstsp; /*!< 020h Receive Status Queue Read & POP Register (Read Only). */
299 volatile uint32_t grxfsiz; /*!< 024h Receive FIFO Size Register. */
300 volatile uint32_t gnptxfsiz; /*!< 028h Non Periodic Transmit FIFO Size Register. */
301 volatile uint32_t gnptxsts; /*!< 02Ch Non Periodic Transmit FIFO/Queue Status Register (Read Only). */
302 volatile uint32_t gi2cctl; /*!< 030h I2C Access Register. */
303 volatile uint32_t gpvndctl; /*!< 034h PHY Vendor Control Register. */
304 volatile uint32_t ggpio; /*!< 038h General Purpose Input/Output Register. */
305 volatile uint32_t guid; /*!< 03Ch User ID Register. */
306 volatile uint32_t gsnpsid; /*!< 040h Synopsys ID Register (Read Only). */
307 volatile uint32_t ghwcfg1; /*!< 044h User HW Config1 Register (Read Only). */
308 volatile uint32_t ghwcfg2; /*!< 048h User HW Config2 Register (Read Only). */
309 volatile uint32_t ghwcfg3; /*!< 04Ch User HW Config3 Register (Read Only). */
310 volatile uint32_t ghwcfg4; /*!< 050h User HW Config4 Register (Read Only). */
311 volatile uint32_t reserved[43]; /*!< 054h Reserved 054h-0FFh */
312 volatile uint32_t hptxfsiz; /*!< 100h Host Periodic Transmit FIFO Size Register. */
313 volatile uint32_t dptxfsiz_dieptxf[15];/*!< 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15.
314 Device Periodic Transmit FIFO#n Register if dedicated
315 fifos are disabled, otherwise Device Transmit FIFO#n
316 Register.
317 */
318 } ifxusb_core_global_regs_t;
319
320 /*!
321 \brief Bits of the Core OTG Control and Status Register (GOTGCTL).
322 */
323 typedef union gotgctl_data
324 {
325 uint32_t d32;
326 struct{
327 unsigned reserved21_31 : 11;
328 unsigned currmod : 1 ; /*!< 20 */
329 unsigned bsesvld : 1 ; /*!< 19 */
330 unsigned asesvld : 1 ; /*!< 18 */
331 unsigned reserved17 : 1 ;
332 unsigned conidsts : 1 ; /*!< 16 */
333 unsigned reserved12_15 : 4 ;
334 unsigned devhnpen : 1 ; /*!< 11 */
335 unsigned hstsethnpen : 1 ; /*!< 10 */
336 unsigned hnpreq : 1 ; /*!< 09 */
337 unsigned hstnegscs : 1 ; /*!< 08 */
338 unsigned reserved2_7 : 6 ;
339 unsigned sesreq : 1 ; /*!< 01 */
340 unsigned sesreqscs : 1 ; /*!< 00 */
341 } b;
342 } gotgctl_data_t;
343
344 /*!
345 \brief Bit fields of the Core OTG Interrupt Register (GOTGINT).
346 */
347 typedef union gotgint_data
348 {
349 uint32_t d32;
350 struct
351 {
352 unsigned reserved31_20 : 12;
353 unsigned debdone : 1 ; /*!< 19 Debounce Done */
354 unsigned adevtoutchng : 1 ; /*!< 18 A-Device Timeout Change */
355 unsigned hstnegdet : 1 ; /*!< 17 Host Negotiation Detected */
356 unsigned reserver10_16 : 7 ;
357 unsigned hstnegsucstschng : 1 ; /*!< 09 Host Negotiation Success Status Change */
358 unsigned sesreqsucstschng : 1 ; /*!< 08 Session Request Success Status Change */
359 unsigned reserved3_7 : 5 ;
360 unsigned sesenddet : 1 ; /*!< 02 Session End Detected */
361 unsigned reserved0_1 : 2 ;
362 } b;
363 } gotgint_data_t;
364
365 /*!
366 \brief Bit fields of the Core AHB Configuration Register (GAHBCFG).
367 */
368 typedef union gahbcfg_data
369 {
370 uint32_t d32;
371 struct
372 {
373 unsigned reserved9_31 : 23;
374 unsigned ptxfemplvl : 1 ; /*!< 08 Periodic FIFO empty level trigger condition*/
375 unsigned nptxfemplvl : 1 ; /*!< 07 Non-Periodic FIFO empty level trigger condition*/
376 #define IFXUSB_GAHBCFG_TXFEMPTYLVL_EMPTY 1
377 #define IFXUSB_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0
378 unsigned reserved : 1 ;
379 unsigned dmaenable : 1 ; /*!< 05 DMA enable*/
380 #define IFXUSB_GAHBCFG_DMAENABLE 1
381 unsigned hburstlen : 4 ; /*!< 01-04 DMA Burst-length*/
382 #define IFXUSB_GAHBCFG_INT_DMA_BURST_SINGLE 0
383 #define IFXUSB_GAHBCFG_INT_DMA_BURST_INCR 1
384 #define IFXUSB_GAHBCFG_INT_DMA_BURST_INCR4 3
385 #define IFXUSB_GAHBCFG_INT_DMA_BURST_INCR8 5
386 #define IFXUSB_GAHBCFG_INT_DMA_BURST_INCR16 7
387 unsigned glblintrmsk : 1 ; /*!< 00 USB Global Interrupt Enable */
388 #define IFXUSB_GAHBCFG_GLBINT_ENABLE 1
389 } b;
390 } gahbcfg_data_t;
391
392 /*!
393 \brief Bit fields of the Core USB Configuration Register (GUSBCFG).
394 */
395 typedef union gusbcfg_data
396 {
397 uint32_t d32;
398 struct
399 {
400 unsigned reserved31 : 1;
401 unsigned ForceDevMode : 1; /*!< 30 Force Device Mode */
402 unsigned ForceHstMode : 1; /*!< 29 Force Host Mode */
403 unsigned TxEndDelay : 1; /*!< 28 Tx End Delay */
404 unsigned reserved2723 : 5;
405 unsigned term_sel_dl_pulse : 1; /*!< 22 TermSel DLine Pulsing Selection */
406 unsigned reserved2117 : 5;
407 unsigned otgutmifssel : 1; /*!< 16 UTMIFS Select */
408 unsigned phylpwrclksel : 1; /*!< 15 PHY Low-Power Clock Select */
409 unsigned reserved14 : 1;
410 unsigned usbtrdtim : 4; /*!< 13-10 USB Turnaround Time */
411 unsigned hnpcap : 1; /*!< 09 HNP-Capable */
412 unsigned srpcap : 1; /*!< 08 SRP-Capable */
413 unsigned reserved07 : 1;
414 unsigned physel : 1; /*!< 06 USB 2.0 High-Speed PHY or
415 USB 1.1 Full-Speed Serial
416 Transceiver Select */
417 unsigned fsintf : 1; /*!< 05 Full-Speed Serial Interface Select */
418 unsigned ulpi_utmi_sel : 1; /*!< 04 ULPI or UTMI+ Select */
419 unsigned phyif : 1; /*!< 03 PHY Interface */
420 unsigned toutcal : 3; /*!< 00-02 HS/FS Timeout Calibration */
421 }b;
422 } gusbcfg_data_t;
423
424 /*!
425 \brief Bit fields of the Core Reset Register (GRSTCTL).
426 */
427 typedef union grstctl_data
428 {
429 uint32_t d32;
430 struct
431 {
432 unsigned ahbidle : 1; /*!< 31 AHB Master Idle. Indicates the AHB Master State
433 Machine is in IDLE condition. */
434 unsigned dmareq : 1; /*!< 30 DMA Request Signal. Indicated DMA request is in
435 probress. Used for debug purpose. */
436 unsigned reserved11_29 :19;
437 unsigned txfnum : 5; /*!< 10-06 TxFIFO Number (TxFNum) to be flushed.
438 0x00: Non Periodic TxFIFO Flush or TxFIFO 0
439 0x01-0x0F: Periodic TxFIFO Flush or TxFIFO n
440 0x10: Flush all TxFIFO
441 */
442 unsigned txfflsh : 1; /*!< 05 TxFIFO Flush */
443 unsigned rxfflsh : 1; /*!< 04 RxFIFO Flush */
444 unsigned intknqflsh : 1; /*!< 03 In Token Sequence Learning Queue Flush (Device Only) */
445 unsigned hstfrm : 1; /*!< 02 Host Frame Counter Reset (Host Only) */
446 unsigned hsftrst : 1; /*!< 01 Hclk Soft Reset */
447
448 unsigned csftrst : 1; /*!< 00 Core Soft Reset
449 The application can flush the control logic in the
450 entire core using this bit. This bit resets the
451 pipelines in the AHB Clock domain as well as the
452 PHY Clock domain.
453 The state machines are reset to an IDLE state, the
454 control bits in the CSRs are cleared, all the
455 transmit FIFOs and the receive FIFO are flushed.
456 The status mask bits that control the generation of
457 the interrupt, are cleared, to clear the
458 interrupt. The interrupt status bits are not
459 cleared, so the application can get the status of
460 any events that occurred in the core after it has
461 set this bit.
462 Any transactions on the AHB are terminated as soon
463 as possible following the protocol. Any
464 transactions on the USB are terminated immediately.
465 The configuration settings in the CSRs are
466 unchanged, so the software doesn't have to
467 reprogram these registers (Device
468 Configuration/Host Configuration/Core System
469 Configuration/Core PHY Configuration).
470 The application can write to this bit, any time it
471 wants to reset the core. This is a self clearing
472 bit and the core clears this bit after all the
473 necessary logic is reset in the core, which may
474 take several clocks, depending on the current state
475 of the core.
476 */
477 }b;
478 } grstctl_t;
479
480 /*!
481 \brief Bit fields of the Core Interrupt Mask Register (GINTMSK) and
482 Core Interrupt Register (GINTSTS).
483 */
484 typedef union gint_data
485 {
486 uint32_t d32;
487 #define IFXUSB_SOF_INTR_MASK 0x0008
488 struct
489 {
490 unsigned wkupintr : 1; /*!< 31 Resume/Remote Wakeup Detected Interrupt */
491 unsigned sessreqintr : 1; /*!< 30 Session Request/New Session Detected Interrupt */
492 unsigned disconnect : 1; /*!< 29 Disconnect Detected Interrupt */
493 unsigned conidstschng : 1; /*!< 28 Connector ID Status Change */
494 unsigned reserved27 : 1;
495 unsigned ptxfempty : 1; /*!< 26 Periodic TxFIFO Empty */
496 unsigned hcintr : 1; /*!< 25 Host Channels Interrupt */
497 unsigned portintr : 1; /*!< 24 Host Port Interrupt */
498 unsigned reserved23 : 1;
499 unsigned fetsuspmsk : 1; /*!< 22 Data Fetch Suspended */
500 unsigned incomplisoout : 1; /*!< 21 Incomplete IsochronousOUT/Period Transfer */
501 unsigned incomplisoin : 1; /*!< 20 Incomplete Isochronous IN Transfer */
502 unsigned outepintr : 1; /*!< 19 OUT Endpoints Interrupt */
503 unsigned inepintr : 1; /*!< 18 IN Endpoints Interrupt */
504 unsigned epmismatch : 1; /*!< 17 Endpoint Mismatch Interrupt */
505 unsigned reserved16 : 1;
506 unsigned eopframe : 1; /*!< 15 End of Periodic Frame Interrupt */
507 unsigned isooutdrop : 1; /*!< 14 Isochronous OUT Packet Dropped Interrupt */
508 unsigned enumdone : 1; /*!< 13 Enumeration Done */
509 unsigned usbreset : 1; /*!< 12 USB Reset */
510 unsigned usbsuspend : 1; /*!< 11 USB Suspend */
511 unsigned erlysuspend : 1; /*!< 10 Early Suspend */
512 unsigned i2cintr : 1; /*!< 09 I2C Interrupt */
513 unsigned reserved8 : 1;
514 unsigned goutnakeff : 1; /*!< 07 Global OUT NAK Effective */
515 unsigned ginnakeff : 1; /*!< 06 Global Non-periodic IN NAK Effective */
516 unsigned nptxfempty : 1; /*!< 05 Non-periodic TxFIFO Empty */
517 unsigned rxstsqlvl : 1; /*!< 04 Receive FIFO Non-Empty */
518 unsigned sofintr : 1; /*!< 03 Start of (u)Frame */
519 unsigned otgintr : 1; /*!< 02 OTG Interrupt */
520 unsigned modemismatch : 1; /*!< 01 Mode Mismatch Interrupt */
521 unsigned reserved0 : 1;
522 } b;
523 } gint_data_t;
524
525 /*!
526 \brief Bit fields in the Receive Status Read and Pop Registers (GRXSTSR, GRXSTSP)
527 */
528 typedef union grxsts_data
529 {
530 uint32_t d32;
531 struct
532 {
533 unsigned reserved : 7;
534 unsigned fn : 4; /*!< 24-21 Frame Number */
535 unsigned pktsts : 4; /*!< 20-17 Packet Status */
536 #define IFXUSB_DSTS_DATA_UPDT 0x2 // OUT Data Packet
537 #define IFXUSB_DSTS_XFER_COMP 0x3 // OUT Data Transfer Complete
538 #define IFXUSB_DSTS_GOUT_NAK 0x1 // Global OUT NAK
539 #define IFXUSB_DSTS_SETUP_COMP 0x4 // Setup Phase Complete
540 #define IFXUSB_DSTS_SETUP_UPDT 0x6 // SETUP Packet
541 unsigned dpid : 2; /*!< 16-15 Data PID */
542 unsigned bcnt :11; /*!< 14-04 Byte Count */
543 unsigned epnum : 4; /*!< 03-00 Endpoint Number */
544 } db;
545 struct
546 {
547 unsigned reserved :11;
548 unsigned pktsts : 4; /*!< 20-17 Packet Status */
549 #define IFXUSB_HSTS_DATA_UPDT 0x2 // OUT Data Packet
550 #define IFXUSB_HSTS_XFER_COMP 0x3 // OUT Data Transfer Complete
551 #define IFXUSB_HSTS_DATA_TOGGLE_ERR 0x5 // DATA TOGGLE Error
552 #define IFXUSB_HSTS_CH_HALTED 0x7 // Channel Halted
553 unsigned dpid : 2; /*!< 16-15 Data PID */
554 unsigned bcnt :11; /*!< 14-04 Byte Count */
555 unsigned chnum : 4; /*!< 03-00 Channel Number */
556 } hb;
557 } grxsts_data_t;
558
559 /*!
560 \brief Bit fields in the FIFO Size Registers (HPTXFSIZ, GNPTXFSIZ, DPTXFSIZn).
561 */
562 typedef union fifosize_data
563 {
564 uint32_t d32;
565 struct
566 {
567 unsigned depth : 16; /*!< 31-16 TxFIFO Depth (in DWord)*/
568 unsigned startaddr : 16; /*!< 15-00 RAM Starting address */
569 } b;
570 } fifosize_data_t;
571
572 /*!
573 \brief Bit fields in the Non-Periodic Transmit FIFO/Queue Status Register (GNPTXSTS).
574 */
575
576 typedef union gnptxsts_data
577 {
578 uint32_t d32;
579 struct
580 {
581 unsigned reserved : 1;
582 unsigned nptxqtop_chnep : 4; /*!< 30-27 Channel/EP Number of top of the Non-Periodic
583 Transmit Request Queue
584 */
585 unsigned nptxqtop_token : 2; /*!< 26-25 Token Type top of the Non-Periodic
586 Transmit Request Queue
587 0 - IN/OUT
588 1 - Zero Length OUT
589 2 - PING/Complete Split
590 3 - Channel Halt
591 */
592 unsigned nptxqtop_terminate : 1; /*!< 24 Terminate (Last entry for the selected
593 channel/EP)*/
594 unsigned nptxqspcavail : 8; /*!< 23-16 Transmit Request Queue Space Available */
595 unsigned nptxfspcavail :16; /*!< 15-00 TxFIFO Space Avail (in DWord)*/
596 }b;
597 } gnptxsts_data_t;
598
599
600 /*!
601 \brief Bit fields in the Transmit FIFO Status Register (DTXFSTS).
602 */
603 typedef union dtxfsts_data
604 {
605 uint32_t d32;
606 struct
607 {
608 unsigned reserved : 16;
609 unsigned txfspcavail : 16; /*!< 15-00 TxFIFO Space Avail (in DWord)*/
610 }b;
611 } dtxfsts_data_t;
612
613
614 /*!
615 \brief Bit fields in the I2C Control Register (I2CCTL).
616 */
617 typedef union gi2cctl_data
618 {
619 uint32_t d32;
620 struct
621 {
622 unsigned bsydne : 1; /*!< 31 I2C Busy/Done*/
623 unsigned rw : 1; /*!< 30 Read/Write Indicator */
624 unsigned reserved : 2;
625 unsigned i2cdevaddr : 2; /*!< 27-26 I2C Device Address */
626 unsigned i2csuspctl : 1; /*!< 25 I2C Suspend Control */
627 unsigned ack : 1; /*!< 24 I2C ACK */
628 unsigned i2cen : 1; /*!< 23 I2C Enable */
629 unsigned addr : 7; /*!< 22-16 I2C Address */
630 unsigned regaddr : 8; /*!< 15-08 I2C Register Addr */
631 unsigned rwdata : 8; /*!< I2C Read/Write Data */
632 } b;
633 } gi2cctl_data_t;
634
635
636 /*!
637 \brief Bit fields in the User HW Config1 Register.
638 */
639 typedef union hwcfg1_data
640 {
641 uint32_t d32;
642 struct
643 {
644 unsigned ep_dir15 : 2; /*!< Direction of each EP
645 0: BIDIR (IN and OUT) endpoint
646 1: IN endpoint
647 2: OUT endpoint
648 3: Reserved
649 */
650 unsigned ep_dir14 : 2;
651 unsigned ep_dir13 : 2;
652 unsigned ep_dir12 : 2;
653 unsigned ep_dir11 : 2;
654 unsigned ep_dir10 : 2;
655 unsigned ep_dir09 : 2;
656 unsigned ep_dir08 : 2;
657 unsigned ep_dir07 : 2;
658 unsigned ep_dir06 : 2;
659 unsigned ep_dir05 : 2;
660 unsigned ep_dir04 : 2;
661 unsigned ep_dir03 : 2;
662 unsigned ep_dir02 : 2;
663 unsigned ep_dir01 : 2;
664 unsigned ep_dir00 : 2;
665 }b;
666 } hwcfg1_data_t;
667
668 /*!
669 \brief Bit fields in the User HW Config2 Register.
670 */
671 typedef union hwcfg2_data
672 {
673 uint32_t d32;
674 struct
675 {
676 unsigned reserved31 : 1;
677 unsigned dev_token_q_depth : 5; /*!< 30-26 Device Mode IN Token Sequence Learning Queue Depth */
678 unsigned host_perio_tx_q_depth : 2; /*!< 25-24 Host Mode Periodic Request Queue Depth */
679 unsigned nonperio_tx_q_depth : 2; /*!< 23-22 Non-periodic Request Queue Depth */
680 unsigned rx_status_q_depth : 2; /*!< 21-20 Multi Processor Interrupt Enabled */
681 unsigned dynamic_fifo : 1; /*!< 19 Dynamic FIFO Sizing Enabled */
682 unsigned perio_ep_supported : 1; /*!< 18 Periodic OUT Channels Supported in Host Mode */
683 unsigned num_host_chan : 4; /*!< 17-14 Number of Host Channels */
684 unsigned num_dev_ep : 4; /*!< 13-10 Number of Device Endpoints */
685 unsigned fs_phy_type : 2; /*!< 09-08 Full-Speed PHY Interface Type */
686 #define IFXUSB_HWCFG2_FS_PHY_TYPE_NOT_SUPPORTED 0
687 #define IFXUSB_HWCFG2_FS_PHY_TYPE_DEDICATE 1
688 #define IFXUSB_HWCFG2_FS_PHY_TYPE_UTMI 2
689 #define IFXUSB_HWCFG2_FS_PHY_TYPE_ULPI 3
690 unsigned hs_phy_type : 2; /*!< 07-06 High-Speed PHY Interface Type */
691 #define IFXUSB_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
692 #define IFXUSB_HWCFG2_HS_PHY_TYPE_UTMI 1
693 #define IFXUSB_HWCFG2_HS_PHY_TYPE_ULPI 2
694 #define IFXUSB_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
695 unsigned point2point : 1; /*!< 05 Point-to-Point */
696 unsigned architecture : 2; /*!< 04-03 Architecture */
697 #define IFXUSB_HWCFG2_ARCH_SLAVE_ONLY 0
698 #define IFXUSB_HWCFG2_ARCH_EXT_DMA 1
699 #define IFXUSB_HWCFG2_ARCH_INT_DMA 2
700 unsigned op_mode : 3; /*!< 02-00 Mode of Operation */
701 #define IFXUSB_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0
702 #define IFXUSB_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1
703 #define IFXUSB_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2
704 #define IFXUSB_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
705 #define IFXUSB_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
706 #define IFXUSB_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
707 #define IFXUSB_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
708 } b;
709 } hwcfg2_data_t;
710
711 /*!
712 \brief Bit fields in the User HW Config3 Register.
713 */
714 typedef union hwcfg3_data
715 {
716 uint32_t d32;
717 struct
718 {
719 unsigned dfifo_depth :16; /*!< 31-16 DFIFO Depth */
720 unsigned reserved15_12 : 4;
721 unsigned synch_reset_type : 1; /*!< 11 Reset Style for Clocked always Blocks in RTL */
722 unsigned optional_features : 1; /*!< 10 Optional Features Removed */
723 unsigned vendor_ctrl_if : 1; /*!< 09 Vendor Control Interface Support */
724 unsigned i2c : 1; /*!< 08 I2C Selection */
725 unsigned otg_func : 1; /*!< 07 OTG Function Enabled */
726 unsigned packet_size_cntr_width : 3; /*!< 06-04 Width of Packet Size Counters */
727 unsigned xfer_size_cntr_width : 4; /*!< 03-00 Width of Transfer Size Counters */
728 } b;
729 } hwcfg3_data_t;
730
731 /*!
732 \brief Bit fields in the User HW Config4
733 * Register. Read the register into the <i>d32</i> element then read
734 * out the bits using the <i>b</i>it elements.
735 */
736 typedef union hwcfg4_data
737 {
738 uint32_t d32;
739 struct
740 {
741 unsigned desc_dma_dyn : 1; /*!< 31 Scatter/Gather DMA */
742 unsigned desc_dma : 1; /*!< 30 Scatter/Gather DMA configuration */
743 unsigned num_in_eps : 4; /*!< 29-26 Number of Device Mode IN Endpoints Including Control Endpoints */
744 unsigned ded_fifo_en : 1; /*!< 25 Enable Dedicated Transmit FIFO for device IN Endpoints */
745 unsigned session_end_filt_en : 1; /*!< 24 session_end Filter Enabled */
746 unsigned b_valid_filt_en : 1; /*!< 23 b_valid Filter Enabled */
747 unsigned a_valid_filt_en : 1; /*!< 22 a_valid Filter Enabled */
748 unsigned vbus_valid_filt_en : 1; /*!< 21 vbus_valid Filter Enabled */
749 unsigned iddig_filt_en : 1; /*!< 20 iddig Filter Enable */
750 unsigned num_dev_mode_ctrl_ep : 4; /*!< 19-16 Number of Device Mode Control Endpoints in Addition to Endpoint 0 */
751 unsigned utmi_phy_data_width : 2; /*!< 15-14 UTMI+ PHY/ULPI-to-Internal UTMI+ Wrapper Data Width */
752 unsigned reserved13_06 : 8;
753 unsigned min_ahb_freq : 1; /*!< 05 Minimum AHB Frequency Less Than 60 MHz */
754 unsigned power_optimiz : 1; /*!< 04 Enable Power Optimization? */
755 unsigned num_dev_perio_in_ep : 4; /*!< 03-00 Number of Device Mode Periodic IN Endpoints */
756 } b;
757 } hwcfg4_data_t;
758
759 /*@}*//*IFXUSB_CSR_CORE_GLOBAL_REG*/
760
761 /****************************************************************************/
762 /*!
763 \addtogroup IFXUSB_CSR_DEVICE_GLOBAL_REG
764 */
765 /*@{*/
766
767 /*! typedef ifxusb_dev_global_regs_t
768 \brief IFXUSB Device Mode Global registers. Offsets 800h-BFFh
769 The ifxusb_dev_global_regs structure defines the size
770 and relative field offsets for the Device Global registers.
771 These registers are visible only in Device mode and must not be
772 accessed in Host mode, as the results are unknown.
773 */
774 typedef struct ifxusb_dev_global_regs
775 {
776 volatile uint32_t dcfg; /*!< 800h Device Configuration Register. */
777 volatile uint32_t dctl; /*!< 804h Device Control Register. */
778 volatile uint32_t dsts; /*!< 808h Device Status Register (Read Only). */
779 uint32_t unused;
780 volatile uint32_t diepmsk; /*!< 810h Device IN Endpoint Common Interrupt Mask Register. */
781 volatile uint32_t doepmsk; /*!< 814h Device OUT Endpoint Common Interrupt Mask Register. */
782 volatile uint32_t daint; /*!< 818h Device All Endpoints Interrupt Register. */
783 volatile uint32_t daintmsk; /*!< 81Ch Device All Endpoints Interrupt Mask Register. */
784 volatile uint32_t dtknqr1; /*!< 820h Device IN Token Queue Read Register-1 (Read Only). */
785 volatile uint32_t dtknqr2; /*!< 824h Device IN Token Queue Read Register-2 (Read Only). */
786 volatile uint32_t dvbusdis; /*!< 828h Device VBUS discharge Register.*/
787 volatile uint32_t dvbuspulse; /*!< 82Ch Device VBUS Pulse Register. */
788 volatile uint32_t dtknqr3_dthrctl; /*!< 830h Device IN Token Queue Read Register-3 (Read Only).
789 Device Thresholding control register (Read/Write)
790 */
791 volatile uint32_t dtknqr4_fifoemptymsk; /*!< 834h Device IN Token Queue Read Register-4 (Read Only).
792 Device IN EPs empty Inr. Mask Register (Read/Write)
793 */
794 } ifxusb_device_global_regs_t;
795
796 /*!
797 \brief Bit fields in the Device Configuration Register.
798 */
799
800 typedef union dcfg_data
801 {
802 uint32_t d32;
803 struct
804 {
805 unsigned reserved31_26 : 6;
806 unsigned perschintvl : 2; /*!< 25-24 Periodic Scheduling Interval */
807 unsigned descdma : 1; /*!< 23 Enable Descriptor DMA in Device mode */
808 unsigned epmscnt : 5; /*!< 22-18 In Endpoint Mis-match count */
809 unsigned reserved13_17 : 5;
810 unsigned perfrint : 2; /*!< 12-11 Periodic Frame Interval */
811 #define IFXUSB_DCFG_FRAME_INTERVAL_80 0
812 #define IFXUSB_DCFG_FRAME_INTERVAL_85 1
813 #define IFXUSB_DCFG_FRAME_INTERVAL_90 2
814 #define IFXUSB_DCFG_FRAME_INTERVAL_95 3
815 unsigned devaddr : 7; /*!< 10-04 Device Addresses */
816 unsigned reserved3 : 1;
817 unsigned nzstsouthshk : 1; /*!< 02 Non Zero Length Status OUT Handshake */
818 #define IFXUSB_DCFG_SEND_STALL 1
819 unsigned devspd : 2; /*!< 01-00 Device Speed */
820 } b;
821 } dcfg_data_t;
822
823 /*!
824 \brief Bit fields in the Device Control Register.
825 */
826 typedef union dctl_data
827 {
828 uint32_t d32;
829 struct
830 {
831 unsigned reserved16_31 :16;
832 unsigned ifrmnum : 1; /*!< 15 Ignore Frame Number for ISOC EPs */
833 unsigned gmc : 2; /*!< 14-13 Global Multi Count */
834 unsigned gcontbna : 1; /*!< 12 Global Continue on BNA */
835 unsigned pwronprgdone : 1; /*!< 11 Power-On Programming Done */
836 unsigned cgoutnak : 1; /*!< 10 Clear Global OUT NAK */
837 unsigned sgoutnak : 1; /*!< 09 Set Global OUT NAK */
838 unsigned cgnpinnak : 1; /*!< 08 Clear Global Non-Periodic IN NAK */
839 unsigned sgnpinnak : 1; /*!< 07 Set Global Non-Periodic IN NAK */
840 unsigned tstctl : 3; /*!< 06-04 Test Control */
841 unsigned goutnaksts : 1; /*!< 03 Global OUT NAK Status */
842 unsigned gnpinnaksts : 1; /*!< 02 Global Non-Periodic IN NAK Status */
843 unsigned sftdiscon : 1; /*!< 01 Soft Disconnect */
844 unsigned rmtwkupsig : 1; /*!< 00 Remote Wakeup */
845 } b;
846 } dctl_data_t;
847
848
849 /*!
850 \brief Bit fields in the Device Status Register.
851 */
852 typedef union dsts_data
853 {
854 uint32_t d32;
855 struct
856 {
857 unsigned reserved22_31 :10;
858 unsigned soffn :14; /*!< 21-08 Frame or Microframe Number of the received SOF */
859 unsigned reserved4_7 : 4;
860 unsigned errticerr : 1; /*!< 03 Erratic Error */
861 unsigned enumspd : 2; /*!< 02-01 Enumerated Speed */
862 #define IFXUSB_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
863 #define IFXUSB_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
864 #define IFXUSB_DSTS_ENUMSPD_LS_PHY_6MHZ 2
865 #define IFXUSB_DSTS_ENUMSPD_FS_PHY_48MHZ 3
866 unsigned suspsts : 1; /*!< 00 Suspend Status */
867 } b;
868 } dsts_data_t;
869
870 /*!
871 \brief Bit fields in the Device IN EP Interrupt Register
872 and the Device IN EP Common Mask Register.
873 */
874 typedef union diepint_data
875 {
876 uint32_t d32;
877 struct
878 {
879 unsigned reserved14_31 :18;
880 unsigned nakmsk : 1; /*!< 13 NAK interrupt Mask */
881 unsigned reserved10_12 : 3;
882 unsigned bna : 1; /*!< 09 BNA Interrupt mask */
883 unsigned txfifoundrn : 1; /*!< 08 Fifo Underrun Mask */
884 unsigned emptyintr : 1; /*!< 07 IN Endpoint HAK Effective mask */
885 unsigned inepnakeff : 1; /*!< 06 IN Endpoint HAK Effective mask */
886 unsigned intknepmis : 1; /*!< 05 IN Token Received with EP mismatch mask */
887 unsigned intktxfemp : 1; /*!< 04 IN Token received with TxF Empty mask */
888 unsigned timeout : 1; /*!< 03 TimeOUT Handshake mask (non-ISOC EPs) */
889 unsigned ahberr : 1; /*!< 02 AHB Error mask */
890 unsigned epdisabled : 1; /*!< 01 Endpoint disable mask */
891 unsigned xfercompl : 1; /*!< 00 Transfer complete mask */
892 } b;
893 } diepint_data_t;
894
895
896 /*!
897 \brief Bit fields in the Device OUT EP Interrupt Register and
898 Device OUT EP Common Interrupt Mask Register.
899 */
900 typedef union doepint_data
901 {
902 uint32_t d32;
903 struct
904 {
905 unsigned reserved15_31 :17;
906 unsigned nyetmsk : 1; /*!< 14 NYET Interrupt */
907 unsigned nakmsk : 1; /*!< 13 NAK Interrupt */
908 unsigned bbleerrmsk : 1; /*!< 12 Babble Interrupt */
909 unsigned reserved10_11 : 2;
910 unsigned bna : 1; /*!< 09 BNA Interrupt */
911 unsigned outpkterr : 1; /*!< 08 OUT packet Error */
912 unsigned reserved07 : 1;
913 unsigned back2backsetup : 1; /*!< 06 Back-to-Back SETUP Packets Received */
914 unsigned stsphsercvd : 1; /*!< 05 */
915 unsigned outtknepdis : 1; /*!< 04 OUT Token Received when Endpoint Disabled */
916 unsigned setup : 1; /*!< 03 Setup Phase Done (contorl EPs) */
917 unsigned ahberr : 1; /*!< 02 AHB Error */
918 unsigned epdisabled : 1; /*!< 01 Endpoint disable */
919 unsigned xfercompl : 1; /*!< 00 Transfer complete */
920 } b;
921 } doepint_data_t;
922
923
924 /*!
925 \brief Bit fields in the Device All EP Interrupt Registers.
926 */
927 typedef union daint_data
928 {
929 uint32_t d32;
930 struct
931 {
932 unsigned out : 16; /*!< 31-16 OUT Endpoint bits */
933 unsigned in : 16; /*!< 15-00 IN Endpoint bits */
934 } eps;
935 struct
936 {
937 /** OUT Endpoint bits */
938 unsigned outep15 : 1;
939 unsigned outep14 : 1;
940 unsigned outep13 : 1;
941 unsigned outep12 : 1;
942 unsigned outep11 : 1;
943 unsigned outep10 : 1;
944 unsigned outep09 : 1;
945 unsigned outep08 : 1;
946 unsigned outep07 : 1;
947 unsigned outep06 : 1;
948 unsigned outep05 : 1;
949 unsigned outep04 : 1;
950 unsigned outep03 : 1;
951 unsigned outep02 : 1;
952 unsigned outep01 : 1;
953 unsigned outep00 : 1;
954 /** IN Endpoint bits */
955 unsigned inep15 : 1;
956 unsigned inep14 : 1;
957 unsigned inep13 : 1;
958 unsigned inep12 : 1;
959 unsigned inep11 : 1;
960 unsigned inep10 : 1;
961 unsigned inep09 : 1;
962 unsigned inep08 : 1;
963 unsigned inep07 : 1;
964 unsigned inep06 : 1;
965 unsigned inep05 : 1;
966 unsigned inep04 : 1;
967 unsigned inep03 : 1;
968 unsigned inep02 : 1;
969 unsigned inep01 : 1;
970 unsigned inep00 : 1;
971 } ep;
972 } daint_data_t;
973
974
975 /*!
976 \brief Bit fields in the Device IN Token Queue Read Registers.
977 */
978 typedef union dtknq1_data
979 {
980 uint32_t d32;
981 struct
982 {
983 unsigned epnums0_5 :24; /*!< 31-08 EP Numbers of IN Tokens 0 ... 4 */
984 unsigned wrap_bit : 1; /*!< 07 write pointer has wrapped */
985 unsigned reserved05_06 : 2;
986 unsigned intknwptr : 5; /*!< 04-00 In Token Queue Write Pointer */
987 }b;
988 } dtknq1_data_t;
989
990
991 /*!
992 \brief Bit fields in Threshold control Register
993 */
994 typedef union dthrctl_data
995 {
996 uint32_t d32;
997 struct
998 {
999 unsigned reserved26_31 : 6;
1000 unsigned rx_thr_len : 9; /*!< 25-17 Rx Thr. Length */
1001 unsigned rx_thr_en : 1; /*!< 16 Rx Thr. Enable */
1002 unsigned reserved11_15 : 5;
1003 unsigned tx_thr_len : 9; /*!< 10-02 Tx Thr. Length */
1004 unsigned iso_thr_en : 1; /*!< 01 ISO Tx Thr. Enable */
1005 unsigned non_iso_thr_en : 1; /*!< 00 non ISO Tx Thr. Enable */
1006 } b;
1007 } dthrctl_data_t;
1008
1009 /*@}*//*IFXUSB_CSR_DEVICE_GLOBAL_REG*/
1010
1011 /****************************************************************************/
1012
1013 /*!
1014 \addtogroup IFXUSB_CSR_DEVICE_EP_REG
1015 */
1016 /*@{*/
1017
1018 /*! typedef ifxusb_dev_in_ep_regs_t
1019 \brief Device Logical IN Endpoint-Specific Registers.
1020 There will be one set of endpoint registers per logical endpoint
1021 implemented.
1022 each EP's IN EP Register are offset at :
1023 900h + * (ep_num * 20h)
1024 */
1025
1026 typedef struct ifxusb_dev_in_ep_regs
1027 {
1028 volatile uint32_t diepctl; /*!< 00h: Endpoint Control Register */
1029 uint32_t reserved04; /*!< 04h: */
1030 volatile uint32_t diepint; /*!< 08h: Endpoint Interrupt Register */
1031 uint32_t reserved0C; /*!< 0Ch: */
1032 volatile uint32_t dieptsiz; /*!< 10h: Endpoint Transfer Size Register.*/
1033 volatile uint32_t diepdma; /*!< 14h: Endpoint DMA Address Register. */
1034 volatile uint32_t dtxfsts; /*!< 18h: Endpoint Transmit FIFO Status Register. */
1035 volatile uint32_t diepdmab; /*!< 1Ch: Endpoint DMA Buffer Register. */
1036 } ifxusb_dev_in_ep_regs_t;
1037
1038 /*! typedef ifxusb_dev_out_ep_regs_t
1039 \brief Device Logical OUT Endpoint-Specific Registers.
1040 There will be one set of endpoint registers per logical endpoint
1041 implemented.
1042 each EP's OUT EP Register are offset at :
1043 B00h + * (ep_num * 20h) + 00h
1044 */
1045 typedef struct ifxusb_dev_out_ep_regs
1046 {
1047 volatile uint32_t doepctl; /*!< 00h: Endpoint Control Register */
1048 volatile uint32_t doepfn; /*!< 04h: Endpoint Frame number Register */
1049 volatile uint32_t doepint; /*!< 08h: Endpoint Interrupt Register */
1050 uint32_t reserved0C; /*!< 0Ch: */
1051 volatile uint32_t doeptsiz; /*!< 10h: Endpoint Transfer Size Register.*/
1052 volatile uint32_t doepdma; /*!< 14h: Endpoint DMA Address Register. */
1053 uint32_t reserved18; /*!< 18h: */
1054 volatile uint32_t doepdmab; /*!< 1Ch: Endpoint DMA Buffer Register. */
1055 } ifxusb_dev_out_ep_regs_t;
1056
1057
1058 /*!
1059 \brief Bit fields in the Device EP Control
1060 Register.
1061 */
1062 typedef union depctl_data
1063 {
1064 uint32_t d32;
1065 struct
1066 {
1067 unsigned epena : 1; /*!< 31 Endpoint Enable */
1068 unsigned epdis : 1; /*!< 30 Endpoint Disable */
1069 unsigned setd1pid : 1; /*!< 29 Set DATA1 PID (INTR/Bulk IN and OUT endpoints) */
1070 unsigned setd0pid : 1; /*!< 28 Set DATA0 PID (INTR/Bulk IN and OUT endpoints) */
1071 unsigned snak : 1; /*!< 27 Set NAK */
1072 unsigned cnak : 1; /*!< 26 Clear NAK */
1073 unsigned txfnum : 4; /*!< 25-22 Tx Fifo Number */
1074 unsigned stall : 1; /*!< 21 Stall Handshake */
1075 unsigned snp : 1; /*!< 20 Snoop Mode */
1076 unsigned eptype : 2; /*!< 19-18 Endpoint Type
1077 0: Control
1078 1: Isochronous
1079 2: Bulk
1080 3: Interrupt
1081 */
1082 unsigned naksts : 1; /*!< 17 NAK Status */
1083 unsigned dpid : 1; /*!< 16 Endpoint DPID (INTR/Bulk IN and OUT endpoints) */
1084 unsigned usbactep : 1; /*!< 15 USB Active Endpoint */
1085 unsigned nextep : 4; /*!< 14-11 Next Endpoint */
1086 unsigned mps :11; /*!< 10-00 Maximum Packet Size */
1087 #define IFXUSB_DEP0CTL_MPS_64 0
1088 #define IFXUSB_DEP0CTL_MPS_32 1
1089 #define IFXUSB_DEP0CTL_MPS_16 2
1090 #define IFXUSB_DEP0CTL_MPS_8 3
1091 } b;
1092 } depctl_data_t;
1093
1094
1095 /*!
1096 \brief Bit fields in the Device EP Transfer Size Register. (EP0 and EPn)
1097 */
1098 typedef union deptsiz_data
1099 {
1100 uint32_t d32;
1101 struct
1102 {
1103 unsigned reserved31 : 1;
1104 unsigned supcnt : 2; /*!< 30-29 Setup Packet Count */
1105 #ifdef __DED_FIFO__
1106 unsigned reserved21_28 : 8;
1107 unsigned pktcnt : 2; /*!< 19-20 Packet Count */
1108 #else
1109 unsigned reserved20_28 : 9;
1110 unsigned pktcnt : 1; /*!< 19 Packet Count */
1111 #endif
1112 unsigned reserved7_18 :12;
1113 unsigned xfersize : 7; /*!< 06-00 Transfer size */
1114 }b0;
1115 struct
1116 {
1117 unsigned reserved : 1;
1118 unsigned mc : 2; /*!< 30-29 Multi Count */
1119 unsigned pktcnt :10; /*!< 28-19 Packet Count */
1120 unsigned xfersize :19; /*!< 18-00 Transfer size */
1121 } b;
1122 } deptsiz_data_t;
1123
1124 /*@}*//*IFXUSB_CSR_DEVICE_EP_REG*/
1125 /****************************************************************************/
1126
1127 /*!
1128 \addtogroup IFXUSB_CSR_DEVICE_DMA_DESC
1129 */
1130 /*@{*/
1131 /*!
1132 \brief Bit fields in the DMA Descriptor status quadlet.
1133 */
1134 typedef union desc_sts_data
1135 {
1136 struct
1137 {
1138 unsigned bs : 2; /*!< 31-30 Buffer Status */
1139 #define BS_HOST_READY 0x0
1140 #define BS_DMA_BUSY 0x1
1141 #define BS_DMA_DONE 0x2
1142 #define BS_HOST_BUSY 0x3
1143 unsigned sts : 2; /*!< 29-28 Receive/Trasmit Status */
1144 #define RTS_SUCCESS 0x0
1145 #define RTS_BUFFLUSH 0x1
1146 #define RTS_RESERVED 0x2
1147 #define RTS_BUFERR 0x3
1148 unsigned l : 1; /*!< 27 Last */
1149 unsigned sp : 1; /*!< 26 Short Packet */
1150 unsigned ioc : 1; /*!< 25 Interrupt On Complete */
1151 unsigned sr : 1; /*!< 24 Setup Packet received */
1152 unsigned mtrf : 1; /*!< 23 Multiple Transfer */
1153 unsigned reserved16_22 : 7;
1154 unsigned bytes :16; /*!< 15-00 Transfer size in bytes */
1155 } b;
1156 uint32_t d32; /*!< DMA Descriptor data buffer pointer */
1157 } desc_sts_data_t;
1158
1159 /*@}*//*IFXUSB_CSR_DEVICE_DMA_DESC*/
1160 /****************************************************************************/
1161
1162 /*!
1163 \addtogroup IFXUSB_CSR_HOST_GLOBAL_REG
1164 */
1165 /*@{*/
1166 /*! typedef ifxusb_host_global_regs_t
1167 \brief IFXUSB Host Mode Global registers. Offsets 400h-7FFh
1168 The ifxusb_host_global_regs structure defines the size
1169 and relative field offsets for the Host Global registers.
1170 These registers are visible only in Host mode and must not be
1171 accessed in Device mode, as the results are unknown.
1172 */
1173 typedef struct ifxusb_host_global_regs
1174 {
1175 volatile uint32_t hcfg; /*!< 400h Host Configuration Register. */
1176 volatile uint32_t hfir; /*!< 404h Host Frame Interval Register. */
1177 volatile uint32_t hfnum; /*!< 408h Host Frame Number / Frame Remaining Register. */
1178 uint32_t reserved40C;
1179 volatile uint32_t hptxsts; /*!< 410h Host Periodic Transmit FIFO/ Queue Status Register. */
1180 volatile uint32_t haint; /*!< 414h Host All Channels Interrupt Register. */
1181 volatile uint32_t haintmsk; /*!< 418h Host All Channels Interrupt Mask Register. */
1182 } ifxusb_host_global_regs_t;
1183
1184 /*!
1185 \brief Bit fields in the Host Configuration Register.
1186 */
1187 typedef union hcfg_data
1188 {
1189 uint32_t d32;
1190 struct
1191 {
1192 unsigned reserved31_03 :29;
1193 unsigned fslssupp : 1; /*!< 02 FS/LS Only Support */
1194 unsigned fslspclksel : 2; /*!< 01-00 FS/LS Phy Clock Select */
1195 #define IFXUSB_HCFG_30_60_MHZ 0
1196 #define IFXUSB_HCFG_48_MHZ 1
1197 #define IFXUSB_HCFG_6_MHZ 2
1198 } b;
1199 } hcfg_data_t;
1200
1201 /*!
1202 \brief Bit fields in the Host Frame Interval Register.
1203 */
1204 typedef union hfir_data
1205 {
1206 uint32_t d32;
1207 struct
1208 {
1209 unsigned reserved : 16;
1210 unsigned frint : 16; /*!< 15-00 Frame Interval */
1211 } b;
1212 } hfir_data_t;
1213
1214 /*!
1215 \brief Bit fields in the Host Frame Time Remaing/Number Register.
1216 */
1217 typedef union hfnum_data
1218 {
1219 uint32_t d32;
1220 struct
1221 {
1222 unsigned frrem : 16; /*!< 31-16 Frame Time Remaining */
1223 unsigned frnum : 16; /*!< 15-00 Frame Number*/
1224 #define IFXUSB_HFNUM_MAX_FRNUM 0x3FFF
1225 } b;
1226 } hfnum_data_t;
1227
1228 /*!
1229 \brief Bit fields in the Host Periodic Transmit FIFO/Queue Status Register
1230 */
1231 typedef union hptxsts_data
1232 {
1233 /** raw register data */
1234 uint32_t d32;
1235 struct
1236 {
1237 /** Top of the Periodic Transmit Request Queue
1238 * - bit 24 - Terminate (last entry for the selected channel)
1239 */
1240 unsigned ptxqtop_odd : 1; /*!< 31 Top of the Periodic Transmit Request
1241 Queue Odd/even microframe*/
1242 unsigned ptxqtop_chnum : 4; /*!< 30-27 Top of the Periodic Transmit Request
1243 Channel Number */
1244 unsigned ptxqtop_token : 2; /*!< 26-25 Top of the Periodic Transmit Request
1245 Token Type
1246 0 - Zero length
1247 1 - Ping
1248 2 - Disable
1249 */
1250 unsigned ptxqtop_terminate : 1; /*!< 24 Top of the Periodic Transmit Request
1251 Terminate (last entry for the selected channel)*/
1252 unsigned ptxqspcavail : 8; /*!< 23-16 Periodic Transmit Request Queue Space Available */
1253 unsigned ptxfspcavail :16; /*!< 15-00 Periodic Transmit Data FIFO Space Available */
1254 } b;
1255 } hptxsts_data_t;
1256
1257 /*!
1258 \brief Bit fields in the Host Port Control and Status Register.
1259 */
1260 typedef union hprt0_data
1261 {
1262 uint32_t d32;
1263 struct
1264 {
1265 unsigned reserved19_31 :13;
1266 unsigned prtspd : 2; /*!< 18-17 Port Speed */
1267 #define IFXUSB_HPRT0_PRTSPD_HIGH_SPEED 0
1268 #define IFXUSB_HPRT0_PRTSPD_FULL_SPEED 1
1269 #define IFXUSB_HPRT0_PRTSPD_LOW_SPEED 2
1270 unsigned prttstctl : 4; /*!< 16-13 Port Test Control */
1271 unsigned prtpwr : 1; /*!< 12 Port Power */
1272 unsigned prtlnsts : 2; /*!< 11-10 Port Line Status */
1273 unsigned reserved9 : 1;
1274 unsigned prtrst : 1; /*!< 08 Port Reset */
1275 unsigned prtsusp : 1; /*!< 07 Port Suspend */
1276 unsigned prtres : 1; /*!< 06 Port Resume */
1277 unsigned prtovrcurrchng : 1; /*!< 05 Port Overcurrent Change */
1278 unsigned prtovrcurract : 1; /*!< 04 Port Overcurrent Active */
1279 unsigned prtenchng : 1; /*!< 03 Port Enable/Disable Change */
1280 unsigned prtena : 1; /*!< 02 Port Enable */
1281 unsigned prtconndet : 1; /*!< 01 Port Connect Detected */
1282 unsigned prtconnsts : 1; /*!< 00 Port Connect Status */
1283 }b;
1284 } hprt0_data_t;
1285
1286 /*!
1287 \brief Bit fields in the Host All Interrupt Register.
1288 */
1289 typedef union haint_data
1290 {
1291 uint32_t d32;
1292 struct
1293 {
1294 unsigned reserved : 16;
1295 unsigned ch15 : 1;
1296 unsigned ch14 : 1;
1297 unsigned ch13 : 1;
1298 unsigned ch12 : 1;
1299 unsigned ch11 : 1;
1300 unsigned ch10 : 1;
1301 unsigned ch09 : 1;
1302 unsigned ch08 : 1;
1303 unsigned ch07 : 1;
1304 unsigned ch06 : 1;
1305 unsigned ch05 : 1;
1306 unsigned ch04 : 1;
1307 unsigned ch03 : 1;
1308 unsigned ch02 : 1;
1309 unsigned ch01 : 1;
1310 unsigned ch00 : 1;
1311 } b;
1312 struct
1313 {
1314 unsigned reserved : 16;
1315 unsigned chint : 16;
1316 } b2;
1317 } haint_data_t;
1318 /*@}*//*IFXUSB_CSR_HOST_GLOBAL_REG*/
1319 /****************************************************************************/
1320 /*!
1321 \addtogroup IFXUSB_CSR_HOST_HC_REG
1322 */
1323 /*@{*/
1324 /*! typedef ifxusb_hc_regs_t
1325 \brief Host Channel Specific Registers
1326 There will be one set of hc registers per host channelimplemented.
1327 each HC's Register are offset at :
1328 500h + * (hc_num * 20h)
1329 */
1330 typedef struct ifxusb_hc_regs
1331 {
1332 volatile uint32_t hcchar; /*!< 00h Host Channel Characteristic Register.*/
1333 volatile uint32_t hcsplt; /*!< 04h Host Channel Split Control Register.*/
1334 volatile uint32_t hcint; /*!< 08h Host Channel Interrupt Register. */
1335 volatile uint32_t hcintmsk; /*!< 0Ch Host Channel Interrupt Mask Register. */
1336 volatile uint32_t hctsiz; /*!< 10h Host Channel Transfer Size Register. */
1337 volatile uint32_t hcdma; /*!< 14h Host Channel DMA Address Register. */
1338 uint32_t reserved[2]; /*!< 18h Reserved. */
1339 } ifxusb_hc_regs_t;
1340
1341
1342 /*!
1343 \brief Bit fields in the Host Channel Characteristics Register.
1344 */
1345 typedef union hcchar_data
1346 {
1347 uint32_t d32;
1348 struct
1349 {
1350 unsigned chen : 1; /*!< 31 Channel enable */
1351 unsigned chdis : 1; /*!< 30 Channel disable */
1352 unsigned oddfrm : 1; /*!< 29 Frame to transmit periodic transaction */
1353 unsigned devaddr : 7; /*!< 28-22 Device address */
1354 unsigned multicnt : 2; /*!< 21-20 Packets per frame for periodic transfers */
1355 unsigned eptype : 2; /*!< 19-18 0: Control, 1: Isoc, 2: Bulk, 3: Intr */
1356 unsigned lspddev : 1; /*!< 17 0: Full/high speed device, 1: Low speed device */
1357 unsigned reserved : 1;
1358 unsigned epdir : 1; /*!< 15 0: OUT, 1: IN */
1359 unsigned epnum : 4; /*!< 14-11 Endpoint number */
1360 unsigned mps :11; /*!< 10-00 Maximum packet size in bytes */
1361 } b;
1362 } hcchar_data_t;
1363
1364 /*!
1365 \brief Bit fields in the Host Channel Split Control Register
1366 */
1367 typedef union hcsplt_data
1368 {
1369 uint32_t d32;
1370 struct
1371 {
1372 unsigned spltena : 1; /*!< 31 Split Enble */
1373 unsigned reserved :14;
1374 unsigned compsplt : 1; /*!< 16 Do Complete Split */
1375 unsigned xactpos : 2; /*!< 15-14 Transaction Position */
1376 #define IFXUSB_HCSPLIT_XACTPOS_MID 0
1377 #define IFXUSB_HCSPLIT_XACTPOS_END 1
1378 #define IFXUSB_HCSPLIT_XACTPOS_BEGIN 2
1379 #define IFXUSB_HCSPLIT_XACTPOS_ALL 3
1380 unsigned hubaddr : 7; /*!< 13-07 Hub Address */
1381 unsigned prtaddr : 7; /*!< 06-00 Port Address */
1382 } b;
1383 } hcsplt_data_t;
1384
1385 /*!
1386 \brief Bit fields in the Host Interrupt Register.
1387 */
1388 typedef union hcint_data
1389 {
1390 uint32_t d32;
1391 struct
1392 {
1393 unsigned reserved :21;
1394 unsigned datatglerr : 1; /*!< 10 Data Toggle Error */
1395 unsigned frmovrun : 1; /*!< 09 Frame Overrun */
1396 unsigned bblerr : 1; /*!< 08 Babble Error */
1397 unsigned xacterr : 1; /*!< 07 Transaction Err */
1398 unsigned nyet : 1; /*!< 06 NYET Response Received */
1399 unsigned ack : 1; /*!< 05 ACK Response Received */
1400 unsigned nak : 1; /*!< 04 NAK Response Received */
1401 unsigned stall : 1; /*!< 03 STALL Response Received */
1402 unsigned ahberr : 1; /*!< 02 AHB Error */
1403 unsigned chhltd : 1; /*!< 01 Channel Halted */
1404 unsigned xfercomp : 1; /*!< 00 Channel Halted */
1405 }b;
1406 } hcint_data_t;
1407
1408
1409 /*!
1410 \brief Bit fields in the Host Channel Transfer Size
1411 Register.
1412 */
1413 typedef union hctsiz_data
1414 {
1415 uint32_t d32;
1416 struct
1417 {
1418 /** */
1419 unsigned dopng : 1; /*!< 31 Do PING protocol when 1 */
1420 /**
1421 * Packet ID for next data packet
1422 * 0: DATA0
1423 * 1: DATA2
1424 * 2: DATA1
1425 * 3: MDATA (non-Control), SETUP (Control)
1426 */
1427 unsigned pid : 2; /*!< 30-29 Packet ID for next data packet
1428 0: DATA0
1429 1: DATA2
1430 2: DATA1
1431 3: MDATA (non-Control), SETUP (Control)
1432 */
1433 #define IFXUSB_HCTSIZ_DATA0 0
1434 #define IFXUSB_HCTSIZ_DATA1 2
1435 #define IFXUSB_HCTSIZ_DATA2 1
1436 #define IFXUSB_HCTSIZ_MDATA 3
1437 #define IFXUSB_HCTSIZ_SETUP 3
1438 unsigned pktcnt :10; /*!< 28-19 Data packets to transfer */
1439 unsigned xfersize :19; /*!< 18-00 Total transfer size in bytes */
1440 }b;
1441 } hctsiz_data_t;
1442
1443 /*@}*//*IFXUSB_CSR_HOST_HC_REG*/
1444
1445 /****************************************************************************/
1446
1447 /*!
1448 \addtogroup IFXUSB_CSR_PWR_CLK_GATING_REG
1449 */
1450 /*@{*/
1451 /*!
1452 \brief Bit fields in the Power and Clock Gating Control Register
1453 */
1454 typedef union pcgcctl_data
1455 {
1456 uint32_t d32;
1457 struct
1458 {
1459 unsigned reserved : 27;
1460 unsigned physuspended : 1; /*!< 04 PHY Suspended */
1461 unsigned rstpdwnmodule : 1; /*!< 03 Reset Power Down Modules */
1462 unsigned pwrclmp : 1; /*!< 02 Power Clamp */
1463 unsigned gatehclk : 1; /*!< 01 Gate Hclk */
1464 unsigned stoppclk : 1; /*!< 00 Stop Pclk */
1465 } b;
1466 } pcgcctl_data_t;
1467 /*@}*//*IFXUSB_CSR_PWR_CLK_GATING_REG*/
1468
1469 /****************************************************************************/
1470
1471 #endif //__IFXUSB_REGS_H__
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