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[openwrt/openwrt.git] / package / kernel / mac80211 / patches / rt2x00 / 010-v6.1-rt2x00-add-TX-LOFT-calibration-for-MT7620.patch
1 From patchwork Sat Sep 17 20:28:43 2022
2 Content-Type: text/plain; charset="utf-8"
3 MIME-Version: 1.0
4 Content-Transfer-Encoding: 8bit
5 X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
6 X-Patchwork-Id: 12979251
7 X-Patchwork-Delegate: kvalo@adurom.com
8 Return-Path: <linux-wireless-owner@kernel.org>
9 Date: Sat, 17 Sep 2022 21:28:43 +0100
10 From: Daniel Golle <daniel@makrotopia.org>
11 To: linux-wireless@vger.kernel.org, Stanislaw Gruszka <stf_xl@wp.pl>,
12 Helmut Schaa <helmut.schaa@googlemail.com>
13 Cc: Kalle Valo <kvalo@kernel.org>,
14 "David S. Miller" <davem@davemloft.net>,
15 Eric Dumazet <edumazet@google.com>,
16 Jakub Kicinski <kuba@kernel.org>,
17 Paolo Abeni <pabeni@redhat.com>,
18 Johannes Berg <johannes.berg@intel.com>
19 Subject: [PATCH v3 10/16] rt2x00: add TX LOFT calibration for MT7620
20 Message-ID:
21 <d9295a9138a1f552b648aacb84e1419d38f5c896.1663445157.git.daniel@makrotopia.org>
22 References: <cover.1663445157.git.daniel@makrotopia.org>
23 MIME-Version: 1.0
24 Content-Disposition: inline
25 In-Reply-To: <cover.1663445157.git.daniel@makrotopia.org>
26 Precedence: bulk
27 List-ID: <linux-wireless.vger.kernel.org>
28 X-Mailing-List: linux-wireless@vger.kernel.org
29
30 From: Tomislav Požega <pozega.tomislav@gmail.com>
31
32 Add TX LOFT calibration from mtk driver.
33
34 Signed-off-by: Tomislav Požega <pozega.tomislav@gmail.com>
35 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
36 ---
37 v2: use helper functions, make tables static const, remove useless
38 debug prints
39 v3: don't export function not used anywhere else
40 Reported-by: kernel test robot <lkp@intel.com>
41
42 .../net/wireless/ralink/rt2x00/rt2800lib.c | 902 ++++++++++++++++++
43 .../net/wireless/ralink/rt2x00/rt2800lib.h | 10 +
44 2 files changed, 912 insertions(+)
45
46 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
47 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
48 @@ -9066,6 +9066,907 @@ restore_value:
49 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
50 }
51
52 +static void rt2800_rf_configstore(struct rt2x00_dev *rt2x00dev,
53 + struct rf_reg_pair rf_reg_record[][13], u8 chain)
54 +{
55 + u8 rfvalue = 0;
56 +
57 + if (chain == CHAIN_0) {
58 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
59 + rf_reg_record[CHAIN_0][0].bank = 0;
60 + rf_reg_record[CHAIN_0][0].reg = 1;
61 + rf_reg_record[CHAIN_0][0].value = rfvalue;
62 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
63 + rf_reg_record[CHAIN_0][1].bank = 0;
64 + rf_reg_record[CHAIN_0][1].reg = 2;
65 + rf_reg_record[CHAIN_0][1].value = rfvalue;
66 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);
67 + rf_reg_record[CHAIN_0][2].bank = 0;
68 + rf_reg_record[CHAIN_0][2].reg = 35;
69 + rf_reg_record[CHAIN_0][2].value = rfvalue;
70 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
71 + rf_reg_record[CHAIN_0][3].bank = 0;
72 + rf_reg_record[CHAIN_0][3].reg = 42;
73 + rf_reg_record[CHAIN_0][3].value = rfvalue;
74 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 0);
75 + rf_reg_record[CHAIN_0][4].bank = 4;
76 + rf_reg_record[CHAIN_0][4].reg = 0;
77 + rf_reg_record[CHAIN_0][4].value = rfvalue;
78 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 2);
79 + rf_reg_record[CHAIN_0][5].bank = 4;
80 + rf_reg_record[CHAIN_0][5].reg = 2;
81 + rf_reg_record[CHAIN_0][5].value = rfvalue;
82 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 4, 34);
83 + rf_reg_record[CHAIN_0][6].bank = 4;
84 + rf_reg_record[CHAIN_0][6].reg = 34;
85 + rf_reg_record[CHAIN_0][6].value = rfvalue;
86 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
87 + rf_reg_record[CHAIN_0][7].bank = 5;
88 + rf_reg_record[CHAIN_0][7].reg = 3;
89 + rf_reg_record[CHAIN_0][7].value = rfvalue;
90 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
91 + rf_reg_record[CHAIN_0][8].bank = 5;
92 + rf_reg_record[CHAIN_0][8].reg = 4;
93 + rf_reg_record[CHAIN_0][8].value = rfvalue;
94 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
95 + rf_reg_record[CHAIN_0][9].bank = 5;
96 + rf_reg_record[CHAIN_0][9].reg = 17;
97 + rf_reg_record[CHAIN_0][9].value = rfvalue;
98 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
99 + rf_reg_record[CHAIN_0][10].bank = 5;
100 + rf_reg_record[CHAIN_0][10].reg = 18;
101 + rf_reg_record[CHAIN_0][10].value = rfvalue;
102 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
103 + rf_reg_record[CHAIN_0][11].bank = 5;
104 + rf_reg_record[CHAIN_0][11].reg = 19;
105 + rf_reg_record[CHAIN_0][11].value = rfvalue;
106 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
107 + rf_reg_record[CHAIN_0][12].bank = 5;
108 + rf_reg_record[CHAIN_0][12].reg = 20;
109 + rf_reg_record[CHAIN_0][12].value = rfvalue;
110 + } else if (chain == CHAIN_1) {
111 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
112 + rf_reg_record[CHAIN_1][0].bank = 0;
113 + rf_reg_record[CHAIN_1][0].reg = 1;
114 + rf_reg_record[CHAIN_1][0].value = rfvalue;
115 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 2);
116 + rf_reg_record[CHAIN_1][1].bank = 0;
117 + rf_reg_record[CHAIN_1][1].reg = 2;
118 + rf_reg_record[CHAIN_1][1].value = rfvalue;
119 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);
120 + rf_reg_record[CHAIN_1][2].bank = 0;
121 + rf_reg_record[CHAIN_1][2].reg = 35;
122 + rf_reg_record[CHAIN_1][2].value = rfvalue;
123 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
124 + rf_reg_record[CHAIN_1][3].bank = 0;
125 + rf_reg_record[CHAIN_1][3].reg = 42;
126 + rf_reg_record[CHAIN_1][3].value = rfvalue;
127 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 0);
128 + rf_reg_record[CHAIN_1][4].bank = 6;
129 + rf_reg_record[CHAIN_1][4].reg = 0;
130 + rf_reg_record[CHAIN_1][4].value = rfvalue;
131 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 2);
132 + rf_reg_record[CHAIN_1][5].bank = 6;
133 + rf_reg_record[CHAIN_1][5].reg = 2;
134 + rf_reg_record[CHAIN_1][5].value = rfvalue;
135 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 6, 34);
136 + rf_reg_record[CHAIN_1][6].bank = 6;
137 + rf_reg_record[CHAIN_1][6].reg = 34;
138 + rf_reg_record[CHAIN_1][6].value = rfvalue;
139 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 3);
140 + rf_reg_record[CHAIN_1][7].bank = 7;
141 + rf_reg_record[CHAIN_1][7].reg = 3;
142 + rf_reg_record[CHAIN_1][7].value = rfvalue;
143 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 4);
144 + rf_reg_record[CHAIN_1][8].bank = 7;
145 + rf_reg_record[CHAIN_1][8].reg = 4;
146 + rf_reg_record[CHAIN_1][8].value = rfvalue;
147 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 17);
148 + rf_reg_record[CHAIN_1][9].bank = 7;
149 + rf_reg_record[CHAIN_1][9].reg = 17;
150 + rf_reg_record[CHAIN_1][9].value = rfvalue;
151 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 18);
152 + rf_reg_record[CHAIN_1][10].bank = 7;
153 + rf_reg_record[CHAIN_1][10].reg = 18;
154 + rf_reg_record[CHAIN_1][10].value = rfvalue;
155 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 19);
156 + rf_reg_record[CHAIN_1][11].bank = 7;
157 + rf_reg_record[CHAIN_1][11].reg = 19;
158 + rf_reg_record[CHAIN_1][11].value = rfvalue;
159 + rfvalue = rt2800_rfcsr_read_bank(rt2x00dev, 7, 20);
160 + rf_reg_record[CHAIN_1][12].bank = 7;
161 + rf_reg_record[CHAIN_1][12].reg = 20;
162 + rf_reg_record[CHAIN_1][12].value = rfvalue;
163 + } else {
164 + rt2x00_warn(rt2x00dev, "Unknown chain = %u\n", chain);
165 + }
166 +}
167 +
168 +static void rt2800_rf_configrecover(struct rt2x00_dev *rt2x00dev,
169 + struct rf_reg_pair rf_record[][13])
170 +{
171 + u8 chain_index = 0, record_index = 0;
172 + u8 bank = 0, rf_register = 0, value = 0;
173 +
174 + for (chain_index = 0; chain_index < 2; chain_index++) {
175 + for (record_index = 0; record_index < 13; record_index++) {
176 + bank = rf_record[chain_index][record_index].bank;
177 + rf_register = rf_record[chain_index][record_index].reg;
178 + value = rf_record[chain_index][record_index].value;
179 + rt2800_rfcsr_write_bank(rt2x00dev, bank, rf_register, value);
180 + rt2x00_dbg(rt2x00dev, "bank: %d, rf_register: %d, value: %x\n",
181 + bank, rf_register, value);
182 + }
183 + }
184 +}
185 +
186 +static void rt2800_setbbptonegenerator(struct rt2x00_dev *rt2x00dev)
187 +{
188 + rt2800_bbp_write(rt2x00dev, 158, 0xAA);
189 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
190 +
191 + rt2800_bbp_write(rt2x00dev, 158, 0xAB);
192 + rt2800_bbp_write(rt2x00dev, 159, 0x0A);
193 +
194 + rt2800_bbp_write(rt2x00dev, 158, 0xAC);
195 + rt2800_bbp_write(rt2x00dev, 159, 0x3F);
196 +
197 + rt2800_bbp_write(rt2x00dev, 158, 0xAD);
198 + rt2800_bbp_write(rt2x00dev, 159, 0x3F);
199 +
200 + rt2800_bbp_write(rt2x00dev, 244, 0x40);
201 +}
202 +
203 +static u32 rt2800_do_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx, u8 read_neg)
204 +{
205 + u32 macvalue = 0;
206 + int fftout_i = 0, fftout_q = 0;
207 + u32 ptmp = 0, pint = 0;
208 + u8 bbp = 0;
209 + u8 tidxi;
210 +
211 + rt2800_bbp_write(rt2x00dev, 158, 0x00);
212 + rt2800_bbp_write(rt2x00dev, 159, 0x9b);
213 +
214 + bbp = 0x9b;
215 +
216 + while (bbp == 0x9b) {
217 + usleep_range(10, 50);
218 + bbp = rt2800_bbp_read(rt2x00dev, 159);
219 + bbp = bbp & 0xff;
220 + }
221 +
222 + rt2800_bbp_write(rt2x00dev, 158, 0xba);
223 + rt2800_bbp_write(rt2x00dev, 159, tidx);
224 + rt2800_bbp_write(rt2x00dev, 159, tidx);
225 + rt2800_bbp_write(rt2x00dev, 159, tidx);
226 +
227 + macvalue = rt2800_register_read(rt2x00dev, 0x057C);
228 +
229 + fftout_i = (macvalue >> 16);
230 + fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;
231 + fftout_q = (macvalue & 0xffff);
232 + fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;
233 + ptmp = (fftout_i * fftout_i);
234 + ptmp = ptmp + (fftout_q * fftout_q);
235 + pint = ptmp;
236 + rt2x00_dbg(rt2x00dev, "I = %d, Q = %d, power = %x\n", fftout_i, fftout_q, pint);
237 + if (read_neg) {
238 + pint = pint >> 1;
239 + tidxi = 0x40 - tidx;
240 + tidxi = tidxi & 0x3f;
241 +
242 + rt2800_bbp_write(rt2x00dev, 158, 0xba);
243 + rt2800_bbp_write(rt2x00dev, 159, tidxi);
244 + rt2800_bbp_write(rt2x00dev, 159, tidxi);
245 + rt2800_bbp_write(rt2x00dev, 159, tidxi);
246 +
247 + macvalue = rt2800_register_read(rt2x00dev, 0x057C);
248 +
249 + fftout_i = (macvalue >> 16);
250 + fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;
251 + fftout_q = (macvalue & 0xffff);
252 + fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;
253 + ptmp = (fftout_i * fftout_i);
254 + ptmp = ptmp + (fftout_q * fftout_q);
255 + ptmp = ptmp >> 1;
256 + pint = pint + ptmp;
257 + }
258 +
259 + return pint;
260 +}
261 +
262 +static u32 rt2800_read_fft_accumulation(struct rt2x00_dev *rt2x00dev, u8 tidx)
263 +{
264 + u32 macvalue = 0;
265 + int fftout_i = 0, fftout_q = 0;
266 + u32 ptmp = 0, pint = 0;
267 +
268 + rt2800_bbp_write(rt2x00dev, 158, 0xBA);
269 + rt2800_bbp_write(rt2x00dev, 159, tidx);
270 + rt2800_bbp_write(rt2x00dev, 159, tidx);
271 + rt2800_bbp_write(rt2x00dev, 159, tidx);
272 +
273 + macvalue = rt2800_register_read(rt2x00dev, 0x057C);
274 +
275 + fftout_i = (macvalue >> 16);
276 + fftout_i = (fftout_i & 0x8000) ? (fftout_i - 0x10000) : fftout_i;
277 + fftout_q = (macvalue & 0xffff);
278 + fftout_q = (fftout_q & 0x8000) ? (fftout_q - 0x10000) : fftout_q;
279 + ptmp = (fftout_i * fftout_i);
280 + ptmp = ptmp + (fftout_q * fftout_q);
281 + pint = ptmp;
282 +
283 + return pint;
284 +}
285 +
286 +static void rt2800_write_dc(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 alc, u8 iorq, u8 dc)
287 +{
288 + u8 bbp = 0;
289 +
290 + rt2800_bbp_write(rt2x00dev, 158, 0xb0);
291 + bbp = alc | 0x80;
292 + rt2800_bbp_write(rt2x00dev, 159, bbp);
293 +
294 + if (ch_idx == 0)
295 + bbp = (iorq == 0) ? 0xb1 : 0xb2;
296 + else
297 + bbp = (iorq == 0) ? 0xb8 : 0xb9;
298 +
299 + rt2800_bbp_write(rt2x00dev, 158, bbp);
300 + bbp = dc;
301 + rt2800_bbp_write(rt2x00dev, 159, bbp);
302 +}
303 +
304 +static void rt2800_loft_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx,
305 + u8 alc_idx, u8 dc_result[][RF_ALC_NUM][2])
306 +{
307 + u32 p0 = 0, p1 = 0, pf = 0;
308 + char idx0 = 0, idx1 = 0;
309 + u8 idxf[] = {0x00, 0x00};
310 + u8 ibit = 0x20;
311 + u8 iorq;
312 + char bidx;
313 +
314 + rt2800_bbp_write(rt2x00dev, 158, 0xb0);
315 + rt2800_bbp_write(rt2x00dev, 159, 0x80);
316 +
317 + for (bidx = 5; bidx >= 0; bidx--) {
318 + for (iorq = 0; iorq <= 1; iorq++) {
319 + if (idxf[iorq] == 0x20) {
320 + idx0 = 0x20;
321 + p0 = pf;
322 + } else {
323 + idx0 = idxf[iorq] - ibit;
324 + idx0 = idx0 & 0x3F;
325 + rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx0);
326 + p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
327 + }
328 +
329 + idx1 = idxf[iorq] + (bidx == 5 ? 0 : ibit);
330 + idx1 = idx1 & 0x3F;
331 + rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idx1);
332 + p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
333 +
334 + rt2x00_dbg(rt2x00dev, "alc=%u, IorQ=%u, idx_final=%2x\n",
335 + alc_idx, iorq, idxf[iorq]);
336 + rt2x00_dbg(rt2x00dev, "p0=%x, p1=%x, pf=%x, idx_0=%x, idx_1=%x, ibit=%x\n",
337 + p0, p1, pf, idx0, idx1, ibit);
338 +
339 + if (bidx != 5 && pf <= p0 && pf < p1) {
340 + idxf[iorq] = idxf[iorq];
341 + } else if (p0 < p1) {
342 + pf = p0;
343 + idxf[iorq] = idx0 & 0x3F;
344 + } else {
345 + pf = p1;
346 + idxf[iorq] = idx1 & 0x3F;
347 + }
348 + rt2x00_dbg(rt2x00dev, "IorQ=%u, idx_final[%u]:%x, pf:%8x\n",
349 + iorq, iorq, idxf[iorq], pf);
350 +
351 + rt2800_write_dc(rt2x00dev, ch_idx, 0, iorq, idxf[iorq]);
352 + }
353 + ibit = ibit >> 1;
354 + }
355 + dc_result[ch_idx][alc_idx][0] = idxf[0];
356 + dc_result[ch_idx][alc_idx][1] = idxf[1];
357 +}
358 +
359 +static void rt2800_iq_search(struct rt2x00_dev *rt2x00dev, u8 ch_idx, u8 *ges, u8 *pes)
360 +{
361 + u32 p0 = 0, p1 = 0, pf = 0;
362 + char perr = 0, gerr = 0, iq_err = 0;
363 + char pef = 0, gef = 0;
364 + char psta, pend;
365 + char gsta, gend;
366 +
367 + u8 ibit = 0x20;
368 + u8 first_search = 0x00, touch_neg_max = 0x00;
369 + char idx0 = 0, idx1 = 0;
370 + u8 gop;
371 + u8 bbp = 0;
372 + char bidx;
373 +
374 + for (bidx = 5; bidx >= 1; bidx--) {
375 + for (gop = 0; gop < 2; gop++) {
376 + if (gop == 1 || bidx < 4) {
377 + if (gop == 0)
378 + iq_err = gerr;
379 + else
380 + iq_err = perr;
381 +
382 + first_search = (gop == 0) ? (bidx == 3) : (bidx == 5);
383 + touch_neg_max = (gop) ? ((iq_err & 0x0F) == 0x08) :
384 + ((iq_err & 0x3F) == 0x20);
385 +
386 + if (touch_neg_max) {
387 + p0 = pf;
388 + idx0 = iq_err;
389 + } else {
390 + idx0 = iq_err - ibit;
391 + bbp = (ch_idx == 0) ? ((gop == 0) ? 0x28 : 0x29) :
392 + ((gop == 0) ? 0x46 : 0x47);
393 +
394 + rt2800_bbp_write(rt2x00dev, 158, bbp);
395 + rt2800_bbp_write(rt2x00dev, 159, idx0);
396 +
397 + p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
398 + }
399 +
400 + idx1 = iq_err + (first_search ? 0 : ibit);
401 + idx1 = (gop == 0) ? (idx1 & 0x0F) : (idx1 & 0x3F);
402 +
403 + bbp = (ch_idx == 0) ? (gop == 0) ? 0x28 : 0x29 :
404 + (gop == 0) ? 0x46 : 0x47;
405 +
406 + rt2800_bbp_write(rt2x00dev, 158, bbp);
407 + rt2800_bbp_write(rt2x00dev, 159, idx1);
408 +
409 + p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
410 +
411 + rt2x00_dbg(rt2x00dev,
412 + "p0=%x, p1=%x, pwer_final=%x, idx0=%x, idx1=%x, iq_err=%x, gop=%d, ibit=%x\n",
413 + p0, p1, pf, idx0, idx1, iq_err, gop, ibit);
414 +
415 + if (!(!first_search && pf <= p0 && pf < p1)) {
416 + if (p0 < p1) {
417 + pf = p0;
418 + iq_err = idx0;
419 + } else {
420 + pf = p1;
421 + iq_err = idx1;
422 + }
423 + }
424 +
425 + bbp = (ch_idx == 0) ? (gop == 0) ? 0x28 : 0x29 :
426 + (gop == 0) ? 0x46 : 0x47;
427 +
428 + rt2800_bbp_write(rt2x00dev, 158, bbp);
429 + rt2800_bbp_write(rt2x00dev, 159, iq_err);
430 +
431 + if (gop == 0)
432 + gerr = iq_err;
433 + else
434 + perr = iq_err;
435 +
436 + rt2x00_dbg(rt2x00dev, "IQCalibration pf=%8x (%2x, %2x) !\n",
437 + pf, gerr & 0x0F, perr & 0x3F);
438 + }
439 + }
440 +
441 + if (bidx > 0)
442 + ibit = (ibit >> 1);
443 + }
444 + gerr = (gerr & 0x08) ? (gerr & 0x0F) - 0x10 : (gerr & 0x0F);
445 + perr = (perr & 0x20) ? (perr & 0x3F) - 0x40 : (perr & 0x3F);
446 +
447 + gerr = (gerr < -0x07) ? -0x07 : (gerr > 0x05) ? 0x05 : gerr;
448 + gsta = gerr - 1;
449 + gend = gerr + 2;
450 +
451 + perr = (perr < -0x1f) ? -0x1f : (perr > 0x1d) ? 0x1d : perr;
452 + psta = perr - 1;
453 + pend = perr + 2;
454 +
455 + for (gef = gsta; gef <= gend; gef = gef + 1)
456 + for (pef = psta; pef <= pend; pef = pef + 1) {
457 + bbp = (ch_idx == 0) ? 0x28 : 0x46;
458 + rt2800_bbp_write(rt2x00dev, 158, bbp);
459 + rt2800_bbp_write(rt2x00dev, 159, gef & 0x0F);
460 +
461 + bbp = (ch_idx == 0) ? 0x29 : 0x47;
462 + rt2800_bbp_write(rt2x00dev, 158, bbp);
463 + rt2800_bbp_write(rt2x00dev, 159, pef & 0x3F);
464 +
465 + p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 1);
466 + if (gef == gsta && pef == psta) {
467 + pf = p1;
468 + gerr = gef;
469 + perr = pef;
470 + } else if (pf > p1) {
471 + pf = p1;
472 + gerr = gef;
473 + perr = pef;
474 + }
475 + rt2x00_dbg(rt2x00dev, "Fine IQCalibration p1=%8x pf=%8x (%2x, %2x) !\n",
476 + p1, pf, gef & 0x0F, pef & 0x3F);
477 + }
478 +
479 + ges[ch_idx] = gerr & 0x0F;
480 + pes[ch_idx] = perr & 0x3F;
481 +}
482 +
483 +static void rt2800_rf_aux_tx0_loopback(struct rt2x00_dev *rt2x00dev)
484 +{
485 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x21);
486 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, 0x10);
487 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);
488 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x1b);
489 + rt2800_rfcsr_write_bank(rt2x00dev, 4, 0, 0x81);
490 + rt2800_rfcsr_write_bank(rt2x00dev, 4, 2, 0x81);
491 + rt2800_rfcsr_write_bank(rt2x00dev, 4, 34, 0xee);
492 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, 0x2d);
493 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, 0x2d);
494 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, 0x80);
495 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xd7);
496 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0xa2);
497 + rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x20);
498 +}
499 +
500 +static void rt2800_rf_aux_tx1_loopback(struct rt2x00_dev *rt2x00dev)
501 +{
502 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x22);
503 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 2, 0x20);
504 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);
505 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x4b);
506 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 0, 0x81);
507 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 2, 0x81);
508 + rt2800_rfcsr_write_bank(rt2x00dev, 6, 34, 0xee);
509 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 3, 0x2d);
510 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 4, 0x2d);
511 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 17, 0x80);
512 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 18, 0xd7);
513 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 19, 0xa2);
514 + rt2800_rfcsr_write_bank(rt2x00dev, 7, 20, 0x20);
515 +}
516 +
517 +static void rt2800_loft_iq_calibration(struct rt2x00_dev *rt2x00dev)
518 +{
519 + struct rf_reg_pair rf_store[CHAIN_NUM][13];
520 + u32 macorg1 = 0;
521 + u32 macorg2 = 0;
522 + u32 macorg3 = 0;
523 + u32 macorg4 = 0;
524 + u32 macorg5 = 0;
525 + u32 orig528 = 0;
526 + u32 orig52c = 0;
527 +
528 + u32 savemacsysctrl = 0;
529 + u32 macvalue = 0;
530 + u32 mac13b8 = 0;
531 + u32 p0 = 0, p1 = 0;
532 + u32 p0_idx10 = 0, p1_idx10 = 0;
533 +
534 + u8 rfvalue;
535 + u8 loft_dc_search_result[CHAIN_NUM][RF_ALC_NUM][2];
536 + u8 ger[CHAIN_NUM], per[CHAIN_NUM];
537 +
538 + u8 vga_gain[] = {14, 14};
539 + u8 bbp = 0, ch_idx = 0, rf_alc_idx = 0, idx = 0;
540 + u8 bbpr30, rfb0r39, rfb0r42;
541 + u8 bbpr1;
542 + u8 bbpr4;
543 + u8 bbpr241, bbpr242;
544 + u8 count_step;
545 +
546 + static const u8 rf_gain[] = {0x00, 0x01, 0x02, 0x04, 0x08, 0x0c};
547 + static const u8 rfvga_gain_table[] = {0x24, 0x25, 0x26, 0x27, 0x28, 0x2c, 0x2d, 0x2e, 0x2f, 0x30,
548 + 0x31, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3F};
549 + static const u8 bbp_2324gain[] = {0x16, 0x14, 0x12, 0x10, 0x0c, 0x08};
550 +
551 + savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
552 + macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
553 + macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
554 + macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
555 + macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
556 + macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
557 + mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8);
558 + orig528 = rt2800_register_read(rt2x00dev, RF_CONTROL2);
559 + orig52c = rt2800_register_read(rt2x00dev, RF_BYPASS2);
560 +
561 + macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
562 + macvalue &= (~0x04);
563 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
564 +
565 + if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))
566 + rt2x00_warn(rt2x00dev, "RF TX busy in LOFT IQ calibration\n");
567 +
568 + macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
569 + macvalue &= (~0x08);
570 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
571 +
572 + if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX)))
573 + rt2x00_warn(rt2x00dev, "RF RX busy in LOFT IQ calibration\n");
574 +
575 + for (ch_idx = 0; ch_idx < 2; ch_idx++)
576 + rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx);
577 +
578 + bbpr30 = rt2800_bbp_read(rt2x00dev, 30);
579 + rfb0r39 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 39);
580 + rfb0r42 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 42);
581 +
582 + rt2800_bbp_write(rt2x00dev, 30, 0x1F);
583 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, 0x80);
584 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, 0x5B);
585 +
586 + rt2800_bbp_write(rt2x00dev, 23, 0x00);
587 + rt2800_bbp_write(rt2x00dev, 24, 0x00);
588 +
589 + rt2800_setbbptonegenerator(rt2x00dev);
590 +
591 + for (ch_idx = 0; ch_idx < 2; ch_idx++) {
592 + rt2800_bbp_write(rt2x00dev, 23, 0x00);
593 + rt2800_bbp_write(rt2x00dev, 24, 0x00);
594 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00);
595 + rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F);
596 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
597 + rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306);
598 + rt2800_register_write(rt2x00dev, 0x13b8, 0x10);
599 + udelay(1);
600 +
601 + if (ch_idx == 0)
602 + rt2800_rf_aux_tx0_loopback(rt2x00dev);
603 + else
604 + rt2800_rf_aux_tx1_loopback(rt2x00dev);
605 +
606 + udelay(1);
607 +
608 + if (ch_idx == 0)
609 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004);
610 + else
611 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004);
612 +
613 + rt2800_bbp_write(rt2x00dev, 158, 0x05);
614 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
615 +
616 + rt2800_bbp_write(rt2x00dev, 158, 0x01);
617 + if (ch_idx == 0)
618 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
619 + else
620 + rt2800_bbp_write(rt2x00dev, 159, 0x01);
621 +
622 + vga_gain[ch_idx] = 18;
623 + for (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) {
624 + rt2800_bbp_write(rt2x00dev, 23, bbp_2324gain[rf_alc_idx]);
625 + rt2800_bbp_write(rt2x00dev, 24, bbp_2324gain[rf_alc_idx]);
626 +
627 + macvalue = rt2800_register_read(rt2x00dev, RF_CONTROL3);
628 + macvalue &= (~0x0000F1F1);
629 + macvalue |= (rf_gain[rf_alc_idx] << 4);
630 + macvalue |= (rf_gain[rf_alc_idx] << 12);
631 + rt2800_register_write(rt2x00dev, RF_CONTROL3, macvalue);
632 + macvalue = (0x0000F1F1);
633 + rt2800_register_write(rt2x00dev, RF_BYPASS3, macvalue);
634 +
635 + if (rf_alc_idx == 0) {
636 + rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x21);
637 + for (; vga_gain[ch_idx] > 0;
638 + vga_gain[ch_idx] = vga_gain[ch_idx] - 2) {
639 + rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
640 + rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
641 + rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
642 + rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00);
643 + rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00);
644 + p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
645 + rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x21);
646 + p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x0A, 0);
647 + rt2x00_dbg(rt2x00dev, "LOFT AGC %d %d\n", p0, p1);
648 + if ((p0 < 7000 * 7000) && (p1 < (7000 * 7000)))
649 + break;
650 + }
651 +
652 + rt2800_write_dc(rt2x00dev, ch_idx, 0, 0, 0x00);
653 + rt2800_write_dc(rt2x00dev, ch_idx, 0, 1, 0x00);
654 +
655 + rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n", vga_gain[ch_idx],
656 + rfvga_gain_table[vga_gain[ch_idx]]);
657 +
658 + if (vga_gain[ch_idx] < 0)
659 + vga_gain[ch_idx] = 0;
660 + }
661 +
662 + rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
663 +
664 + rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
665 + rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
666 +
667 + rt2800_loft_search(rt2x00dev, ch_idx, rf_alc_idx, loft_dc_search_result);
668 + }
669 + }
670 +
671 + for (rf_alc_idx = 0; rf_alc_idx < 3; rf_alc_idx++) {
672 + for (idx = 0; idx < 4; idx++) {
673 + rt2800_bbp_write(rt2x00dev, 158, 0xB0);
674 + bbp = (idx << 2) + rf_alc_idx;
675 + rt2800_bbp_write(rt2x00dev, 159, bbp);
676 + rt2x00_dbg(rt2x00dev, " ALC %2x,", bbp);
677 +
678 + rt2800_bbp_write(rt2x00dev, 158, 0xb1);
679 + bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x00];
680 + bbp = bbp & 0x3F;
681 + rt2800_bbp_write(rt2x00dev, 159, bbp);
682 + rt2x00_dbg(rt2x00dev, " I0 %2x,", bbp);
683 +
684 + rt2800_bbp_write(rt2x00dev, 158, 0xb2);
685 + bbp = loft_dc_search_result[CHAIN_0][rf_alc_idx][0x01];
686 + bbp = bbp & 0x3F;
687 + rt2800_bbp_write(rt2x00dev, 159, bbp);
688 + rt2x00_dbg(rt2x00dev, " Q0 %2x,", bbp);
689 +
690 + rt2800_bbp_write(rt2x00dev, 158, 0xb8);
691 + bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x00];
692 + bbp = bbp & 0x3F;
693 + rt2800_bbp_write(rt2x00dev, 159, bbp);
694 + rt2x00_dbg(rt2x00dev, " I1 %2x,", bbp);
695 +
696 + rt2800_bbp_write(rt2x00dev, 158, 0xb9);
697 + bbp = loft_dc_search_result[CHAIN_1][rf_alc_idx][0x01];
698 + bbp = bbp & 0x3F;
699 + rt2800_bbp_write(rt2x00dev, 159, bbp);
700 + rt2x00_dbg(rt2x00dev, " Q1 %2x\n", bbp);
701 + }
702 + }
703 +
704 + rt2800_bbp_write(rt2x00dev, 23, 0x00);
705 + rt2800_bbp_write(rt2x00dev, 24, 0x00);
706 +
707 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
708 +
709 + rt2800_bbp_write(rt2x00dev, 158, 0x00);
710 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
711 +
712 + bbp = 0x00;
713 + rt2800_bbp_write(rt2x00dev, 244, 0x00);
714 +
715 + rt2800_bbp_write(rt2x00dev, 21, 0x01);
716 + udelay(1);
717 + rt2800_bbp_write(rt2x00dev, 21, 0x00);
718 +
719 + rt2800_rf_configrecover(rt2x00dev, rf_store);
720 +
721 + rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1);
722 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
723 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00);
724 + rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00);
725 + rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2);
726 + udelay(1);
727 + rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3);
728 + rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4);
729 + rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5);
730 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
731 + rt2800_register_write(rt2x00dev, RF_CONTROL2, orig528);
732 + rt2800_register_write(rt2x00dev, RF_BYPASS2, orig52c);
733 + rt2800_register_write(rt2x00dev, 0x13b8, mac13b8);
734 +
735 + savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
736 + macorg1 = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
737 + macorg2 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
738 + macorg3 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
739 + macorg4 = rt2800_register_read(rt2x00dev, RF_CONTROL3);
740 + macorg5 = rt2800_register_read(rt2x00dev, RF_BYPASS3);
741 +
742 + bbpr1 = rt2800_bbp_read(rt2x00dev, 1);
743 + bbpr4 = rt2800_bbp_read(rt2x00dev, 4);
744 + bbpr241 = rt2800_bbp_read(rt2x00dev, 241);
745 + bbpr242 = rt2800_bbp_read(rt2x00dev, 242);
746 + mac13b8 = rt2800_register_read(rt2x00dev, 0x13b8);
747 +
748 + macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
749 + macvalue &= (~0x04);
750 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
751 +
752 + if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_TX)))
753 + rt2x00_warn(rt2x00dev, "RF TX busy in LOFT IQ calibration\n");
754 +
755 + macvalue = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
756 + macvalue &= (~0x08);
757 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, macvalue);
758 +
759 + if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev, MAC_STATUS_CFG_BBP_RF_BUSY_RX)))
760 + rt2x00_warn(rt2x00dev, "RF RX busy in LOFT IQ calibration\n");
761 +
762 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
763 + rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000101);
764 + rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1);
765 + }
766 +
767 + rt2800_bbp_write(rt2x00dev, 23, 0x00);
768 + rt2800_bbp_write(rt2x00dev, 24, 0x00);
769 +
770 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
771 + rt2800_bbp_write(rt2x00dev, 4, bbpr4 & (~0x18));
772 + rt2800_bbp_write(rt2x00dev, 21, 0x01);
773 + udelay(1);
774 + rt2800_bbp_write(rt2x00dev, 21, 0x00);
775 +
776 + rt2800_bbp_write(rt2x00dev, 241, 0x14);
777 + rt2800_bbp_write(rt2x00dev, 242, 0x80);
778 + rt2800_bbp_write(rt2x00dev, 244, 0x31);
779 + } else {
780 + rt2800_setbbptonegenerator(rt2x00dev);
781 + }
782 +
783 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00000004);
784 + rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00003306);
785 + udelay(1);
786 +
787 + rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x0000000F);
788 +
789 + if (!test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
790 + rt2800_register_write(rt2x00dev, RF_CONTROL3, 0x00000000);
791 + rt2800_register_write(rt2x00dev, RF_BYPASS3, 0x0000F1F1);
792 + }
793 +
794 + rt2800_register_write(rt2x00dev, 0x13b8, 0x00000010);
795 +
796 + for (ch_idx = 0; ch_idx < 2; ch_idx++)
797 + rt2800_rf_configstore(rt2x00dev, rf_store, ch_idx);
798 +
799 + rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x3B);
800 + rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x3B);
801 +
802 + rt2800_bbp_write(rt2x00dev, 158, 0x03);
803 + rt2800_bbp_write(rt2x00dev, 159, 0x60);
804 + rt2800_bbp_write(rt2x00dev, 158, 0xB0);
805 + rt2800_bbp_write(rt2x00dev, 159, 0x80);
806 +
807 + for (ch_idx = 0; ch_idx < 2; ch_idx++) {
808 + rt2800_bbp_write(rt2x00dev, 23, 0x00);
809 + rt2800_bbp_write(rt2x00dev, 24, 0x00);
810 +
811 + if (ch_idx == 0) {
812 + rt2800_bbp_write(rt2x00dev, 158, 0x01);
813 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
814 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
815 + bbp = bbpr1 & (~0x18);
816 + bbp = bbp | 0x00;
817 + rt2800_bbp_write(rt2x00dev, 1, bbp);
818 + }
819 + rt2800_rf_aux_tx0_loopback(rt2x00dev);
820 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00001004);
821 + } else {
822 + rt2800_bbp_write(rt2x00dev, 158, 0x01);
823 + rt2800_bbp_write(rt2x00dev, 159, 0x01);
824 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags)) {
825 + bbp = bbpr1 & (~0x18);
826 + bbp = bbp | 0x08;
827 + rt2800_bbp_write(rt2x00dev, 1, bbp);
828 + }
829 + rt2800_rf_aux_tx1_loopback(rt2x00dev);
830 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00002004);
831 + }
832 +
833 + rt2800_bbp_write(rt2x00dev, 158, 0x05);
834 + rt2800_bbp_write(rt2x00dev, 159, 0x04);
835 +
836 + bbp = (ch_idx == 0) ? 0x28 : 0x46;
837 + rt2800_bbp_write(rt2x00dev, 158, bbp);
838 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
839 +
840 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
841 + rt2800_bbp_write(rt2x00dev, 23, 0x06);
842 + rt2800_bbp_write(rt2x00dev, 24, 0x06);
843 + count_step = 1;
844 + } else {
845 + rt2800_bbp_write(rt2x00dev, 23, 0x1F);
846 + rt2800_bbp_write(rt2x00dev, 24, 0x1F);
847 + count_step = 2;
848 + }
849 +
850 + for (; vga_gain[ch_idx] < 19; vga_gain[ch_idx] = (vga_gain[ch_idx] + count_step)) {
851 + rfvalue = rfvga_gain_table[vga_gain[ch_idx]];
852 + rt2800_rfcsr_write_dccal(rt2x00dev, 3, rfvalue);
853 + rt2800_rfcsr_write_dccal(rt2x00dev, 4, rfvalue);
854 +
855 + bbp = (ch_idx == 0) ? 0x29 : 0x47;
856 + rt2800_bbp_write(rt2x00dev, 158, bbp);
857 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
858 + p0 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0);
859 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))
860 + p0_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A);
861 +
862 + bbp = (ch_idx == 0) ? 0x29 : 0x47;
863 + rt2800_bbp_write(rt2x00dev, 158, bbp);
864 + rt2800_bbp_write(rt2x00dev, 159, 0x21);
865 + p1 = rt2800_do_fft_accumulation(rt2x00dev, 0x14, 0);
866 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX1, &rt2x00dev->cap_flags))
867 + p1_idx10 = rt2800_read_fft_accumulation(rt2x00dev, 0x0A);
868 +
869 + rt2x00_dbg(rt2x00dev, "IQ AGC %d %d\n", p0, p1);
870 +
871 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
872 + rt2x00_dbg(rt2x00dev, "IQ AGC IDX 10 %d %d\n", p0_idx10, p1_idx10);
873 + if ((p0_idx10 > 7000 * 7000) || (p1_idx10 > 7000 * 7000)) {
874 + if (vga_gain[ch_idx] != 0)
875 + vga_gain[ch_idx] = vga_gain[ch_idx] - 1;
876 + break;
877 + }
878 + }
879 +
880 + if ((p0 > 2500 * 2500) || (p1 > 2500 * 2500))
881 + break;
882 + }
883 +
884 + if (vga_gain[ch_idx] > 18)
885 + vga_gain[ch_idx] = 18;
886 + rt2x00_dbg(rt2x00dev, "Used VGA %d %x\n", vga_gain[ch_idx],
887 + rfvga_gain_table[vga_gain[ch_idx]]);
888 +
889 + bbp = (ch_idx == 0) ? 0x29 : 0x47;
890 + rt2800_bbp_write(rt2x00dev, 158, bbp);
891 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
892 +
893 + rt2800_iq_search(rt2x00dev, ch_idx, ger, per);
894 + }
895 +
896 + rt2800_bbp_write(rt2x00dev, 23, 0x00);
897 + rt2800_bbp_write(rt2x00dev, 24, 0x00);
898 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
899 +
900 + rt2800_bbp_write(rt2x00dev, 158, 0x28);
901 + bbp = ger[CHAIN_0] & 0x0F;
902 + rt2800_bbp_write(rt2x00dev, 159, bbp);
903 +
904 + rt2800_bbp_write(rt2x00dev, 158, 0x29);
905 + bbp = per[CHAIN_0] & 0x3F;
906 + rt2800_bbp_write(rt2x00dev, 159, bbp);
907 +
908 + rt2800_bbp_write(rt2x00dev, 158, 0x46);
909 + bbp = ger[CHAIN_1] & 0x0F;
910 + rt2800_bbp_write(rt2x00dev, 159, bbp);
911 +
912 + rt2800_bbp_write(rt2x00dev, 158, 0x47);
913 + bbp = per[CHAIN_1] & 0x3F;
914 + rt2800_bbp_write(rt2x00dev, 159, bbp);
915 +
916 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags)) {
917 + rt2800_bbp_write(rt2x00dev, 1, bbpr1);
918 + rt2800_bbp_write(rt2x00dev, 241, bbpr241);
919 + rt2800_bbp_write(rt2x00dev, 242, bbpr242);
920 + }
921 + rt2800_bbp_write(rt2x00dev, 244, 0x00);
922 +
923 + rt2800_bbp_write(rt2x00dev, 158, 0x00);
924 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
925 + rt2800_bbp_write(rt2x00dev, 158, 0xB0);
926 + rt2800_bbp_write(rt2x00dev, 159, 0x00);
927 +
928 + rt2800_bbp_write(rt2x00dev, 30, bbpr30);
929 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 39, rfb0r39);
930 + rt2800_rfcsr_write_bank(rt2x00dev, 0, 42, rfb0r42);
931 +
932 + if (test_bit(CAPABILITY_EXTERNAL_PA_TX0, &rt2x00dev->cap_flags))
933 + rt2800_bbp_write(rt2x00dev, 4, bbpr4);
934 +
935 + rt2800_bbp_write(rt2x00dev, 21, 0x01);
936 + udelay(1);
937 + rt2800_bbp_write(rt2x00dev, 21, 0x00);
938 +
939 + rt2800_rf_configrecover(rt2x00dev, rf_store);
940 +
941 + rt2800_register_write(rt2x00dev, TX_PIN_CFG, macorg1);
942 + rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x00);
943 + rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x00);
944 + rt2800_register_write(rt2x00dev, RF_CONTROL0, macorg2);
945 + udelay(1);
946 + rt2800_register_write(rt2x00dev, RF_BYPASS0, macorg3);
947 + rt2800_register_write(rt2x00dev, RF_CONTROL3, macorg4);
948 + rt2800_register_write(rt2x00dev, RF_BYPASS3, macorg5);
949 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
950 + rt2800_register_write(rt2x00dev, 0x13b8, mac13b8);
951 +}
952 +
953 static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
954 bool set_bw, bool is_ht40)
955 {
956 @@ -9678,6 +10579,7 @@ static void rt2800_init_rfcsr_6352(struc
957 rt2800_rxdcoc_calibration(rt2x00dev);
958 rt2800_bw_filter_calibration(rt2x00dev, true);
959 rt2800_bw_filter_calibration(rt2x00dev, false);
960 + rt2800_loft_iq_calibration(rt2x00dev);
961 rt2800_rxiq_calibration(rt2x00dev);
962 }
963
964 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.h
965 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.h
966 @@ -17,6 +17,16 @@
967 #define WCID_START 33
968 #define WCID_END 222
969 #define STA_IDS_SIZE (WCID_END - WCID_START + 2)
970 +#define CHAIN_0 0x0
971 +#define CHAIN_1 0x1
972 +#define RF_ALC_NUM 6
973 +#define CHAIN_NUM 2
974 +
975 +struct rf_reg_pair {
976 + u8 bank;
977 + u8 reg;
978 + u8 value;
979 +};
980
981 /* RT2800 driver data structure */
982 struct rt2800_drv_data {
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