target/linux/ar71xx/files/arch/mips/ar71xx/setup.c

   1 /*
   2  *  Atheros AR71xx SoC specific setup
   3  *
   4  *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
   5  *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
   6  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   7  *
   8  *  Parts of this file are based on Atheros 2.6.15 BSP
   9  *  Parts of this file are based on Atheros 2.6.31 BSP
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License version 2 as published
  13  *  by the Free Software Foundation.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/bootmem.h>
  19
  20 #include <asm/bootinfo.h>
  21 #include <asm/time.h>           /* for mips_hpt_frequency */
  22 #include <asm/reboot.h>         /* for _machine_{restart,halt} */
  23 #include <asm/mips_machine.h>
  24
  25 #include <asm/mach-ar71xx/ar71xx.h>
  26
  27 #include "machtype.h"
  28 #include "devices.h"
  29
  30 #define AR71XX_SYS_TYPE_LEN     64
  31
  32 u32 ar71xx_cpu_freq;
  33 EXPORT_SYMBOL_GPL(ar71xx_cpu_freq);
  34
  35 u32 ar71xx_ahb_freq;
  36 EXPORT_SYMBOL_GPL(ar71xx_ahb_freq);
  37
  38 u32 ar71xx_ddr_freq;
  39 EXPORT_SYMBOL_GPL(ar71xx_ddr_freq);
  40
  41 u32 ar71xx_ref_freq;
  42 EXPORT_SYMBOL_GPL(ar71xx_ref_freq);
  43
  44 enum ar71xx_soc_type ar71xx_soc;
  45 EXPORT_SYMBOL_GPL(ar71xx_soc);
  46
  47 u32 ar71xx_soc_rev;
  48 EXPORT_SYMBOL_GPL(ar71xx_soc_rev);
  49
  50 static char ar71xx_sys_type[AR71XX_SYS_TYPE_LEN];
  51
  52 static void ar71xx_restart(char *command)
  53 {
  54         ar71xx_device_stop(RESET_MODULE_FULL_CHIP);
  55         for (;;)
  56                 if (cpu_wait)
  57                         cpu_wait();
  58 }
  59
  60 static void ar71xx_halt(void)
  61 {
  62         while (1)
  63                 cpu_wait();
  64 }
  65
  66 static void __init ar71xx_detect_mem_size(void)
  67 {
  68         unsigned long size;
  69
  70         for (size = AR71XX_MEM_SIZE_MIN; size < AR71XX_MEM_SIZE_MAX;
  71              size <<= 1) {
  72                 if (!memcmp(ar71xx_detect_mem_size,
  73                             ar71xx_detect_mem_size + size, 1024))
  74                         break;
  75         }
  76
  77         add_memory_region(0, size, BOOT_MEM_RAM);
  78 }
  79
  80 static void __init ar71xx_detect_sys_type(void)
  81 {
  82         char *chip = "????";
  83         u32 id;
  84         u32 major;
  85         u32 minor;
  86         u32 rev = 0;
  87
  88         id = ar71xx_reset_rr(AR71XX_RESET_REG_REV_ID);
  89         major = id & REV_ID_MAJOR_MASK;
  90
  91         switch (major) {
  92         case REV_ID_MAJOR_AR71XX:
  93                 minor = id & AR71XX_REV_ID_MINOR_MASK;
  94                 rev = id >> AR71XX_REV_ID_REVISION_SHIFT;
  95                 rev &= AR71XX_REV_ID_REVISION_MASK;
  96                 switch (minor) {
  97                 case AR71XX_REV_ID_MINOR_AR7130:
  98                         ar71xx_soc = AR71XX_SOC_AR7130;
  99                         chip = "7130";
 100                         break;
 101
 102                 case AR71XX_REV_ID_MINOR_AR7141:
 103                         ar71xx_soc = AR71XX_SOC_AR7141;
 104                         chip = "7141";
 105                         break;
 106
 107                 case AR71XX_REV_ID_MINOR_AR7161:
 108                         ar71xx_soc = AR71XX_SOC_AR7161;
 109                         chip = "7161";
 110                         break;
 111                 }
 112                 break;
 113
 114         case REV_ID_MAJOR_AR7240:
 115                 ar71xx_soc = AR71XX_SOC_AR7240;
 116                 chip = "7240";
 117                 rev = id & AR724X_REV_ID_REVISION_MASK;
 118                 break;
 119
 120         case REV_ID_MAJOR_AR7241:
 121                 ar71xx_soc = AR71XX_SOC_AR7241;
 122                 chip = "7241";
 123                 rev = id & AR724X_REV_ID_REVISION_MASK;
 124                 break;
 125
 126         case REV_ID_MAJOR_AR7242:
 127                 ar71xx_soc = AR71XX_SOC_AR7242;
 128                 chip = "7242";
 129                 rev = id & AR724X_REV_ID_REVISION_MASK;
 130                 break;
 131
 132         case REV_ID_MAJOR_AR913X:
 133                 minor = id & AR91XX_REV_ID_MINOR_MASK;
 134                 rev = id >> AR91XX_REV_ID_REVISION_SHIFT;
 135                 rev &= AR91XX_REV_ID_REVISION_MASK;
 136                 switch (minor) {
 137                 case AR91XX_REV_ID_MINOR_AR9130:
 138                         ar71xx_soc = AR71XX_SOC_AR9130;
 139                         chip = "9130";
 140                         break;
 141
 142                 case AR91XX_REV_ID_MINOR_AR9132:
 143                         ar71xx_soc = AR71XX_SOC_AR9132;
 144                         chip = "9132";
 145                         break;
 146                 }
 147                 break;
 148
 149         case REV_ID_MAJOR_AR9330:
 150                 ar71xx_soc = AR71XX_SOC_AR9330;
 151                 chip = "9330";
 152                 rev = id & AR933X_REV_ID_REVISION_MASK;
 153                 break;
 154
 155         case REV_ID_MAJOR_AR9331:
 156                 ar71xx_soc = AR71XX_SOC_AR9331;
 157                 chip = "9331";
 158                 rev = id & AR933X_REV_ID_REVISION_MASK;
 159                 break;
 160
 161         case REV_ID_MAJOR_AR9342:
 162                 ar71xx_soc = AR71XX_SOC_AR9342;
 163                 chip = "9342";
 164                 rev = id & AR934X_REV_ID_REVISION_MASK;
 165                 break;
 166
 167         case REV_ID_MAJOR_AR9344:
 168                 ar71xx_soc = AR71XX_SOC_AR9344;
 169                 chip = "9344";
 170                 rev = id & AR934X_REV_ID_REVISION_MASK;
 171                 break;
 172
 173         default:
 174                 panic("ar71xx: unknown chip id:0x%08x\n", id);
 175         }
 176
 177         ar71xx_soc_rev = rev;
 178
 179         sprintf(ar71xx_sys_type, "Atheros AR%s rev %u", chip, rev);
 180         pr_info("SoC: %s\n", ar71xx_sys_type);
 181 }
 182
 183 static void __init ar934x_detect_sys_frequency(void)
 184 {
 185         u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
 186
 187         if (ar71xx_reset_rr(AR934X_RESET_REG_BOOTSTRAP) & AR934X_REF_CLK_40)
 188                 ar71xx_ref_freq = 40 * 1000 * 1000;
 189         else
 190                 ar71xx_ref_freq = 25 * 1000 * 1000;
 191
 192         clk_ctrl = ar71xx_pll_rr(AR934X_PLL_REG_DDR_CTRL_CLOCK);
 193
 194         pll = ar71xx_pll_rr(AR934X_PLL_REG_CPU_CONFIG);
 195         out_div = AR934X_CPU_PLL_CFG_OUTDIV_GET(pll);
 196         ref_div = AR934X_CPU_PLL_CFG_REFDIV_GET(pll);
 197         nint    = AR934X_CPU_PLL_CFG_NINT_GET(pll);
 198         frac    = AR934X_CPU_PLL_CFG_NFRAC_GET(pll);
 199         postdiv = AR934X_CPU_DDR_CLK_CTRL_CPU_POST_DIV_GET(clk_ctrl);
 200         ar71xx_cpu_freq = ((nint * ar71xx_ref_freq / ref_div) >> out_div) /
 201                           (postdiv + 1);
 202
 203         out_div = AR934X_DDR_PLL_CFG_OUTDIV_GET(pll);
 204         ref_div = AR934X_DDR_PLL_CFG_REFDIV_GET(pll);
 205         nint    = AR934X_DDR_PLL_CFG_NINT_GET(pll);
 206         frac    = AR934X_DDR_PLL_CFG_NFRAC_GET(pll);
 207         postdiv = AR934X_CPU_DDR_CLK_CTRL_DDR_POST_DIV_GET(clk_ctrl);
 208         ar71xx_ddr_freq = ((nint * ar71xx_ref_freq / ref_div) >> out_div) /
 209                           (postdiv + 1);
 210
 211         postdiv = AR934X_CPU_DDR_CLK_CTRL_AHB_POST_DIV_GET(clk_ctrl);
 212
 213         if (AR934X_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL_GET(clk_ctrl)) {
 214                 ar71xx_ahb_freq = ar71xx_ddr_freq / (postdiv + 1);
 215         } else {
 216                 ar71xx_ahb_freq = ar71xx_cpu_freq / (postdiv + 1);
 217         }
 218
 219 }
 220
 221 static void __init ar91xx_detect_sys_frequency(void)
 222 {
 223         u32 pll;
 224         u32 freq;
 225         u32 div;
 226
 227         ar71xx_ref_freq = 5 * 1000 * 1000;
 228
 229         pll = ar71xx_pll_rr(AR91XX_PLL_REG_CPU_CONFIG);
 230
 231         div = ((pll >> AR91XX_PLL_DIV_SHIFT) & AR91XX_PLL_DIV_MASK);
 232         freq = div * ar71xx_ref_freq;
 233
 234         ar71xx_cpu_freq = freq;
 235
 236         div = ((pll >> AR91XX_DDR_DIV_SHIFT) & AR91XX_DDR_DIV_MASK) + 1;
 237         ar71xx_ddr_freq = freq / div;
 238
 239         div = (((pll >> AR91XX_AHB_DIV_SHIFT) & AR91XX_AHB_DIV_MASK) + 1) * 2;
 240         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 241 }
 242
 243 static void __init ar71xx_detect_sys_frequency(void)
 244 {
 245         u32 pll;
 246         u32 freq;
 247         u32 div;
 248
 249         ar71xx_ref_freq = 40 * 1000 * 1000;
 250
 251         pll = ar71xx_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
 252
 253         div = ((pll >> AR71XX_PLL_DIV_SHIFT) & AR71XX_PLL_DIV_MASK) + 1;
 254         freq = div * ar71xx_ref_freq;
 255
 256         div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
 257         ar71xx_cpu_freq = freq / div;
 258
 259         div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
 260         ar71xx_ddr_freq = freq / div;
 261
 262         div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
 263         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 264 }
 265
 266 static void __init ar724x_detect_sys_frequency(void)
 267 {
 268         u32 pll;
 269         u32 freq;
 270         u32 div;
 271
 272         ar71xx_ref_freq = 5 * 1000 * 1000;
 273
 274         pll = ar71xx_pll_rr(AR724X_PLL_REG_CPU_CONFIG);
 275
 276         div = ((pll >> AR724X_PLL_DIV_SHIFT) & AR724X_PLL_DIV_MASK);
 277         freq = div * ar71xx_ref_freq;
 278
 279         div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK);
 280         freq *= div;
 281
 282         ar71xx_cpu_freq = freq;
 283
 284         div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
 285         ar71xx_ddr_freq = freq / div;
 286
 287         div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
 288         ar71xx_ahb_freq = ar71xx_cpu_freq / div;
 289 }
 290
 291 static void __init ar933x_detect_sys_frequency(void)
 292 {
 293         u32 clock_ctrl;
 294         u32 cpu_config;
 295         u32 freq;
 296         u32 t;
 297
 298         t = ar71xx_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
 299         if (t & AR933X_BOOTSTRAP_REF_CLK_40)
 300                 ar71xx_ref_freq = (40 * 1000 * 1000);
 301         else
 302                 ar71xx_ref_freq = (25 * 1000 * 1000);
 303
 304         clock_ctrl = ar71xx_pll_rr(AR933X_PLL_CLOCK_CTRL_REG);
 305         if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
 306                 ar71xx_cpu_freq = ar71xx_ref_freq;
 307                 ar71xx_ahb_freq = ar71xx_ref_freq;
 308                 ar71xx_ddr_freq = ar71xx_ref_freq;
 309         } else {
 310                 cpu_config = ar71xx_pll_rr(AR933X_PLL_CPU_CONFIG_REG);
 311
 312                 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
 313                     AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
 314                 freq = ar71xx_ref_freq / t;
 315
 316                 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
 317                     AR933X_PLL_CPU_CONFIG_NINT_MASK;
 318                 freq *= t;
 319
 320                 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
 321                     AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
 322                 if (t == 0)
 323                         t = 1;
 324
 325                 freq >>= t;
 326
 327                 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
 328                      AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
 329                 ar71xx_cpu_freq = freq / t;
 330
 331                 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
 332                       AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
 333                 ar71xx_ddr_freq = freq / t;
 334
 335                 t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
 336                      AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
 337                 ar71xx_ahb_freq = freq / t;
 338         }
 339 }
 340
 341 static void __init detect_sys_frequency(void)
 342 {
 343         switch (ar71xx_soc) {
 344         case AR71XX_SOC_AR7130:
 345         case AR71XX_SOC_AR7141:
 346         case AR71XX_SOC_AR7161:
 347                 ar71xx_detect_sys_frequency();
 348                 break;
 349
 350         case AR71XX_SOC_AR7240:
 351         case AR71XX_SOC_AR7241:
 352         case AR71XX_SOC_AR7242:
 353                 ar724x_detect_sys_frequency();
 354                 break;
 355
 356         case AR71XX_SOC_AR9130:
 357         case AR71XX_SOC_AR9132:
 358                 ar91xx_detect_sys_frequency();
 359                 break;
 360
 361         case AR71XX_SOC_AR9330:
 362         case AR71XX_SOC_AR9331:
 363                 ar933x_detect_sys_frequency();
 364                 break;
 365
 366         case AR71XX_SOC_AR9341:
 367         case AR71XX_SOC_AR9342:
 368         case AR71XX_SOC_AR9344:
 369                 ar934x_detect_sys_frequency();
 370                 break;
 371         default:
 372                 BUG();
 373         }
 374 }
 375
 376 const char *get_system_type(void)
 377 {
 378         return ar71xx_sys_type;
 379 }
 380
 381 unsigned int __cpuinit get_c0_compare_irq(void)
 382 {
 383         return CP0_LEGACY_COMPARE_IRQ;
 384 }
 385
 386 void __init plat_mem_setup(void)
 387 {
 388         set_io_port_base(KSEG1);
 389
 390         ar71xx_ddr_base = ioremap_nocache(AR71XX_DDR_CTRL_BASE,
 391                                                 AR71XX_DDR_CTRL_SIZE);
 392
 393         ar71xx_pll_base = ioremap_nocache(AR71XX_PLL_BASE,
 394                                                 AR71XX_PLL_SIZE);
 395
 396         ar71xx_reset_base = ioremap_nocache(AR71XX_RESET_BASE,
 397                                                 AR71XX_RESET_SIZE);
 398
 399         ar71xx_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
 400
 401         ar71xx_usb_ctrl_base = ioremap_nocache(AR71XX_USB_CTRL_BASE,
 402                                                 AR71XX_USB_CTRL_SIZE);
 403
 404         ar71xx_detect_mem_size();
 405         ar71xx_detect_sys_type();
 406         detect_sys_frequency();
 407
 408         pr_info("Clocks: CPU:%u.%03uMHz, DDR:%u.%03uMHz, AHB:%u.%03uMHz, "
 409                 "Ref:%u.%03uMHz",
 410                 ar71xx_cpu_freq / 1000000, (ar71xx_cpu_freq / 1000) % 1000,
 411                 ar71xx_ddr_freq / 1000000, (ar71xx_ddr_freq / 1000) % 1000,
 412                 ar71xx_ahb_freq / 1000000, (ar71xx_ahb_freq / 1000) % 1000,
 413                 ar71xx_ref_freq / 1000000, (ar71xx_ref_freq / 1000) % 1000);
 414
 415         _machine_restart = ar71xx_restart;
 416         _machine_halt = ar71xx_halt;
 417         pm_power_off = ar71xx_halt;
 418 }
 419
 420 void __init plat_time_init(void)
 421 {
 422         mips_hpt_frequency = ar71xx_cpu_freq / 2;
 423 }
 424
 425 __setup("board=", mips_machtype_setup);
 426
 427 static int __init ar71xx_machine_setup(void)
 428 {
 429         ar71xx_gpio_init();
 430
 431         ar71xx_add_device_uart();
 432         ar71xx_add_device_wdt();
 433
 434         mips_machine_setup();
 435         return 0;
 436 }
 437
 438 arch_initcall(ar71xx_machine_setup);
 439
 440 static void __init ar71xx_generic_init(void)
 441 {
 442         /* Nothing to do */
 443 }
 444
 445 MIPS_MACHINE(AR71XX_MACH_GENERIC, "Generic", "Generic AR71xx board",
 446              ar71xx_generic_init);