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[openwrt/openwrt.git] / target / linux / ar71xx / files / arch / mips / ath79 / mach-rbspi.c
1 /*
2 * MikroTik SPI-NOR RouterBOARDs support
3 *
4 * - MikroTik RouterBOARD mAP L-2nD
5 * - MikroTik RouterBOARD 941L-2nD
6 * - MikroTik RouterBOARD 951Ui-2nD
7 * - MikroTik RouterBOARD 952Ui-5ac2nD
8 * - MikroTik RouterBOARD 962UiGS-5HacT2HnT
9 * - MikroTik RouterBOARD 750UP r2
10 * - MikroTik RouterBOARD 750P-PBr2
11 * - MikroTik RouterBOARD 750 r2
12 * - MikroTik RouterBOARD LHG 5nD
13 *
14 * Preliminary support for the following hardware
15 * - MikroTik RouterBOARD wAP2nD
16 * - MikroTik RouterBOARD cAP2nD
17 * - MikroTik RouterBOARD mAP2nD
18 * Furthermore, the cAP lite (cAPL2nD) appears to feature the exact same
19 * hardware as the mAP L-2nD. It is unknown if they share the same board
20 * identifier.
21 *
22 * Copyright (C) 2017 Thibaut VARENE <varenet@parisc-linux.org>
23 * Copyright (C) 2016 David Hutchison <dhutchison@bluemesh.net>
24 * Copyright (C) 2017 Ryan Mounce <ryan@mounce.com.au>
25 *
26 * This program is free software; you can redistribute it and/or modify it
27 * under the terms of the GNU General Public License version 2 as published
28 * by the Free Software Foundation.
29 */
30
31 #include <linux/pci.h>
32 #include <linux/platform_device.h>
33 #include <linux/phy.h>
34 #include <linux/routerboot.h>
35 #include <linux/gpio.h>
36
37 #include <linux/spi/spi.h>
38 #include <linux/spi/74x164.h>
39
40 #include <linux/mtd/mtd.h>
41 #include <linux/mtd/partitions.h>
42
43 #include <linux/ar8216_platform.h>
44
45 #include <asm/prom.h>
46 #include <asm/mach-ath79/ar71xx_regs.h>
47 #include <asm/mach-ath79/ath79.h>
48
49 #include "common.h"
50 #include "dev-eth.h"
51 #include "dev-spi.h"
52 #include "dev-gpio-buttons.h"
53 #include "dev-leds-gpio.h"
54 #include "dev-m25p80.h"
55 #include "dev-usb.h"
56 #include "dev-wmac.h"
57 #include "machtypes.h"
58 #include "pci.h"
59 #include "routerboot.h"
60
61 #define RBSPI_KEYS_POLL_INTERVAL 20 /* msecs */
62 #define RBSPI_KEYS_DEBOUNCE_INTERVAL (3 * RBSPI_KEYS_POLL_INTERVAL)
63
64 #define RBSPI_HAS_USB BIT(0)
65 #define RBSPI_HAS_WLAN0 BIT(1)
66 #define RBSPI_HAS_WLAN1 BIT(2)
67 #define RBSPI_HAS_WAN4 BIT(3) /* has WAN port on PHY4 */
68 #define RBSPI_HAS_SSR BIT(4) /* has an SSR on SPI bus 0 */
69 #define RBSPI_HAS_POE BIT(5)
70 #define RBSPI_HAS_MDIO1 BIT(6)
71 #define RBSPI_HAS_PCI BIT(7)
72
73 #define RB_ROUTERBOOT_OFFSET 0x0000
74 #define RB_BIOS_SIZE 0x1000
75 #define RB_SOFT_CFG_SIZE 0x1000
76
77 /* Flash partitions indexes */
78 enum {
79 RBSPI_PART_RBOOT,
80 RBSPI_PART_HCONF,
81 RBSPI_PART_BIOS,
82 RBSPI_PART_RBOOT2,
83 RBSPI_PART_SCONF,
84 RBSPI_PART_FIRMW,
85 RBSPI_PARTS
86 };
87
88 static struct mtd_partition rbspi_spi_partitions[RBSPI_PARTS];
89
90 /*
91 * Setup the SPI flash partition table based on initial parsing.
92 * The kernel can be at any aligned position and have any size.
93 */
94 static void __init rbspi_init_partitions(const struct rb_info *info)
95 {
96 struct mtd_partition *parts = rbspi_spi_partitions;
97 memset(parts, 0x0, sizeof(*parts));
98
99 parts[RBSPI_PART_RBOOT].name = "routerboot";
100 parts[RBSPI_PART_RBOOT].offset = RB_ROUTERBOOT_OFFSET;
101 parts[RBSPI_PART_RBOOT].size = info->hard_cfg_offs;
102 parts[RBSPI_PART_RBOOT].mask_flags = MTD_WRITEABLE;
103
104 parts[RBSPI_PART_HCONF].name = "hard_config";
105 parts[RBSPI_PART_HCONF].offset = info->hard_cfg_offs;
106 parts[RBSPI_PART_HCONF].size = info->hard_cfg_size;
107 parts[RBSPI_PART_HCONF].mask_flags = MTD_WRITEABLE;
108
109 parts[RBSPI_PART_BIOS].name = "bios";
110 parts[RBSPI_PART_BIOS].offset = info->hard_cfg_offs
111 + info->hard_cfg_size;
112 parts[RBSPI_PART_BIOS].size = RB_BIOS_SIZE;
113 parts[RBSPI_PART_BIOS].mask_flags = MTD_WRITEABLE;
114
115 parts[RBSPI_PART_RBOOT2].name = "routerboot2";
116 parts[RBSPI_PART_RBOOT2].offset = parts[RBSPI_PART_BIOS].offset
117 + RB_BIOS_SIZE;
118 parts[RBSPI_PART_RBOOT2].size = info->soft_cfg_offs
119 - parts[RBSPI_PART_RBOOT2].offset;
120 parts[RBSPI_PART_RBOOT2].mask_flags = MTD_WRITEABLE;
121
122 parts[RBSPI_PART_SCONF].name = "soft_config";
123 parts[RBSPI_PART_SCONF].offset = info->soft_cfg_offs;
124 parts[RBSPI_PART_SCONF].size = RB_SOFT_CFG_SIZE;
125
126 parts[RBSPI_PART_FIRMW].name = "firmware";
127 parts[RBSPI_PART_FIRMW].offset = parts[RBSPI_PART_SCONF].offset
128 + parts[RBSPI_PART_SCONF].size;
129 parts[RBSPI_PART_FIRMW].size = MTDPART_SIZ_FULL;
130 }
131
132 static struct flash_platform_data rbspi_spi_flash_data = {
133 .parts = rbspi_spi_partitions,
134 .nr_parts = ARRAY_SIZE(rbspi_spi_partitions),
135 };
136
137 /* Several boards only have a single reset button wired to GPIO 16 */
138 #define RBSPI_GPIO_BTN_RESET16 16
139 #define RBSPI_GPIO_BTN_RESET20 20
140
141 static struct gpio_keys_button rbspi_gpio_keys_reset16[] __initdata = {
142 {
143 .desc = "Reset button",
144 .type = EV_KEY,
145 .code = KEY_RESTART,
146 .debounce_interval = RBSPI_KEYS_DEBOUNCE_INTERVAL,
147 .gpio = RBSPI_GPIO_BTN_RESET16,
148 .active_low = 1,
149 },
150 };
151
152 static struct gpio_keys_button rbspi_gpio_keys_reset20[] __initdata = {
153 {
154 .desc = "Reset button",
155 .type = EV_KEY,
156 .code = KEY_RESTART,
157 .debounce_interval = RBSPI_KEYS_DEBOUNCE_INTERVAL,
158 .gpio = RBSPI_GPIO_BTN_RESET20,
159 .active_low = 1,
160 },
161 };
162
163 /* RB mAP L-2nD gpios */
164 #define RBMAPL_GPIO_LED_POWER 17
165 #define RBMAPL_GPIO_LED_USER 14
166 #define RBMAPL_GPIO_LED_ETH 4
167 #define RBMAPL_GPIO_LED_WLAN 11
168
169 static struct gpio_led rbmapl_leds[] __initdata = {
170 {
171 .name = "rb:green:power",
172 .gpio = RBMAPL_GPIO_LED_POWER,
173 .active_low = 0,
174 .default_state = LEDS_GPIO_DEFSTATE_ON,
175 }, {
176 .name = "rb:green:user",
177 .gpio = RBMAPL_GPIO_LED_USER,
178 .active_low = 0,
179 }, {
180 .name = "rb:green:eth",
181 .gpio = RBMAPL_GPIO_LED_ETH,
182 .active_low = 0,
183 }, {
184 .name = "rb:green:wlan",
185 .gpio = RBMAPL_GPIO_LED_WLAN,
186 .active_low = 0,
187 },
188 };
189
190 /* RB 941L-2nD gpios */
191 #define RBHAPL_GPIO_LED_USER 14
192 static struct gpio_led rbhapl_leds[] __initdata = {
193 {
194 .name = "rb:green:user",
195 .gpio = RBHAPL_GPIO_LED_USER,
196 .active_low = 1,
197 },
198 };
199
200 /* common RB SSRs */
201 #define RBSPI_SSR_GPIO_BASE 40
202 #define RBSPI_SSR_GPIO(bit) (RBSPI_SSR_GPIO_BASE + (bit))
203
204 /* RB 951Ui-2nD gpios */
205 #define RB952_SSR_BIT_LED_LAN1 0
206 #define RB952_SSR_BIT_LED_LAN2 1
207 #define RB952_SSR_BIT_LED_LAN3 2
208 #define RB952_SSR_BIT_LED_LAN4 3
209 #define RB952_SSR_BIT_LED_LAN5 4
210 #define RB952_SSR_BIT_USB_POWER 5
211 #define RB952_SSR_BIT_LED_WLAN 6
212 #define RB952_GPIO_SSR_CS 11
213 #define RB952_GPIO_LED_USER 4
214 #define RB952_GPIO_POE_POWER 14
215 #define RB952_GPIO_POE_STATUS 12
216 #define RB952_GPIO_USB_POWER RBSPI_SSR_GPIO(RB952_SSR_BIT_USB_POWER)
217 #define RB952_GPIO_LED_LAN1 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN1)
218 #define RB952_GPIO_LED_LAN2 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN2)
219 #define RB952_GPIO_LED_LAN3 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN3)
220 #define RB952_GPIO_LED_LAN4 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN4)
221 #define RB952_GPIO_LED_LAN5 RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_LAN5)
222 #define RB952_GPIO_LED_WLAN RBSPI_SSR_GPIO(RB952_SSR_BIT_LED_WLAN)
223
224 static struct gpio_led rb952_leds[] __initdata = {
225 {
226 .name = "rb:green:user",
227 .gpio = RB952_GPIO_LED_USER,
228 .active_low = 0,
229 }, {
230 .name = "rb:blue:wlan",
231 .gpio = RB952_GPIO_LED_WLAN,
232 .active_low = 1,
233 }, {
234 .name = "rb:green:port1",
235 .gpio = RB952_GPIO_LED_LAN1,
236 .active_low = 1,
237 }, {
238 .name = "rb:green:port2",
239 .gpio = RB952_GPIO_LED_LAN2,
240 .active_low = 1,
241 }, {
242 .name = "rb:green:port3",
243 .gpio = RB952_GPIO_LED_LAN3,
244 .active_low = 1,
245 }, {
246 .name = "rb:green:port4",
247 .gpio = RB952_GPIO_LED_LAN4,
248 .active_low = 1,
249 }, {
250 .name = "rb:green:port5",
251 .gpio = RB952_GPIO_LED_LAN5,
252 .active_low = 1,
253 },
254 };
255
256
257 /* RB 962UiGS-5HacT2HnT gpios */
258 #define RB962_GPIO_POE_STATUS 2
259 #define RB962_GPIO_POE_POWER 3
260 #define RB962_GPIO_LED_USER 12
261 #define RB962_GPIO_USB_POWER 13
262
263 static struct gpio_led rb962_leds_gpio[] __initdata = {
264 {
265 .name = "rb:green:user",
266 .gpio = RB962_GPIO_LED_USER,
267 .active_low = 1,
268 },
269 };
270
271 static const struct ar8327_led_info rb962_leds_ar8327[] = {
272 AR8327_LED_INFO(PHY0_0, HW, "rb:green:port1"),
273 AR8327_LED_INFO(PHY1_0, HW, "rb:green:port2"),
274 AR8327_LED_INFO(PHY2_0, HW, "rb:green:port3"),
275 AR8327_LED_INFO(PHY3_0, HW, "rb:green:port4"),
276 AR8327_LED_INFO(PHY4_0, HW, "rb:green:port5"),
277 };
278
279 static struct ar8327_pad_cfg rb962_ar8327_pad0_cfg = {
280 .mode = AR8327_PAD_MAC_RGMII,
281 .txclk_delay_en = true,
282 .rxclk_delay_en = true,
283 .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
284 .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
285 .mac06_exchange_dis = true,
286 };
287
288 static struct ar8327_pad_cfg rb962_ar8327_pad6_cfg = {
289 /* Use SGMII interface for GMAC6 of the AR8337 switch */
290 .mode = AR8327_PAD_MAC_SGMII,
291 .rxclk_delay_en = true,
292 .rxclk_delay_sel = AR8327_CLK_DELAY_SEL0,
293 };
294
295 static struct ar8327_led_cfg rb962_ar8327_led_cfg = {
296 .led_ctrl0 = 0xc737c737,
297 .led_ctrl1 = 0x00000000,
298 .led_ctrl2 = 0x00000000,
299 .led_ctrl3 = 0x0030c300,
300 .open_drain = false,
301 };
302
303 static struct ar8327_platform_data rb962_ar8327_data = {
304 .pad0_cfg = &rb962_ar8327_pad0_cfg,
305 .pad6_cfg = &rb962_ar8327_pad6_cfg,
306 .port0_cfg = {
307 .force_link = 1,
308 .speed = AR8327_PORT_SPEED_1000,
309 .duplex = 1,
310 .txpause = 1,
311 .rxpause = 1,
312 },
313 .port6_cfg = {
314 .force_link = 1,
315 .speed = AR8327_PORT_SPEED_1000,
316 .duplex = 1,
317 .txpause = 1,
318 .rxpause = 1,
319 },
320 .led_cfg = &rb962_ar8327_led_cfg,
321 .num_leds = ARRAY_SIZE(rb962_leds_ar8327),
322 .leds = rb962_leds_ar8327,
323 };
324
325 static struct mdio_board_info rb962_mdio0_info[] = {
326 {
327 .bus_id = "ag71xx-mdio.0",
328 .phy_addr = 0,
329 .platform_data = &rb962_ar8327_data,
330 },
331 };
332
333 /* RB wAP-2nD gpios */
334 #define RBWAP_GPIO_LED_USER 14
335 #define RBWAP_GPIO_LED_WLAN 11
336
337 static struct gpio_led rbwap_leds[] __initdata = {
338 {
339 .name = "rb:green:user",
340 .gpio = RBWAP_GPIO_LED_USER,
341 .active_low = 1,
342 }, {
343 .name = "rb:green:wlan",
344 .gpio = RBWAP_GPIO_LED_WLAN,
345 .active_low = 1,
346 },
347 };
348
349 /* RB cAP-2nD gpios */
350 #define RBCAP_GPIO_LED_1 14
351 #define RBCAP_GPIO_LED_2 12
352 #define RBCAP_GPIO_LED_3 11
353 #define RBCAP_GPIO_LED_4 4
354 #define RBCAP_GPIO_LED_ALL 13
355
356 static struct gpio_led rbcap_leds[] __initdata = {
357 {
358 .name = "rb:green:rssi1",
359 .gpio = RBCAP_GPIO_LED_1,
360 .active_low = 1,
361 }, {
362 .name = "rb:green:rssi2",
363 .gpio = RBCAP_GPIO_LED_2,
364 .active_low = 1,
365 }, {
366 .name = "rb:green:rssi3",
367 .gpio = RBCAP_GPIO_LED_3,
368 .active_low = 1,
369 }, {
370 .name = "rb:green:rssi4",
371 .gpio = RBCAP_GPIO_LED_4,
372 .active_low = 1,
373 },
374 };
375
376 /* RB mAP-2nD gpios */
377 #define RBMAP_SSR_BIT_LED_LAN1 0
378 #define RBMAP_SSR_BIT_LED_LAN2 1
379 #define RBMAP_SSR_BIT_LED_POEO 2
380 #define RBMAP_SSR_BIT_LED_USER 3
381 #define RBMAP_SSR_BIT_LED_WLAN 4
382 #define RBMAP_SSR_BIT_USB_POWER 5
383 #define RBMAP_SSR_BIT_LED_APCAP 6
384 #define RBMAP_GPIO_SSR_CS 11
385 #define RBMAP_GPIO_LED_POWER 4
386 #define RBMAP_GPIO_POE_POWER 14
387 #define RBMAP_GPIO_POE_STATUS 12
388 #define RBMAP_GPIO_USB_POWER RBSPI_SSR_GPIO(RBMAP_SSR_BIT_USB_POWER)
389 #define RBMAP_GPIO_LED_LAN1 RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_LAN1)
390 #define RBMAP_GPIO_LED_LAN2 RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_LAN2)
391 #define RBMAP_GPIO_LED_POEO RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_POEO)
392 #define RBMAP_GPIO_LED_USER RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_USER)
393 #define RBMAP_GPIO_LED_WLAN RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_WLAN)
394 #define RBMAP_GPIO_LED_APCAP RBSPI_SSR_GPIO(RBMAP_SSR_BIT_LED_APCAP)
395
396 static struct gpio_led rbmap_leds[] __initdata = {
397 {
398 .name = "rb:green:power",
399 .gpio = RBMAP_GPIO_LED_POWER,
400 .active_low = 1,
401 .default_state = LEDS_GPIO_DEFSTATE_ON,
402 }, {
403 .name = "rb:green:eth1",
404 .gpio = RBMAP_GPIO_LED_LAN1,
405 .active_low = 1,
406 }, {
407 .name = "rb:green:eth2",
408 .gpio = RBMAP_GPIO_LED_WLAN,
409 .active_low = 1,
410 }, {
411 .name = "rb:red:poe_out",
412 .gpio = RBMAP_GPIO_LED_POEO,
413 .active_low = 1,
414 }, {
415 .name = "rb:green:user",
416 .gpio = RBMAP_GPIO_LED_USER,
417 .active_low = 1,
418 }, {
419 .name = "rb:green:wlan",
420 .gpio = RBMAP_GPIO_LED_WLAN,
421 .active_low = 1,
422 }, {
423 .name = "rb:green:ap_cap",
424 .gpio = RBMAP_GPIO_LED_APCAP,
425 .active_low = 1,
426 },
427 };
428
429 /* RB LHG 5nD gpios */
430 #define RBLHG_GPIO_LED_0 13
431 #define RBLHG_GPIO_LED_1 12
432 #define RBLHG_GPIO_LED_2 4
433 #define RBLHG_GPIO_LED_3 21
434 #define RBLHG_GPIO_LED_4 18
435 #define RBLHG_GPIO_LED_ETH 14
436 #define RBLHG_GPIO_LED_POWER 11
437 #define RBLHG_GPIO_LED_USER 20
438 #define RBLHG_GPIO_BTN_RESET 15
439
440 static struct gpio_led rblhg_leds[] __initdata = {
441 {
442 .name = "rb:green:rssi0",
443 .gpio = RBLHG_GPIO_LED_0,
444 .active_low = 1,
445 }, {
446 .name = "rb:green:rssi1",
447 .gpio = RBLHG_GPIO_LED_1,
448 .active_low = 1,
449 }, {
450 .name = "rb:green:rssi2",
451 .gpio = RBLHG_GPIO_LED_2,
452 .active_low = 1,
453 }, {
454 .name = "rb:green:rssi3",
455 .gpio = RBLHG_GPIO_LED_3,
456 .active_low = 1,
457 }, {
458 .name = "rb:green:rssi4",
459 .gpio = RBLHG_GPIO_LED_4,
460 .active_low = 1,
461 }, {
462 .name = "rb:green:eth",
463 .gpio = RBLHG_GPIO_LED_ETH,
464 .active_low = 1,
465 }, {
466 .name = "rb:green:user",
467 .gpio = RBLHG_GPIO_LED_USER,
468 .active_low = 1,
469 }, {
470 .name = "rb:blue:power",
471 .gpio = RBLHG_GPIO_LED_POWER,
472 .active_low = 0,
473 .default_state = LEDS_GPIO_DEFSTATE_ON,
474 },
475 };
476
477 static struct gpio_keys_button rblhg_gpio_keys[] __initdata = {
478 {
479 .desc = "Reset button",
480 .type = EV_KEY,
481 .code = KEY_RESTART,
482 .debounce_interval = RBSPI_KEYS_DEBOUNCE_INTERVAL,
483 .gpio = RBLHG_GPIO_BTN_RESET,
484 .active_low = 1,
485 },
486 };
487
488
489 static struct gen_74x164_chip_platform_data rbspi_ssr_data = {
490 .base = RBSPI_SSR_GPIO_BASE,
491 };
492
493 /* the spi-ath79 driver can only natively handle CS0. Other CS are bit-banged */
494 static int rbspi_spi_cs_gpios[] = {
495 -ENOENT, /* CS0 is always -ENOENT: natively handled */
496 -ENOENT, /* CS1 can be updated by the code as necessary */
497 };
498
499 static struct ath79_spi_platform_data rbspi_ath79_spi_data = {
500 .bus_num = 0,
501 .cs_gpios = rbspi_spi_cs_gpios,
502 };
503
504 /*
505 * Global spi_board_info: devices that don't have an SSR only have the SPI NOR
506 * flash on bus0 CS0, while devices that have an SSR add it on the same bus CS1
507 */
508 static struct spi_board_info rbspi_spi_info[] = {
509 {
510 .bus_num = 0,
511 .chip_select = 0,
512 .max_speed_hz = 25000000,
513 .modalias = "m25p80",
514 .platform_data = &rbspi_spi_flash_data,
515 }, {
516 .bus_num = 0,
517 .chip_select = 1,
518 .max_speed_hz = 25000000,
519 .modalias = "74x164",
520 .platform_data = &rbspi_ssr_data,
521 }
522 };
523
524 void __init rbspi_wlan_init(u16 id, int wmac_offset)
525 {
526 char *art_buf;
527 u8 wlan_mac[ETH_ALEN];
528
529 art_buf = rb_get_ext_wlan_data(id);
530 if (!art_buf)
531 return;
532
533 ath79_init_mac(wlan_mac, ath79_mac_base, wmac_offset);
534 ath79_register_wmac(art_buf + 0x1000, wlan_mac);
535
536 kfree(art_buf);
537 }
538
539 #define RBSPI_MACH_BUFLEN 64
540 /*
541 * Common platform init routine for all SPI NOR devices.
542 */
543 static int __init rbspi_platform_setup(void)
544 {
545 const struct rb_info *info;
546 char buf[RBSPI_MACH_BUFLEN] = "MikroTik ";
547 char *str;
548 int len = RBSPI_MACH_BUFLEN - strlen(buf) - 1;
549
550 info = rb_init_info((void *)(KSEG1ADDR(AR71XX_SPI_BASE)), 0x20000);
551 if (!info)
552 return -ENODEV;
553
554 if (info->board_name) {
555 str = "RouterBOARD ";
556 if (strncmp(info->board_name, str, strlen(str))) {
557 strncat(buf, str, len);
558 len -= strlen(str);
559 }
560 strncat(buf, info->board_name, len);
561 }
562 else
563 strncat(buf, "UNKNOWN", len);
564
565 mips_set_machine_name(buf);
566
567 /* fix partitions based on flash parsing */
568 rbspi_init_partitions(info);
569
570 return 0;
571 }
572
573 /*
574 * Common peripherals init routine for all SPI NOR devices.
575 * Sets SPI and USB.
576 */
577 static void __init rbspi_peripherals_setup(u32 flags)
578 {
579 unsigned spi_n;
580
581 if (flags & RBSPI_HAS_SSR)
582 spi_n = ARRAY_SIZE(rbspi_spi_info);
583 else
584 spi_n = 1; /* only one device on bus0 */
585
586 rbspi_ath79_spi_data.num_chipselect = spi_n;
587 rbspi_ath79_spi_data.cs_gpios = rbspi_spi_cs_gpios;
588 ath79_register_spi(&rbspi_ath79_spi_data, rbspi_spi_info, spi_n);
589
590 if (flags & RBSPI_HAS_USB)
591 ath79_register_usb();
592
593 if (flags & RBSPI_HAS_PCI)
594 ath79_register_pci();
595 }
596
597 /*
598 * Common network init routine for all SPI NOR devices.
599 * Sets LAN/WAN/WLAN.
600 */
601 static void __init rbspi_network_setup(u32 flags, int gmac1_offset,
602 int wmac0_offset, int wmac1_offset)
603 {
604 /* for QCA953x that will init mdio1_device/data */
605 ath79_register_mdio(0, 0x0);
606 if (flags & RBSPI_HAS_MDIO1)
607 ath79_register_mdio(1, 0x0);
608
609 if (flags & RBSPI_HAS_WAN4) {
610 ath79_setup_ar934x_eth_cfg(0);
611
612 /* set switch to oper mode 1, PHY4 connected to CPU */
613 ath79_switch_data.phy4_mii_en = 1;
614 ath79_switch_data.phy_poll_mask |= BIT(4);
615
616 /* init GMAC0 connected to PHY4 at 100M */
617 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
618 ath79_eth0_data.phy_mask = BIT(4);
619 ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
620 ath79_register_eth(0);
621 } else {
622 /* set the SoC to SW_ONLY_MODE, which connects all PHYs
623 * to the internal switch.
624 * We hijack ath79_setup_ar934x_eth_cfg() to set the switch in
625 * the QCA953x, this works because this configuration bit is
626 * the same as the AR934x. There's no equivalent function for
627 * QCA953x for now. */
628 ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE);
629 }
630
631 /* init GMAC1 */
632 ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, gmac1_offset);
633 ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
634 ath79_register_eth(1);
635
636 if (flags & RBSPI_HAS_WLAN0)
637 rbspi_wlan_init(0, wmac0_offset);
638
639 if (flags & RBSPI_HAS_WLAN1)
640 rbspi_wlan_init(1, wmac1_offset);
641 }
642
643 /*
644 * Init the mAP lite hardware (QCA953x).
645 * The mAP L-2nD (mAP lite) has a single ethernet port, connected to PHY0.
646 * Trying to use GMAC0 in direct mode was unsucessful, so we're
647 * using SW_ONLY_MODE, which connects PHY0 to MAC1 on the internal
648 * switch, which is connected to GMAC1 on the SoC. GMAC0 is unused.
649 */
650 static void __init rbmapl_setup(void)
651 {
652 u32 flags = RBSPI_HAS_WLAN0;
653
654 if (rbspi_platform_setup())
655 return;
656
657 rbspi_peripherals_setup(flags);
658
659 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
660 rbspi_network_setup(flags, 0, 1, 0);
661
662 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbmapl_leds), rbmapl_leds);
663
664 /* mAP lite has a single reset button as gpio 16 */
665 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
666 ARRAY_SIZE(rbspi_gpio_keys_reset16),
667 rbspi_gpio_keys_reset16);
668
669 /* clear internal multiplexing */
670 ath79_gpio_output_select(RBMAPL_GPIO_LED_ETH, AR934X_GPIO_OUT_GPIO);
671 ath79_gpio_output_select(RBMAPL_GPIO_LED_POWER, AR934X_GPIO_OUT_GPIO);
672 }
673
674 /*
675 * Init the hAP lite hardware (QCA953x).
676 * The 941-2nD (hAP lite) has 4 ethernet ports, with port 2-4
677 * being assigned to LAN on the casing, and port 1 being assigned
678 * to "internet" (WAN) on the casing. Port 1 is connected to PHY3.
679 * Since WAN is neither PHY0 nor PHY4, we cannot use GMAC0 with this device.
680 */
681 static void __init rbhapl_setup(void)
682 {
683 u32 flags = RBSPI_HAS_WLAN0;
684
685 if (rbspi_platform_setup())
686 return;
687
688 rbspi_peripherals_setup(flags);
689
690 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 4 */
691 rbspi_network_setup(flags, 0, 4, 0);
692
693 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbhapl_leds), rbhapl_leds);
694
695 /* hAP lite has a single reset button as gpio 16 */
696 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
697 ARRAY_SIZE(rbspi_gpio_keys_reset16),
698 rbspi_gpio_keys_reset16);
699 }
700
701 /*
702 * The hAP, hAP ac lite, hEX lite and hEX PoE lite share the same platform
703 */
704 static void __init rbspi_952_750r2_setup(u32 flags)
705 {
706 if (flags & RBSPI_HAS_SSR)
707 rbspi_spi_cs_gpios[1] = RB952_GPIO_SSR_CS;
708
709 rbspi_peripherals_setup(flags);
710
711 /*
712 * GMAC1 is HW MAC + 1, WLAN0 MAC IS HW MAC + 5 (hAP),
713 * WLAN1 MAC IS HW MAC + 6 (hAP ac lite)
714 */
715 rbspi_network_setup(flags, 1, 5, 6);
716
717 if (flags & RBSPI_HAS_USB)
718 gpio_request_one(RB952_GPIO_USB_POWER,
719 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
720 "USB power");
721
722 if (flags & RBSPI_HAS_POE)
723 gpio_request_one(RB952_GPIO_POE_POWER,
724 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
725 "POE power");
726
727 ath79_register_leds_gpio(-1, ARRAY_SIZE(rb952_leds), rb952_leds);
728
729 /* These devices have a single reset button as gpio 16 */
730 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
731 ARRAY_SIZE(rbspi_gpio_keys_reset16),
732 rbspi_gpio_keys_reset16);
733 }
734
735 /*
736 * Init the hAP (ac lite) hardware (QCA953x).
737 * The 951Ui-2nD (hAP) has 5 ethernet ports, with ports 2-5 being assigned
738 * to LAN on the casing, and port 1 being assigned to "internet" (WAN).
739 * Port 1 is connected to PHY4 (the ports are labelled in reverse physical
740 * number), so the SoC can be set to connect GMAC0 to PHY4 and GMAC1 to the
741 * internal switch for the LAN ports.
742 * The device also has USB, PoE output and an SSR used for LED multiplexing.
743 * The 952Ui-5ac2nD (hAP ac lite) is nearly identical to the hAP, it adds a
744 * QCA9887 5GHz radio via PCI and moves 2.4GHz from WLAN0 to WLAN1.
745 */
746 static void __init rb952_setup(void)
747 {
748 u32 flags = RBSPI_HAS_WAN4 | RBSPI_HAS_USB |
749 RBSPI_HAS_SSR | RBSPI_HAS_POE;
750
751 if (rbspi_platform_setup())
752 return;
753
754 /* differentiate the hAP from the hAP ac lite */
755 if (strstr(mips_get_machine_name(), "952Ui-5ac2nD"))
756 flags |= RBSPI_HAS_WLAN1 | RBSPI_HAS_PCI;
757 else
758 flags |= RBSPI_HAS_WLAN0;
759
760 rbspi_952_750r2_setup(flags);
761 }
762
763 /*
764 * Init the hEX (PoE) lite hardware (QCA953x).
765 * The 750UP r2 (hEX PoE lite) is nearly identical to the hAP, only without
766 * WLAN. The 750 r2 (hEX lite) is nearly identical to the 750UP r2, only
767 * without USB and POE. The 750P Pbr2 (Powerbox) is nearly identical to hEX PoE
768 * lite, only without USB. It shares the same bootloader board identifier.
769 */
770 static void __init rb750upr2_setup(void)
771 {
772 u32 flags = RBSPI_HAS_WAN4 | RBSPI_HAS_SSR;
773
774 if (rbspi_platform_setup())
775 return;
776
777 /* differentiate the hEX lite from the hEX PoE lite */
778 if (strstr(mips_get_machine_name(), "750UP r2"))
779 flags |= RBSPI_HAS_USB | RBSPI_HAS_POE;
780
781 /* differentiate the Powerbox from the hEX lite */
782 else if (strstr(mips_get_machine_name(), "750P r2"))
783 flags |= RBSPI_HAS_POE;
784
785 rbspi_952_750r2_setup(flags);
786 }
787
788 /*
789 * Init the hAP ac / 962UiGS-5HacT2HnT hardware (QCA9558).
790 * The hAP ac has 5 ethernet ports provided by an AR8337 switch. Port 1 is
791 * assigned to WAN, ports 2-5 are assigned to LAN. Port 0 is connected to the
792 * SoC, ports 1-5 of the switch are connected to physical ports 1-5 in order.
793 * The SFP cage is not assigned by default on RouterOS. Extra work is required
794 * to support this interface as it is directly connected to the SoC (eth1).
795 * Wireless is provided by a 2.4GHz radio on the SoC (WLAN1) and a 5GHz radio
796 * attached via PCI (QCA9880). Red and green WLAN LEDs are populated however
797 * they are not attached to GPIOs, extra work is required to support these.
798 * PoE and USB output power control is supported.
799 */
800 static void __init rb962_setup(void)
801 {
802 u32 flags = RBSPI_HAS_USB | RBSPI_HAS_POE | RBSPI_HAS_PCI;
803
804 if (rbspi_platform_setup())
805 return;
806
807 rbspi_peripherals_setup(flags);
808
809 /* Do not call rbspi_network_setup as we have a discrete switch chip */
810 ath79_eth0_pll_data.pll_1000 = 0xae000000;
811 ath79_eth0_pll_data.pll_100 = 0xa0000101;
812 ath79_eth0_pll_data.pll_10 = 0xa0001313;
813
814 ath79_register_mdio(0, 0x0);
815 mdiobus_register_board_info(rb962_mdio0_info,
816 ARRAY_SIZE(rb962_mdio0_info));
817
818 ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
819
820 ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
821 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
822 ath79_eth0_data.phy_mask = BIT(0);
823 ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
824 ath79_register_eth(0);
825
826 /* WLAN1 MAC is HW MAC + 7 */
827 rbspi_wlan_init(1, 7);
828
829 if (flags & RBSPI_HAS_USB)
830 gpio_request_one(RB962_GPIO_USB_POWER,
831 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
832 "USB power");
833
834 /* PoE output GPIO is inverted, set GPIOF_ACTIVE_LOW for consistency */
835 if (flags & RBSPI_HAS_POE)
836 gpio_request_one(RB962_GPIO_POE_POWER,
837 GPIOF_OUT_INIT_HIGH | GPIOF_ACTIVE_LOW |
838 GPIOF_EXPORT_DIR_FIXED,
839 "POE power");
840
841 ath79_register_leds_gpio(-1, ARRAY_SIZE(rb962_leds_gpio),
842 rb962_leds_gpio);
843
844 /* This device has a single reset button as gpio 20 */
845 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
846 ARRAY_SIZE(rbspi_gpio_keys_reset20),
847 rbspi_gpio_keys_reset20);
848 }
849
850 /*
851 * Init the LHG hardware (AR9344).
852 * The LHG 5nD has a single ethernet port connected to PHY0.
853 * Wireless is provided via 5GHz WLAN1.
854 */
855 static void __init rblhg_setup(void)
856 {
857 u32 flags = RBSPI_HAS_WLAN1 | RBSPI_HAS_MDIO1;
858
859 if (rbspi_platform_setup())
860 return;
861
862 rbspi_peripherals_setup(flags);
863
864 /* GMAC1 is HW MAC, WLAN1 MAC is HW MAC + 1 */
865 rbspi_network_setup(flags, 0, 0, 1);
866
867 ath79_register_leds_gpio(-1, ARRAY_SIZE(rblhg_leds), rblhg_leds);
868
869 ath79_register_gpio_keys_polled(-1, RBSPI_KEYS_POLL_INTERVAL,
870 ARRAY_SIZE(rblhg_gpio_keys),
871 rblhg_gpio_keys);
872 }
873
874 /*
875 * Init the wAP hardware (EXPERIMENTAL).
876 * The wAP 2nD has a single ethernet port.
877 */
878 static void __init rbwap_setup(void)
879 {
880 u32 flags = RBSPI_HAS_WLAN0;
881
882 if (rbspi_platform_setup())
883 return;
884
885 rbspi_peripherals_setup(flags);
886
887 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
888 rbspi_network_setup(flags, 0, 1, 0);
889
890 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbwap_leds), rbwap_leds);
891 }
892
893 /*
894 * Init the cAP hardware (EXPERIMENTAL).
895 * The cAP 2nD has a single ethernet port, and a global LED switch.
896 */
897 static void __init rbcap_setup(void)
898 {
899 u32 flags = RBSPI_HAS_WLAN0;
900
901 if (rbspi_platform_setup())
902 return;
903
904 rbspi_peripherals_setup(flags);
905
906 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 1 */
907 rbspi_network_setup(flags, 0, 1, 0);
908
909 gpio_request_one(RBCAP_GPIO_LED_ALL,
910 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
911 "LEDs enable");
912
913 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbcap_leds), rbcap_leds);
914 }
915
916 /*
917 * Init the mAP hardware (EXPERIMENTAL).
918 * The mAP 2nD has two ethernet ports, PoE output and an SSR for LED
919 * multiplexing.
920 */
921 static void __init rbmap_setup(void)
922 {
923 u32 flags = RBSPI_HAS_WLAN0 | RBSPI_HAS_SSR | RBSPI_HAS_POE;
924
925 if (rbspi_platform_setup())
926 return;
927
928 rbspi_spi_cs_gpios[1] = RBMAP_GPIO_SSR_CS;
929 rbspi_peripherals_setup(flags);
930
931 /* GMAC1 is HW MAC, WLAN0 MAC is HW MAC + 2 */
932 rbspi_network_setup(flags, 0, 2, 0);
933
934 if (flags & RBSPI_HAS_POE)
935 gpio_request_one(RBMAP_GPIO_POE_POWER,
936 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
937 "POE power");
938
939 ath79_register_leds_gpio(-1, ARRAY_SIZE(rbmap_leds), rbmap_leds);
940 }
941
942
943 MIPS_MACHINE_NONAME(ATH79_MACH_RB_MAPL, "map-hb", rbmapl_setup);
944 MIPS_MACHINE_NONAME(ATH79_MACH_RB_941, "H951L", rbhapl_setup);
945 MIPS_MACHINE_NONAME(ATH79_MACH_RB_952, "952-hb", rb952_setup);
946 MIPS_MACHINE_NONAME(ATH79_MACH_RB_962, "962", rb962_setup);
947 MIPS_MACHINE_NONAME(ATH79_MACH_RB_750UPR2, "750-hb", rb750upr2_setup);
948 MIPS_MACHINE_NONAME(ATH79_MACH_RB_LHG5, "lhg", rblhg_setup);
949 MIPS_MACHINE_NONAME(ATH79_MACH_RB_WAP, "wap-hb", rbwap_setup);
950 MIPS_MACHINE_NONAME(ATH79_MACH_RB_CAP, "cap-hb", rbcap_setup);
951 MIPS_MACHINE_NONAME(ATH79_MACH_RB_MAP, "map2-hb", rbmap_setup);
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