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[openwrt/openwrt.git] / target / linux / ar71xx / files / drivers / net / ethernet / atheros / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include "ag71xx.h"
15
16 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,2,0)
17 static inline void skb_free_frag(void *data)
18 {
19 put_page(virt_to_head_page(data));
20 }
21 #endif
22
23 #define AG71XX_DEFAULT_MSG_ENABLE \
24 (NETIF_MSG_DRV \
25 | NETIF_MSG_PROBE \
26 | NETIF_MSG_LINK \
27 | NETIF_MSG_TIMER \
28 | NETIF_MSG_IFDOWN \
29 | NETIF_MSG_IFUP \
30 | NETIF_MSG_RX_ERR \
31 | NETIF_MSG_TX_ERR)
32
33 static int ag71xx_msg_level = -1;
34
35 module_param_named(msg_level, ag71xx_msg_level, int, 0);
36 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
37
38 #define ETH_SWITCH_HEADER_LEN 2
39
40 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush);
41
42 static inline unsigned int ag71xx_max_frame_len(unsigned int mtu)
43 {
44 return ETH_SWITCH_HEADER_LEN + ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN;
45 }
46
47 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
48 {
49 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
50 ag->dev->name,
51 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
52 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
53 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
54
55 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
56 ag->dev->name,
57 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
58 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
59 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
60 }
61
62 static void ag71xx_dump_regs(struct ag71xx *ag)
63 {
64 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
65 ag->dev->name,
66 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
67 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
68 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
69 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
70 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
71 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
72 ag->dev->name,
73 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
74 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
75 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
76 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
77 ag->dev->name,
78 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
79 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
80 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
81 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
82 ag->dev->name,
83 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
84 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
85 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
86 }
87
88 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
89 {
90 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
91 ag->dev->name, label, intr,
92 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
93 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
94 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
95 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
96 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
97 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
98 }
99
100 static void ag71xx_ring_free(struct ag71xx_ring *ring)
101 {
102 int ring_size = BIT(ring->order);
103 kfree(ring->buf);
104
105 if (ring->descs_cpu)
106 dma_free_coherent(NULL, ring_size * AG71XX_DESC_SIZE,
107 ring->descs_cpu, ring->descs_dma);
108 }
109
110 static int ag71xx_ring_alloc(struct ag71xx_ring *ring)
111 {
112 int ring_size = BIT(ring->order);
113 int err;
114
115 ring->descs_cpu = dma_alloc_coherent(NULL, ring_size * AG71XX_DESC_SIZE,
116 &ring->descs_dma, GFP_ATOMIC);
117 if (!ring->descs_cpu) {
118 err = -ENOMEM;
119 goto err;
120 }
121
122
123 ring->buf = kzalloc(ring_size * sizeof(*ring->buf), GFP_KERNEL);
124 if (!ring->buf) {
125 err = -ENOMEM;
126 goto err;
127 }
128
129 return 0;
130
131 err:
132 return err;
133 }
134
135 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
136 {
137 struct ag71xx_ring *ring = &ag->tx_ring;
138 struct net_device *dev = ag->dev;
139 int ring_mask = BIT(ring->order) - 1;
140 u32 bytes_compl = 0, pkts_compl = 0;
141
142 while (ring->curr != ring->dirty) {
143 struct ag71xx_desc *desc;
144 u32 i = ring->dirty & ring_mask;
145
146 desc = ag71xx_ring_desc(ring, i);
147 if (!ag71xx_desc_empty(desc)) {
148 desc->ctrl = 0;
149 dev->stats.tx_errors++;
150 }
151
152 if (ring->buf[i].skb) {
153 bytes_compl += ring->buf[i].len;
154 pkts_compl++;
155 dev_kfree_skb_any(ring->buf[i].skb);
156 }
157 ring->buf[i].skb = NULL;
158 ring->dirty++;
159 }
160
161 /* flush descriptors */
162 wmb();
163
164 netdev_completed_queue(dev, pkts_compl, bytes_compl);
165 }
166
167 static void ag71xx_ring_tx_init(struct ag71xx *ag)
168 {
169 struct ag71xx_ring *ring = &ag->tx_ring;
170 int ring_size = BIT(ring->order);
171 int ring_mask = ring_size - 1;
172 int i;
173
174 for (i = 0; i < ring_size; i++) {
175 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
176
177 desc->next = (u32) (ring->descs_dma +
178 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
179
180 desc->ctrl = DESC_EMPTY;
181 ring->buf[i].skb = NULL;
182 }
183
184 /* flush descriptors */
185 wmb();
186
187 ring->curr = 0;
188 ring->dirty = 0;
189 netdev_reset_queue(ag->dev);
190 }
191
192 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
193 {
194 struct ag71xx_ring *ring = &ag->rx_ring;
195 int ring_size = BIT(ring->order);
196 int i;
197
198 if (!ring->buf)
199 return;
200
201 for (i = 0; i < ring_size; i++)
202 if (ring->buf[i].rx_buf) {
203 dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
204 ag->rx_buf_size, DMA_FROM_DEVICE);
205 skb_free_frag(ring->buf[i].rx_buf);
206 }
207 }
208
209 static int ag71xx_buffer_offset(struct ag71xx *ag)
210 {
211 int offset = NET_SKB_PAD;
212
213 /*
214 * On AR71xx/AR91xx packets must be 4-byte aligned.
215 *
216 * When using builtin AR8216 support, hardware adds a 2-byte header,
217 * so we don't need any extra alignment in that case.
218 */
219 if (!ag71xx_get_pdata(ag)->is_ar724x || ag71xx_has_ar8216(ag))
220 return offset;
221
222 return offset + NET_IP_ALIGN;
223 }
224
225 static int ag71xx_buffer_size(struct ag71xx *ag)
226 {
227 return ag->rx_buf_size +
228 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
229 }
230
231 static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf,
232 int offset,
233 void *(*alloc)(unsigned int size))
234 {
235 struct ag71xx_ring *ring = &ag->rx_ring;
236 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]);
237 void *data;
238
239 data = alloc(ag71xx_buffer_size(ag));
240 if (!data)
241 return false;
242
243 buf->rx_buf = data;
244 buf->dma_addr = dma_map_single(&ag->dev->dev, data, ag->rx_buf_size,
245 DMA_FROM_DEVICE);
246 desc->data = (u32) buf->dma_addr + offset;
247 return true;
248 }
249
250 static int ag71xx_ring_rx_init(struct ag71xx *ag)
251 {
252 struct ag71xx_ring *ring = &ag->rx_ring;
253 int ring_size = BIT(ring->order);
254 int ring_mask = BIT(ring->order) - 1;
255 unsigned int i;
256 int ret;
257 int offset = ag71xx_buffer_offset(ag);
258
259 ret = 0;
260 for (i = 0; i < ring_size; i++) {
261 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
262
263 desc->next = (u32) (ring->descs_dma +
264 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
265
266 DBG("ag71xx: RX desc at %p, next is %08x\n",
267 desc, desc->next);
268 }
269
270 for (i = 0; i < ring_size; i++) {
271 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
272
273 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], offset,
274 netdev_alloc_frag)) {
275 ret = -ENOMEM;
276 break;
277 }
278
279 desc->ctrl = DESC_EMPTY;
280 }
281
282 /* flush descriptors */
283 wmb();
284
285 ring->curr = 0;
286 ring->dirty = 0;
287
288 return ret;
289 }
290
291 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
292 {
293 struct ag71xx_ring *ring = &ag->rx_ring;
294 int ring_mask = BIT(ring->order) - 1;
295 unsigned int count;
296 int offset = ag71xx_buffer_offset(ag);
297
298 count = 0;
299 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
300 struct ag71xx_desc *desc;
301 unsigned int i;
302
303 i = ring->dirty & ring_mask;
304 desc = ag71xx_ring_desc(ring, i);
305
306 if (!ring->buf[i].rx_buf &&
307 !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset,
308 napi_alloc_frag))
309 break;
310
311 desc->ctrl = DESC_EMPTY;
312 count++;
313 }
314
315 /* flush descriptors */
316 wmb();
317
318 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
319
320 return count;
321 }
322
323 static int ag71xx_rings_init(struct ag71xx *ag)
324 {
325 int ret;
326
327 ret = ag71xx_ring_alloc(&ag->tx_ring);
328 if (ret)
329 return ret;
330
331 ag71xx_ring_tx_init(ag);
332
333 ret = ag71xx_ring_alloc(&ag->rx_ring);
334 if (ret)
335 return ret;
336
337 ret = ag71xx_ring_rx_init(ag);
338 return ret;
339 }
340
341 static void ag71xx_rings_cleanup(struct ag71xx *ag)
342 {
343 ag71xx_ring_rx_clean(ag);
344 ag71xx_ring_free(&ag->rx_ring);
345
346 ag71xx_ring_tx_clean(ag);
347 netdev_reset_queue(ag->dev);
348 ag71xx_ring_free(&ag->tx_ring);
349 }
350
351 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
352 {
353 switch (ag->speed) {
354 case SPEED_1000:
355 return "1000";
356 case SPEED_100:
357 return "100";
358 case SPEED_10:
359 return "10";
360 }
361
362 return "?";
363 }
364
365 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
366 {
367 u32 t;
368
369 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
370 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
371
372 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
373
374 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
375 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
376 }
377
378 static void ag71xx_dma_reset(struct ag71xx *ag)
379 {
380 u32 val;
381 int i;
382
383 ag71xx_dump_dma_regs(ag);
384
385 /* stop RX and TX */
386 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
387 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
388
389 /*
390 * give the hardware some time to really stop all rx/tx activity
391 * clearing the descriptors too early causes random memory corruption
392 */
393 mdelay(1);
394
395 /* clear descriptor addresses */
396 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
397 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
398
399 /* clear pending RX/TX interrupts */
400 for (i = 0; i < 256; i++) {
401 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
402 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
403 }
404
405 /* clear pending errors */
406 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
407 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
408
409 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
410 if (val)
411 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
412 ag->dev->name, val);
413
414 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
415
416 /* mask out reserved bits */
417 val &= ~0xff000000;
418
419 if (val)
420 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
421 ag->dev->name, val);
422
423 ag71xx_dump_dma_regs(ag);
424 }
425
426 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
427 MAC_CFG1_SRX | MAC_CFG1_STX)
428
429 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
430
431 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
432 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
433 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
434 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
435 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
436 FIFO_CFG4_VT)
437
438 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
439 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
440 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
441 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
442 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
443 FIFO_CFG5_17 | FIFO_CFG5_SF)
444
445 static void ag71xx_hw_stop(struct ag71xx *ag)
446 {
447 /* disable all interrupts and stop the rx/tx engine */
448 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
449 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
450 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
451 }
452
453 static void ag71xx_hw_setup(struct ag71xx *ag)
454 {
455 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
456 u32 init = MAC_CFG1_INIT;
457
458 /* setup MAC configuration registers */
459 if (pdata->use_flow_control)
460 init |= MAC_CFG1_TFC | MAC_CFG1_RFC;
461 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, init);
462
463 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
464 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
465
466 /* setup max frame length to zero */
467 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);
468
469 /* setup FIFO configuration registers */
470 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
471 if (pdata->is_ar724x) {
472 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
473 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
474 } else {
475 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
476 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
477 }
478 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
479 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
480 }
481
482 static void ag71xx_hw_init(struct ag71xx *ag)
483 {
484 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
485 u32 reset_mask = pdata->reset_bit;
486
487 ag71xx_hw_stop(ag);
488
489 if (pdata->is_ar724x) {
490 u32 reset_phy = reset_mask;
491
492 reset_phy &= AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY;
493 reset_mask &= ~(AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY);
494
495 ath79_device_reset_set(reset_phy);
496 msleep(50);
497 ath79_device_reset_clear(reset_phy);
498 msleep(200);
499 }
500
501 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
502 udelay(20);
503
504 ath79_device_reset_set(reset_mask);
505 msleep(100);
506 ath79_device_reset_clear(reset_mask);
507 msleep(200);
508
509 ag71xx_hw_setup(ag);
510
511 ag71xx_dma_reset(ag);
512 }
513
514 static void ag71xx_fast_reset(struct ag71xx *ag)
515 {
516 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
517 struct net_device *dev = ag->dev;
518 u32 reset_mask = pdata->reset_bit;
519 u32 rx_ds;
520 u32 mii_reg;
521
522 reset_mask &= AR71XX_RESET_GE0_MAC | AR71XX_RESET_GE1_MAC;
523
524 ag71xx_hw_stop(ag);
525 wmb();
526
527 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
528 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
529
530 ag71xx_tx_packets(ag, true);
531
532 ath79_device_reset_set(reset_mask);
533 udelay(10);
534 ath79_device_reset_clear(reset_mask);
535 udelay(10);
536
537 ag71xx_dma_reset(ag);
538 ag71xx_hw_setup(ag);
539 ag->tx_ring.curr = 0;
540 ag->tx_ring.dirty = 0;
541 netdev_reset_queue(ag->dev);
542
543 /* setup max frame length */
544 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
545 ag71xx_max_frame_len(ag->dev->mtu));
546
547 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
548 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
549 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
550
551 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
552 }
553
554 static void ag71xx_hw_start(struct ag71xx *ag)
555 {
556 /* start RX engine */
557 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
558
559 /* enable interrupts */
560 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
561
562 netif_wake_queue(ag->dev);
563 }
564
565 static void
566 __ag71xx_link_adjust(struct ag71xx *ag, bool update)
567 {
568 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
569 u32 cfg2;
570 u32 ifctl;
571 u32 fifo5;
572 u32 fifo3;
573
574 if (!ag->link && update) {
575 ag71xx_hw_stop(ag);
576 netif_carrier_off(ag->dev);
577 if (netif_msg_link(ag))
578 pr_info("%s: link down\n", ag->dev->name);
579 return;
580 }
581
582 if (pdata->is_ar724x)
583 ag71xx_fast_reset(ag);
584
585 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
586 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
587 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
588
589 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
590 ifctl &= ~(MAC_IFCTL_SPEED);
591
592 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
593 fifo5 &= ~FIFO_CFG5_BM;
594
595 switch (ag->speed) {
596 case SPEED_1000:
597 cfg2 |= MAC_CFG2_IF_1000;
598 fifo5 |= FIFO_CFG5_BM;
599 break;
600 case SPEED_100:
601 cfg2 |= MAC_CFG2_IF_10_100;
602 ifctl |= MAC_IFCTL_SPEED;
603 break;
604 case SPEED_10:
605 cfg2 |= MAC_CFG2_IF_10_100;
606 break;
607 default:
608 BUG();
609 return;
610 }
611
612 if (pdata->is_ar91xx)
613 fifo3 = 0x00780fff;
614 else if (pdata->is_ar724x)
615 fifo3 = pdata->fifo_cfg3;
616 else
617 fifo3 = 0x008001ff;
618
619 if (ag->tx_ring.desc_split) {
620 fifo3 &= 0xffff;
621 fifo3 |= ((2048 - ag->tx_ring.desc_split) / 4) << 16;
622 }
623
624 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, fifo3);
625
626 if (update && pdata->set_speed)
627 pdata->set_speed(ag->speed);
628
629 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
630 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
631 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
632
633 if (pdata->disable_inline_checksum_engine) {
634 /*
635 * The rx ring buffer can stall on small packets on QCA953x and
636 * QCA956x. Disabling the inline checksum engine fixes the stall.
637 * The wr, rr functions cannot be used since this hidden register
638 * is outside of the normal ag71xx register block.
639 */
640 void __iomem *dam = ioremap_nocache(0xb90001bc, 0x4);
641 if (dam) {
642 __raw_writel(__raw_readl(dam) & ~BIT(27), dam);
643 (void)__raw_readl(dam);
644 iounmap(dam);
645 }
646 }
647
648 ag71xx_hw_start(ag);
649
650 netif_carrier_on(ag->dev);
651 if (update && netif_msg_link(ag))
652 pr_info("%s: link up (%sMbps/%s duplex)\n",
653 ag->dev->name,
654 ag71xx_speed_str(ag),
655 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
656
657 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
658 ag->dev->name,
659 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
660 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
661 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
662
663 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
664 ag->dev->name,
665 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
666 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
667 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
668
669 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n",
670 ag->dev->name,
671 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
672 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL));
673 }
674
675 void ag71xx_link_adjust(struct ag71xx *ag)
676 {
677 __ag71xx_link_adjust(ag, true);
678 }
679
680 static int ag71xx_hw_enable(struct ag71xx *ag)
681 {
682 int ret;
683
684 ret = ag71xx_rings_init(ag);
685 if (ret)
686 return ret;
687
688 napi_enable(&ag->napi);
689 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
690 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
691 netif_start_queue(ag->dev);
692
693 return 0;
694 }
695
696 static void ag71xx_hw_disable(struct ag71xx *ag)
697 {
698 unsigned long flags;
699
700 spin_lock_irqsave(&ag->lock, flags);
701
702 netif_stop_queue(ag->dev);
703
704 ag71xx_hw_stop(ag);
705 ag71xx_dma_reset(ag);
706
707 napi_disable(&ag->napi);
708 del_timer_sync(&ag->oom_timer);
709
710 spin_unlock_irqrestore(&ag->lock, flags);
711
712 ag71xx_rings_cleanup(ag);
713 }
714
715 static int ag71xx_open(struct net_device *dev)
716 {
717 struct ag71xx *ag = netdev_priv(dev);
718 unsigned int max_frame_len;
719 int ret;
720
721 netif_carrier_off(dev);
722 max_frame_len = ag71xx_max_frame_len(dev->mtu);
723 ag->rx_buf_size = SKB_DATA_ALIGN(max_frame_len + NET_SKB_PAD + NET_IP_ALIGN);
724
725 /* setup max frame length */
726 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);
727 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
728
729 ret = ag71xx_hw_enable(ag);
730 if (ret)
731 goto err;
732
733 ag71xx_phy_start(ag);
734
735 return 0;
736
737 err:
738 ag71xx_rings_cleanup(ag);
739 return ret;
740 }
741
742 static int ag71xx_stop(struct net_device *dev)
743 {
744 struct ag71xx *ag = netdev_priv(dev);
745
746 netif_carrier_off(dev);
747 ag71xx_phy_stop(ag);
748 ag71xx_hw_disable(ag);
749
750 return 0;
751 }
752
753 static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len)
754 {
755 int i;
756 struct ag71xx_desc *desc;
757 int ring_mask = BIT(ring->order) - 1;
758 int ndesc = 0;
759 int split = ring->desc_split;
760
761 if (!split)
762 split = len;
763
764 while (len > 0) {
765 unsigned int cur_len = len;
766
767 i = (ring->curr + ndesc) & ring_mask;
768 desc = ag71xx_ring_desc(ring, i);
769
770 if (!ag71xx_desc_empty(desc))
771 return -1;
772
773 if (cur_len > split) {
774 cur_len = split;
775
776 /*
777 * TX will hang if DMA transfers <= 4 bytes,
778 * make sure next segment is more than 4 bytes long.
779 */
780 if (len <= split + 4)
781 cur_len -= 4;
782 }
783
784 desc->data = addr;
785 addr += cur_len;
786 len -= cur_len;
787
788 if (len > 0)
789 cur_len |= DESC_MORE;
790
791 /* prevent early tx attempt of this descriptor */
792 if (!ndesc)
793 cur_len |= DESC_EMPTY;
794
795 desc->ctrl = cur_len;
796 ndesc++;
797 }
798
799 return ndesc;
800 }
801
802 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
803 struct net_device *dev)
804 {
805 struct ag71xx *ag = netdev_priv(dev);
806 struct ag71xx_ring *ring = &ag->tx_ring;
807 int ring_mask = BIT(ring->order) - 1;
808 int ring_size = BIT(ring->order);
809 struct ag71xx_desc *desc;
810 dma_addr_t dma_addr;
811 int i, n, ring_min;
812
813 if (ag71xx_has_ar8216(ag))
814 ag71xx_add_ar8216_header(ag, skb);
815
816 if (skb->len <= 4) {
817 DBG("%s: packet len is too small\n", ag->dev->name);
818 goto err_drop;
819 }
820
821 dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
822 DMA_TO_DEVICE);
823
824 i = ring->curr & ring_mask;
825 desc = ag71xx_ring_desc(ring, i);
826
827 /* setup descriptor fields */
828 n = ag71xx_fill_dma_desc(ring, (u32) dma_addr, skb->len & ag->desc_pktlen_mask);
829 if (n < 0)
830 goto err_drop_unmap;
831
832 i = (ring->curr + n - 1) & ring_mask;
833 ring->buf[i].len = skb->len;
834 ring->buf[i].skb = skb;
835 ring->buf[i].timestamp = jiffies;
836
837 netdev_sent_queue(dev, skb->len);
838
839 skb_tx_timestamp(skb);
840
841 desc->ctrl &= ~DESC_EMPTY;
842 ring->curr += n;
843
844 /* flush descriptor */
845 wmb();
846
847 ring_min = 2;
848 if (ring->desc_split)
849 ring_min *= AG71XX_TX_RING_DS_PER_PKT;
850
851 if (ring->curr - ring->dirty >= ring_size - ring_min) {
852 DBG("%s: tx queue full\n", dev->name);
853 netif_stop_queue(dev);
854 }
855
856 DBG("%s: packet injected into TX queue\n", ag->dev->name);
857
858 /* enable TX engine */
859 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
860
861 return NETDEV_TX_OK;
862
863 err_drop_unmap:
864 dma_unmap_single(&dev->dev, dma_addr, skb->len, DMA_TO_DEVICE);
865
866 err_drop:
867 dev->stats.tx_dropped++;
868
869 dev_kfree_skb(skb);
870 return NETDEV_TX_OK;
871 }
872
873 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
874 {
875 struct ag71xx *ag = netdev_priv(dev);
876 int ret;
877
878 switch (cmd) {
879 case SIOCETHTOOL:
880 if (ag->phy_dev == NULL)
881 break;
882
883 spin_lock_irq(&ag->lock);
884 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
885 spin_unlock_irq(&ag->lock);
886 return ret;
887
888 case SIOCSIFHWADDR:
889 if (copy_from_user
890 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
891 return -EFAULT;
892 return 0;
893
894 case SIOCGIFHWADDR:
895 if (copy_to_user
896 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
897 return -EFAULT;
898 return 0;
899
900 case SIOCGMIIPHY:
901 case SIOCGMIIREG:
902 case SIOCSMIIREG:
903 if (ag->phy_dev == NULL)
904 break;
905
906 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
907
908 default:
909 break;
910 }
911
912 return -EOPNOTSUPP;
913 }
914
915 static void ag71xx_oom_timer_handler(unsigned long data)
916 {
917 struct net_device *dev = (struct net_device *) data;
918 struct ag71xx *ag = netdev_priv(dev);
919
920 napi_schedule(&ag->napi);
921 }
922
923 static void ag71xx_tx_timeout(struct net_device *dev)
924 {
925 struct ag71xx *ag = netdev_priv(dev);
926
927 if (netif_msg_tx_err(ag))
928 pr_info("%s: tx timeout\n", ag->dev->name);
929
930 schedule_delayed_work(&ag->restart_work, 1);
931 }
932
933 static void ag71xx_restart_work_func(struct work_struct *work)
934 {
935 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work.work);
936
937 rtnl_lock();
938 ag71xx_hw_disable(ag);
939 ag71xx_hw_enable(ag);
940 if (ag->link)
941 __ag71xx_link_adjust(ag, false);
942 rtnl_unlock();
943 }
944
945 static bool ag71xx_check_dma_stuck(struct ag71xx *ag, unsigned long timestamp)
946 {
947 u32 rx_sm, tx_sm, rx_fd;
948
949 if (likely(time_before(jiffies, timestamp + HZ/10)))
950 return false;
951
952 if (!netif_carrier_ok(ag->dev))
953 return false;
954
955 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
956 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
957 return true;
958
959 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
960 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
961 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
962 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
963 return true;
964
965 return false;
966 }
967
968 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush)
969 {
970 struct ag71xx_ring *ring = &ag->tx_ring;
971 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
972 bool dma_stuck = false;
973 int ring_mask = BIT(ring->order) - 1;
974 int ring_size = BIT(ring->order);
975 int sent = 0;
976 int bytes_compl = 0;
977 int n = 0;
978
979 DBG("%s: processing TX ring\n", ag->dev->name);
980
981 while (ring->dirty + n != ring->curr) {
982 unsigned int i = (ring->dirty + n) & ring_mask;
983 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
984 struct sk_buff *skb = ring->buf[i].skb;
985
986 if (!flush && !ag71xx_desc_empty(desc)) {
987 if (pdata->is_ar724x &&
988 ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp)) {
989 schedule_delayed_work(&ag->restart_work, HZ / 2);
990 dma_stuck = true;
991 }
992 break;
993 }
994
995 if (flush)
996 desc->ctrl |= DESC_EMPTY;
997
998 n++;
999 if (!skb)
1000 continue;
1001
1002 dev_kfree_skb_any(skb);
1003 ring->buf[i].skb = NULL;
1004
1005 bytes_compl += ring->buf[i].len;
1006
1007 sent++;
1008 ring->dirty += n;
1009
1010 while (n > 0) {
1011 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
1012 n--;
1013 }
1014 }
1015
1016 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
1017
1018 ag->dev->stats.tx_bytes += bytes_compl;
1019 ag->dev->stats.tx_packets += sent;
1020
1021 if (!sent)
1022 return 0;
1023
1024 netdev_completed_queue(ag->dev, sent, bytes_compl);
1025 if ((ring->curr - ring->dirty) < (ring_size * 3) / 4)
1026 netif_wake_queue(ag->dev);
1027
1028 if (!dma_stuck)
1029 cancel_delayed_work(&ag->restart_work);
1030
1031 return sent;
1032 }
1033
1034 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
1035 {
1036 struct net_device *dev = ag->dev;
1037 struct ag71xx_ring *ring = &ag->rx_ring;
1038 int offset = ag71xx_buffer_offset(ag);
1039 unsigned int pktlen_mask = ag->desc_pktlen_mask;
1040 int ring_mask = BIT(ring->order) - 1;
1041 int ring_size = BIT(ring->order);
1042 struct sk_buff_head queue;
1043 struct sk_buff *skb;
1044 int done = 0;
1045
1046 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
1047 dev->name, limit, ring->curr, ring->dirty);
1048
1049 skb_queue_head_init(&queue);
1050
1051 while (done < limit) {
1052 unsigned int i = ring->curr & ring_mask;
1053 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1054 int pktlen;
1055 int err = 0;
1056
1057 if (ag71xx_desc_empty(desc))
1058 break;
1059
1060 if ((ring->dirty + ring_size) == ring->curr) {
1061 ag71xx_assert(0);
1062 break;
1063 }
1064
1065 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
1066
1067 pktlen = desc->ctrl & pktlen_mask;
1068 pktlen -= ETH_FCS_LEN;
1069
1070 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
1071 ag->rx_buf_size, DMA_FROM_DEVICE);
1072
1073 dev->stats.rx_packets++;
1074 dev->stats.rx_bytes += pktlen;
1075
1076 skb = build_skb(ring->buf[i].rx_buf, ag71xx_buffer_size(ag));
1077 if (!skb) {
1078 skb_free_frag(ring->buf[i].rx_buf);
1079 goto next;
1080 }
1081
1082 skb_reserve(skb, offset);
1083 skb_put(skb, pktlen);
1084
1085 if (ag71xx_has_ar8216(ag))
1086 err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
1087
1088 if (err) {
1089 dev->stats.rx_dropped++;
1090 kfree_skb(skb);
1091 } else {
1092 skb->dev = dev;
1093 skb->ip_summed = CHECKSUM_NONE;
1094 __skb_queue_tail(&queue, skb);
1095 }
1096
1097 next:
1098 ring->buf[i].rx_buf = NULL;
1099 done++;
1100
1101 ring->curr++;
1102 }
1103
1104 ag71xx_ring_rx_refill(ag);
1105
1106 while ((skb = __skb_dequeue(&queue)) != NULL) {
1107 skb->protocol = eth_type_trans(skb, dev);
1108 netif_receive_skb(skb);
1109 }
1110
1111 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
1112 dev->name, ring->curr, ring->dirty, done);
1113
1114 return done;
1115 }
1116
1117 static int ag71xx_poll(struct napi_struct *napi, int limit)
1118 {
1119 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
1120 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
1121 struct net_device *dev = ag->dev;
1122 struct ag71xx_ring *rx_ring = &ag->rx_ring;
1123 int rx_ring_size = BIT(rx_ring->order);
1124 unsigned long flags;
1125 u32 status;
1126 int tx_done;
1127 int rx_done;
1128
1129 pdata->ddr_flush();
1130 tx_done = ag71xx_tx_packets(ag, false);
1131
1132 DBG("%s: processing RX ring\n", dev->name);
1133 rx_done = ag71xx_rx_packets(ag, limit);
1134
1135 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
1136
1137 if (rx_ring->buf[rx_ring->dirty % rx_ring_size].rx_buf == NULL)
1138 goto oom;
1139
1140 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
1141 if (unlikely(status & RX_STATUS_OF)) {
1142 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
1143 dev->stats.rx_fifo_errors++;
1144
1145 /* restart RX */
1146 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
1147 }
1148
1149 if (rx_done < limit) {
1150 if (status & RX_STATUS_PR)
1151 goto more;
1152
1153 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
1154 if (status & TX_STATUS_PS)
1155 goto more;
1156
1157 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
1158 dev->name, rx_done, tx_done, limit);
1159
1160 napi_complete(napi);
1161
1162 /* enable interrupts */
1163 spin_lock_irqsave(&ag->lock, flags);
1164 ag71xx_int_enable(ag, AG71XX_INT_POLL);
1165 spin_unlock_irqrestore(&ag->lock, flags);
1166 return rx_done;
1167 }
1168
1169 more:
1170 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
1171 dev->name, rx_done, tx_done, limit);
1172 return limit;
1173
1174 oom:
1175 if (netif_msg_rx_err(ag))
1176 pr_info("%s: out of memory\n", dev->name);
1177
1178 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
1179 napi_complete(napi);
1180 return 0;
1181 }
1182
1183 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
1184 {
1185 struct net_device *dev = dev_id;
1186 struct ag71xx *ag = netdev_priv(dev);
1187 u32 status;
1188
1189 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1190 ag71xx_dump_intr(ag, "raw", status);
1191
1192 if (unlikely(!status))
1193 return IRQ_NONE;
1194
1195 if (unlikely(status & AG71XX_INT_ERR)) {
1196 if (status & AG71XX_INT_TX_BE) {
1197 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1198 dev_err(&dev->dev, "TX BUS error\n");
1199 }
1200 if (status & AG71XX_INT_RX_BE) {
1201 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1202 dev_err(&dev->dev, "RX BUS error\n");
1203 }
1204 }
1205
1206 if (likely(status & AG71XX_INT_POLL)) {
1207 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1208 DBG("%s: enable polling mode\n", dev->name);
1209 napi_schedule(&ag->napi);
1210 }
1211
1212 ag71xx_debugfs_update_int_stats(ag, status);
1213
1214 return IRQ_HANDLED;
1215 }
1216
1217 #ifdef CONFIG_NET_POLL_CONTROLLER
1218 /*
1219 * Polling 'interrupt' - used by things like netconsole to send skbs
1220 * without having to re-enable interrupts. It's not called while
1221 * the interrupt routine is executing.
1222 */
1223 static void ag71xx_netpoll(struct net_device *dev)
1224 {
1225 disable_irq(dev->irq);
1226 ag71xx_interrupt(dev->irq, dev);
1227 enable_irq(dev->irq);
1228 }
1229 #endif
1230
1231 static int ag71xx_change_mtu(struct net_device *dev, int new_mtu)
1232 {
1233 struct ag71xx *ag = netdev_priv(dev);
1234 unsigned int max_frame_len;
1235
1236 max_frame_len = ag71xx_max_frame_len(new_mtu);
1237 if (new_mtu < 68 || max_frame_len > ag->max_frame_len)
1238 return -EINVAL;
1239
1240 if (netif_running(dev))
1241 return -EBUSY;
1242
1243 dev->mtu = new_mtu;
1244 return 0;
1245 }
1246
1247 static const struct net_device_ops ag71xx_netdev_ops = {
1248 .ndo_open = ag71xx_open,
1249 .ndo_stop = ag71xx_stop,
1250 .ndo_start_xmit = ag71xx_hard_start_xmit,
1251 .ndo_do_ioctl = ag71xx_do_ioctl,
1252 .ndo_tx_timeout = ag71xx_tx_timeout,
1253 .ndo_change_mtu = ag71xx_change_mtu,
1254 .ndo_set_mac_address = eth_mac_addr,
1255 .ndo_validate_addr = eth_validate_addr,
1256 #ifdef CONFIG_NET_POLL_CONTROLLER
1257 .ndo_poll_controller = ag71xx_netpoll,
1258 #endif
1259 };
1260
1261 static const char *ag71xx_get_phy_if_mode_name(phy_interface_t mode)
1262 {
1263 switch (mode) {
1264 case PHY_INTERFACE_MODE_MII:
1265 return "MII";
1266 case PHY_INTERFACE_MODE_GMII:
1267 return "GMII";
1268 case PHY_INTERFACE_MODE_RMII:
1269 return "RMII";
1270 case PHY_INTERFACE_MODE_RGMII:
1271 return "RGMII";
1272 case PHY_INTERFACE_MODE_SGMII:
1273 return "SGMII";
1274 default:
1275 break;
1276 }
1277
1278 return "unknown";
1279 }
1280
1281
1282 static int ag71xx_probe(struct platform_device *pdev)
1283 {
1284 struct net_device *dev;
1285 struct resource *res;
1286 struct ag71xx *ag;
1287 struct ag71xx_platform_data *pdata;
1288 int tx_size, err;
1289
1290 pdata = pdev->dev.platform_data;
1291 if (!pdata) {
1292 dev_err(&pdev->dev, "no platform data specified\n");
1293 err = -ENXIO;
1294 goto err_out;
1295 }
1296
1297 if (pdata->mii_bus_dev == NULL && pdata->phy_mask) {
1298 dev_err(&pdev->dev, "no MII bus device specified\n");
1299 err = -EINVAL;
1300 goto err_out;
1301 }
1302
1303 dev = alloc_etherdev(sizeof(*ag));
1304 if (!dev) {
1305 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1306 err = -ENOMEM;
1307 goto err_out;
1308 }
1309
1310 if (!pdata->max_frame_len || !pdata->desc_pktlen_mask)
1311 return -EINVAL;
1312
1313 SET_NETDEV_DEV(dev, &pdev->dev);
1314
1315 ag = netdev_priv(dev);
1316 ag->pdev = pdev;
1317 ag->dev = dev;
1318 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1319 AG71XX_DEFAULT_MSG_ENABLE);
1320 spin_lock_init(&ag->lock);
1321
1322 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
1323 if (!res) {
1324 dev_err(&pdev->dev, "no mac_base resource found\n");
1325 err = -ENXIO;
1326 goto err_out;
1327 }
1328
1329 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
1330 if (!ag->mac_base) {
1331 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
1332 err = -ENOMEM;
1333 goto err_free_dev;
1334 }
1335
1336 dev->irq = platform_get_irq(pdev, 0);
1337 err = request_irq(dev->irq, ag71xx_interrupt,
1338 0x0,
1339 dev->name, dev);
1340 if (err) {
1341 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1342 goto err_unmap_base;
1343 }
1344
1345 dev->base_addr = (unsigned long)ag->mac_base;
1346 dev->netdev_ops = &ag71xx_netdev_ops;
1347 dev->ethtool_ops = &ag71xx_ethtool_ops;
1348
1349 INIT_DELAYED_WORK(&ag->restart_work, ag71xx_restart_work_func);
1350
1351 init_timer(&ag->oom_timer);
1352 ag->oom_timer.data = (unsigned long) dev;
1353 ag->oom_timer.function = ag71xx_oom_timer_handler;
1354
1355 tx_size = AG71XX_TX_RING_SIZE_DEFAULT;
1356 ag->rx_ring.order = ag71xx_ring_size_order(AG71XX_RX_RING_SIZE_DEFAULT);
1357
1358 ag->max_frame_len = pdata->max_frame_len;
1359 ag->desc_pktlen_mask = pdata->desc_pktlen_mask;
1360
1361 if (!pdata->is_ar724x && !pdata->is_ar91xx) {
1362 ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT;
1363 tx_size *= AG71XX_TX_RING_DS_PER_PKT;
1364 }
1365 ag->tx_ring.order = ag71xx_ring_size_order(tx_size);
1366
1367 ag->stop_desc = dma_alloc_coherent(NULL,
1368 sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL);
1369
1370 if (!ag->stop_desc)
1371 goto err_free_irq;
1372
1373 ag->stop_desc->data = 0;
1374 ag->stop_desc->ctrl = 0;
1375 ag->stop_desc->next = (u32) ag->stop_desc_dma;
1376
1377 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1378
1379 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1380
1381 ag71xx_dump_regs(ag);
1382
1383 ag71xx_hw_init(ag);
1384
1385 ag71xx_dump_regs(ag);
1386
1387 err = ag71xx_phy_connect(ag);
1388 if (err)
1389 goto err_free_desc;
1390
1391 err = ag71xx_debugfs_init(ag);
1392 if (err)
1393 goto err_phy_disconnect;
1394
1395 platform_set_drvdata(pdev, dev);
1396
1397 err = register_netdev(dev);
1398 if (err) {
1399 dev_err(&pdev->dev, "unable to register net device\n");
1400 goto err_debugfs_exit;
1401 }
1402
1403 pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n",
1404 dev->name, dev->base_addr, dev->irq,
1405 ag71xx_get_phy_if_mode_name(pdata->phy_if_mode));
1406
1407 return 0;
1408
1409 err_debugfs_exit:
1410 ag71xx_debugfs_exit(ag);
1411 err_phy_disconnect:
1412 ag71xx_phy_disconnect(ag);
1413 err_free_desc:
1414 dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc,
1415 ag->stop_desc_dma);
1416 err_free_irq:
1417 free_irq(dev->irq, dev);
1418 err_unmap_base:
1419 iounmap(ag->mac_base);
1420 err_free_dev:
1421 kfree(dev);
1422 err_out:
1423 platform_set_drvdata(pdev, NULL);
1424 return err;
1425 }
1426
1427 static int ag71xx_remove(struct platform_device *pdev)
1428 {
1429 struct net_device *dev = platform_get_drvdata(pdev);
1430
1431 if (dev) {
1432 struct ag71xx *ag = netdev_priv(dev);
1433
1434 ag71xx_debugfs_exit(ag);
1435 ag71xx_phy_disconnect(ag);
1436 unregister_netdev(dev);
1437 free_irq(dev->irq, dev);
1438 iounmap(ag->mac_base);
1439 kfree(dev);
1440 platform_set_drvdata(pdev, NULL);
1441 }
1442
1443 return 0;
1444 }
1445
1446 static struct platform_driver ag71xx_driver = {
1447 .probe = ag71xx_probe,
1448 .remove = ag71xx_remove,
1449 .driver = {
1450 .name = AG71XX_DRV_NAME,
1451 }
1452 };
1453
1454 static int __init ag71xx_module_init(void)
1455 {
1456 int ret;
1457
1458 ret = ag71xx_debugfs_root_init();
1459 if (ret)
1460 goto err_out;
1461
1462 ret = ag71xx_mdio_driver_init();
1463 if (ret)
1464 goto err_debugfs_exit;
1465
1466 ret = platform_driver_register(&ag71xx_driver);
1467 if (ret)
1468 goto err_mdio_exit;
1469
1470 return 0;
1471
1472 err_mdio_exit:
1473 ag71xx_mdio_driver_exit();
1474 err_debugfs_exit:
1475 ag71xx_debugfs_root_exit();
1476 err_out:
1477 return ret;
1478 }
1479
1480 static void __exit ag71xx_module_exit(void)
1481 {
1482 platform_driver_unregister(&ag71xx_driver);
1483 ag71xx_mdio_driver_exit();
1484 ag71xx_debugfs_root_exit();
1485 }
1486
1487 module_init(ag71xx_module_init);
1488 module_exit(ag71xx_module_exit);
1489
1490 MODULE_VERSION(AG71XX_DRV_VERSION);
1491 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1492 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1493 MODULE_LICENSE("GPL v2");
1494 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
OpenWrt Source Repository