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[openwrt/openwrt.git] / target / linux / ar71xx / files / drivers / net / ethernet / atheros / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include "ag71xx.h"
15
16 #define AG71XX_DEFAULT_MSG_ENABLE \
17 (NETIF_MSG_DRV \
18 | NETIF_MSG_PROBE \
19 | NETIF_MSG_LINK \
20 | NETIF_MSG_TIMER \
21 | NETIF_MSG_IFDOWN \
22 | NETIF_MSG_IFUP \
23 | NETIF_MSG_RX_ERR \
24 | NETIF_MSG_TX_ERR)
25
26 static int ag71xx_msg_level = -1;
27
28 module_param_named(msg_level, ag71xx_msg_level, int, 0);
29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31 static inline unsigned int ag71xx_max_frame_len(unsigned int mtu)
32 {
33 return ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN;
34 }
35
36 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
37 {
38 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
39 ag->dev->name,
40 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
41 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
42 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
43
44 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
45 ag->dev->name,
46 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
47 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
48 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
49 }
50
51 static void ag71xx_dump_regs(struct ag71xx *ag)
52 {
53 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
54 ag->dev->name,
55 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
56 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
57 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
58 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
59 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
60 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
61 ag->dev->name,
62 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
63 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
64 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
65 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
66 ag->dev->name,
67 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
68 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
69 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
70 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
71 ag->dev->name,
72 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
73 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
74 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
75 }
76
77 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
78 {
79 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
80 ag->dev->name, label, intr,
81 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
82 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
83 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
84 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
85 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
86 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
87 }
88
89 static void ag71xx_ring_free(struct ag71xx_ring *ring)
90 {
91 kfree(ring->buf);
92
93 if (ring->descs_cpu)
94 dma_free_coherent(NULL, ring->size * ring->desc_size,
95 ring->descs_cpu, ring->descs_dma);
96 }
97
98 static int ag71xx_ring_alloc(struct ag71xx_ring *ring)
99 {
100 int err;
101 int i;
102
103 ring->desc_size = sizeof(struct ag71xx_desc);
104 if (ring->desc_size % cache_line_size()) {
105 DBG("ag71xx: ring %p, desc size %u rounded to %u\n",
106 ring, ring->desc_size,
107 roundup(ring->desc_size, cache_line_size()));
108 ring->desc_size = roundup(ring->desc_size, cache_line_size());
109 }
110
111 ring->descs_cpu = dma_alloc_coherent(NULL, ring->size * ring->desc_size,
112 &ring->descs_dma, GFP_ATOMIC);
113 if (!ring->descs_cpu) {
114 err = -ENOMEM;
115 goto err;
116 }
117
118
119 ring->buf = kzalloc(ring->size * sizeof(*ring->buf), GFP_KERNEL);
120 if (!ring->buf) {
121 err = -ENOMEM;
122 goto err;
123 }
124
125 for (i = 0; i < ring->size; i++) {
126 int idx = i * ring->desc_size;
127 ring->buf[i].desc = (struct ag71xx_desc *)&ring->descs_cpu[idx];
128 DBG("ag71xx: ring %p, desc %d at %p\n",
129 ring, i, ring->buf[i].desc);
130 }
131
132 return 0;
133
134 err:
135 return err;
136 }
137
138 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
139 {
140 struct ag71xx_ring *ring = &ag->tx_ring;
141 struct net_device *dev = ag->dev;
142 u32 bytes_compl = 0, pkts_compl = 0;
143
144 while (ring->curr != ring->dirty) {
145 u32 i = ring->dirty % ring->size;
146
147 if (!ag71xx_desc_empty(ring->buf[i].desc)) {
148 ring->buf[i].desc->ctrl = 0;
149 dev->stats.tx_errors++;
150 }
151
152 if (ring->buf[i].skb) {
153 bytes_compl += ring->buf[i].len;
154 pkts_compl++;
155 dev_kfree_skb_any(ring->buf[i].skb);
156 }
157 ring->buf[i].skb = NULL;
158 ring->dirty++;
159 }
160
161 /* flush descriptors */
162 wmb();
163
164 netdev_completed_queue(dev, pkts_compl, bytes_compl);
165 }
166
167 static void ag71xx_ring_tx_init(struct ag71xx *ag)
168 {
169 struct ag71xx_ring *ring = &ag->tx_ring;
170 int i;
171
172 for (i = 0; i < ring->size; i++) {
173 ring->buf[i].desc->next = (u32) (ring->descs_dma +
174 ring->desc_size * ((i + 1) % ring->size));
175
176 ring->buf[i].desc->ctrl = DESC_EMPTY;
177 ring->buf[i].skb = NULL;
178 }
179
180 /* flush descriptors */
181 wmb();
182
183 ring->curr = 0;
184 ring->dirty = 0;
185 netdev_reset_queue(ag->dev);
186 }
187
188 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
189 {
190 struct ag71xx_ring *ring = &ag->rx_ring;
191 int i;
192
193 if (!ring->buf)
194 return;
195
196 for (i = 0; i < ring->size; i++)
197 if (ring->buf[i].rx_buf) {
198 dma_unmap_single(&ag->dev->dev, ring->buf[i].dma_addr,
199 ag->rx_buf_size, DMA_FROM_DEVICE);
200 kfree(ring->buf[i].rx_buf);
201 }
202 }
203
204 static int ag71xx_buffer_offset(struct ag71xx *ag)
205 {
206 int offset = NET_SKB_PAD;
207
208 /*
209 * On AR71xx/AR91xx packets must be 4-byte aligned.
210 *
211 * When using builtin AR8216 support, hardware adds a 2-byte header,
212 * so we don't need any extra alignment in that case.
213 */
214 if (!ag71xx_get_pdata(ag)->is_ar724x || ag71xx_has_ar8216(ag))
215 return offset;
216
217 return offset + NET_IP_ALIGN;
218 }
219
220 static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf,
221 int offset)
222 {
223 void *data;
224
225 data = kmalloc(ag->rx_buf_size +
226 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)),
227 GFP_ATOMIC);
228 if (!data)
229 return false;
230
231 buf->rx_buf = data;
232 buf->dma_addr = dma_map_single(&ag->dev->dev, data, ag->rx_buf_size,
233 DMA_FROM_DEVICE);
234 buf->desc->data = (u32) buf->dma_addr + offset;
235 return true;
236 }
237
238 static int ag71xx_ring_rx_init(struct ag71xx *ag)
239 {
240 struct ag71xx_ring *ring = &ag->rx_ring;
241 unsigned int i;
242 int ret;
243 int offset = ag71xx_buffer_offset(ag);
244
245 ret = 0;
246 for (i = 0; i < ring->size; i++) {
247 ring->buf[i].desc->next = (u32) (ring->descs_dma +
248 ring->desc_size * ((i + 1) % ring->size));
249
250 DBG("ag71xx: RX desc at %p, next is %08x\n",
251 ring->buf[i].desc,
252 ring->buf[i].desc->next);
253 }
254
255 for (i = 0; i < ring->size; i++) {
256 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], offset)) {
257 ret = -ENOMEM;
258 break;
259 }
260
261 ring->buf[i].desc->ctrl = DESC_EMPTY;
262 }
263
264 /* flush descriptors */
265 wmb();
266
267 ring->curr = 0;
268 ring->dirty = 0;
269
270 return ret;
271 }
272
273 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
274 {
275 struct ag71xx_ring *ring = &ag->rx_ring;
276 unsigned int count;
277 int offset = ag71xx_buffer_offset(ag);
278
279 count = 0;
280 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
281 unsigned int i;
282
283 i = ring->dirty % ring->size;
284
285 if (!ring->buf[i].rx_buf &&
286 !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset))
287 break;
288
289 ring->buf[i].desc->ctrl = DESC_EMPTY;
290 count++;
291 }
292
293 /* flush descriptors */
294 wmb();
295
296 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
297
298 return count;
299 }
300
301 static int ag71xx_rings_init(struct ag71xx *ag)
302 {
303 int ret;
304
305 ret = ag71xx_ring_alloc(&ag->tx_ring);
306 if (ret)
307 return ret;
308
309 ag71xx_ring_tx_init(ag);
310
311 ret = ag71xx_ring_alloc(&ag->rx_ring);
312 if (ret)
313 return ret;
314
315 ret = ag71xx_ring_rx_init(ag);
316 return ret;
317 }
318
319 static void ag71xx_rings_cleanup(struct ag71xx *ag)
320 {
321 ag71xx_ring_rx_clean(ag);
322 ag71xx_ring_free(&ag->rx_ring);
323
324 ag71xx_ring_tx_clean(ag);
325 netdev_reset_queue(ag->dev);
326 ag71xx_ring_free(&ag->tx_ring);
327 }
328
329 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
330 {
331 switch (ag->speed) {
332 case SPEED_1000:
333 return "1000";
334 case SPEED_100:
335 return "100";
336 case SPEED_10:
337 return "10";
338 }
339
340 return "?";
341 }
342
343 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
344 {
345 u32 t;
346
347 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
348 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
349
350 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
351
352 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
353 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
354 }
355
356 static void ag71xx_dma_reset(struct ag71xx *ag)
357 {
358 u32 val;
359 int i;
360
361 ag71xx_dump_dma_regs(ag);
362
363 /* stop RX and TX */
364 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
365 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
366
367 /*
368 * give the hardware some time to really stop all rx/tx activity
369 * clearing the descriptors too early causes random memory corruption
370 */
371 mdelay(1);
372
373 /* clear descriptor addresses */
374 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
375 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
376
377 /* clear pending RX/TX interrupts */
378 for (i = 0; i < 256; i++) {
379 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
380 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
381 }
382
383 /* clear pending errors */
384 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
385 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
386
387 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
388 if (val)
389 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
390 ag->dev->name, val);
391
392 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
393
394 /* mask out reserved bits */
395 val &= ~0xff000000;
396
397 if (val)
398 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
399 ag->dev->name, val);
400
401 ag71xx_dump_dma_regs(ag);
402 }
403
404 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
405 MAC_CFG1_SRX | MAC_CFG1_STX)
406
407 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
408
409 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
410 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
411 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
412 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
413 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
414 FIFO_CFG4_VT)
415
416 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
417 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
418 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
419 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
420 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
421 FIFO_CFG5_17 | FIFO_CFG5_SF)
422
423 static void ag71xx_hw_stop(struct ag71xx *ag)
424 {
425 /* disable all interrupts and stop the rx/tx engine */
426 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
427 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
428 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
429 }
430
431 static void ag71xx_hw_setup(struct ag71xx *ag)
432 {
433 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
434
435 /* setup MAC configuration registers */
436 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
437
438 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
439 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
440
441 /* setup max frame length */
442 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, ag->max_frame_len);
443
444 /* setup FIFO configuration registers */
445 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
446 if (pdata->is_ar724x) {
447 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, pdata->fifo_cfg1);
448 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, pdata->fifo_cfg2);
449 } else {
450 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
451 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
452 }
453 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
454 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
455 }
456
457 static void ag71xx_hw_init(struct ag71xx *ag)
458 {
459 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
460 u32 reset_mask = pdata->reset_bit;
461
462 ag71xx_hw_stop(ag);
463
464 if (pdata->is_ar724x) {
465 u32 reset_phy = reset_mask;
466
467 reset_phy &= AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY;
468 reset_mask &= ~(AR71XX_RESET_GE0_PHY | AR71XX_RESET_GE1_PHY);
469
470 ath79_device_reset_set(reset_phy);
471 mdelay(50);
472 ath79_device_reset_clear(reset_phy);
473 mdelay(200);
474 }
475
476 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
477 udelay(20);
478
479 ath79_device_reset_set(reset_mask);
480 mdelay(100);
481 ath79_device_reset_clear(reset_mask);
482 mdelay(200);
483
484 ag71xx_hw_setup(ag);
485
486 ag71xx_dma_reset(ag);
487 }
488
489 static void ag71xx_fast_reset(struct ag71xx *ag)
490 {
491 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
492 struct net_device *dev = ag->dev;
493 u32 reset_mask = pdata->reset_bit;
494 u32 rx_ds, tx_ds;
495 u32 mii_reg;
496
497 reset_mask &= AR71XX_RESET_GE0_MAC | AR71XX_RESET_GE1_MAC;
498
499 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
500 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
501 tx_ds = ag71xx_rr(ag, AG71XX_REG_TX_DESC);
502
503 ath79_device_reset_set(reset_mask);
504 udelay(10);
505 ath79_device_reset_clear(reset_mask);
506 udelay(10);
507
508 ag71xx_dma_reset(ag);
509 ag71xx_hw_setup(ag);
510
511 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
512 ag71xx_wr(ag, AG71XX_REG_TX_DESC, tx_ds);
513 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
514
515 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
516 }
517
518 static void ag71xx_hw_start(struct ag71xx *ag)
519 {
520 /* start RX engine */
521 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
522
523 /* enable interrupts */
524 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
525 }
526
527 void ag71xx_link_adjust(struct ag71xx *ag)
528 {
529 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
530 u32 cfg2;
531 u32 ifctl;
532 u32 fifo5;
533
534 if (!ag->link) {
535 ag71xx_hw_stop(ag);
536 netif_carrier_off(ag->dev);
537 if (netif_msg_link(ag))
538 pr_info("%s: link down\n", ag->dev->name);
539 return;
540 }
541
542 if (pdata->is_ar724x)
543 ag71xx_fast_reset(ag);
544
545 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
546 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
547 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
548
549 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
550 ifctl &= ~(MAC_IFCTL_SPEED);
551
552 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
553 fifo5 &= ~FIFO_CFG5_BM;
554
555 switch (ag->speed) {
556 case SPEED_1000:
557 cfg2 |= MAC_CFG2_IF_1000;
558 fifo5 |= FIFO_CFG5_BM;
559 break;
560 case SPEED_100:
561 cfg2 |= MAC_CFG2_IF_10_100;
562 ifctl |= MAC_IFCTL_SPEED;
563 break;
564 case SPEED_10:
565 cfg2 |= MAC_CFG2_IF_10_100;
566 break;
567 default:
568 BUG();
569 return;
570 }
571
572 if (pdata->is_ar91xx)
573 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x00780fff);
574 else if (pdata->is_ar724x)
575 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, pdata->fifo_cfg3);
576 else
577 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, 0x008001ff);
578
579 if (pdata->set_speed)
580 pdata->set_speed(ag->speed);
581
582 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
583 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
584 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
585 ag71xx_hw_start(ag);
586
587 netif_carrier_on(ag->dev);
588 if (netif_msg_link(ag))
589 pr_info("%s: link up (%sMbps/%s duplex)\n",
590 ag->dev->name,
591 ag71xx_speed_str(ag),
592 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
593
594 DBG("%s: fifo_cfg0=%#x, fifo_cfg1=%#x, fifo_cfg2=%#x\n",
595 ag->dev->name,
596 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
597 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
598 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
599
600 DBG("%s: fifo_cfg3=%#x, fifo_cfg4=%#x, fifo_cfg5=%#x\n",
601 ag->dev->name,
602 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
603 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
604 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
605
606 DBG("%s: mac_cfg2=%#x, mac_ifctl=%#x\n",
607 ag->dev->name,
608 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
609 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL));
610 }
611
612 static int ag71xx_open(struct net_device *dev)
613 {
614 struct ag71xx *ag = netdev_priv(dev);
615 int ret;
616
617 ag->rx_buf_size = ag->max_frame_len + NET_SKB_PAD + NET_IP_ALIGN;
618
619 ret = ag71xx_rings_init(ag);
620 if (ret)
621 goto err;
622
623 napi_enable(&ag->napi);
624
625 netif_carrier_off(dev);
626 ag71xx_phy_start(ag);
627
628 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
629 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
630
631 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
632
633 netif_start_queue(dev);
634
635 return 0;
636
637 err:
638 ag71xx_rings_cleanup(ag);
639 return ret;
640 }
641
642 static int ag71xx_stop(struct net_device *dev)
643 {
644 struct ag71xx *ag = netdev_priv(dev);
645 unsigned long flags;
646
647 netif_carrier_off(dev);
648 ag71xx_phy_stop(ag);
649
650 spin_lock_irqsave(&ag->lock, flags);
651
652 netif_stop_queue(dev);
653
654 ag71xx_hw_stop(ag);
655 ag71xx_dma_reset(ag);
656
657 napi_disable(&ag->napi);
658 del_timer_sync(&ag->oom_timer);
659
660 spin_unlock_irqrestore(&ag->lock, flags);
661
662 ag71xx_rings_cleanup(ag);
663
664 return 0;
665 }
666
667 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
668 struct net_device *dev)
669 {
670 struct ag71xx *ag = netdev_priv(dev);
671 struct ag71xx_ring *ring = &ag->tx_ring;
672 struct ag71xx_desc *desc;
673 dma_addr_t dma_addr;
674 int i;
675
676 i = ring->curr % ring->size;
677 desc = ring->buf[i].desc;
678
679 if (!ag71xx_desc_empty(desc))
680 goto err_drop;
681
682 if (ag71xx_has_ar8216(ag))
683 ag71xx_add_ar8216_header(ag, skb);
684
685 if (skb->len <= 0) {
686 DBG("%s: packet len is too small\n", ag->dev->name);
687 goto err_drop;
688 }
689
690 dma_addr = dma_map_single(&dev->dev, skb->data, skb->len,
691 DMA_TO_DEVICE);
692
693 netdev_sent_queue(dev, skb->len);
694 ring->buf[i].len = skb->len;
695 ring->buf[i].skb = skb;
696 ring->buf[i].timestamp = jiffies;
697
698 /* setup descriptor fields */
699 desc->data = (u32) dma_addr;
700 desc->ctrl = skb->len & ag->desc_pktlen_mask;
701
702 /* flush descriptor */
703 wmb();
704
705 ring->curr++;
706 if (ring->curr == (ring->dirty + ring->size)) {
707 DBG("%s: tx queue full\n", ag->dev->name);
708 netif_stop_queue(dev);
709 }
710
711 DBG("%s: packet injected into TX queue\n", ag->dev->name);
712
713 /* enable TX engine */
714 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
715
716 return NETDEV_TX_OK;
717
718 err_drop:
719 dev->stats.tx_dropped++;
720
721 dev_kfree_skb(skb);
722 return NETDEV_TX_OK;
723 }
724
725 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
726 {
727 struct ag71xx *ag = netdev_priv(dev);
728 int ret;
729
730 switch (cmd) {
731 case SIOCETHTOOL:
732 if (ag->phy_dev == NULL)
733 break;
734
735 spin_lock_irq(&ag->lock);
736 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
737 spin_unlock_irq(&ag->lock);
738 return ret;
739
740 case SIOCSIFHWADDR:
741 if (copy_from_user
742 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
743 return -EFAULT;
744 return 0;
745
746 case SIOCGIFHWADDR:
747 if (copy_to_user
748 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
749 return -EFAULT;
750 return 0;
751
752 case SIOCGMIIPHY:
753 case SIOCGMIIREG:
754 case SIOCSMIIREG:
755 if (ag->phy_dev == NULL)
756 break;
757
758 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
759
760 default:
761 break;
762 }
763
764 return -EOPNOTSUPP;
765 }
766
767 static void ag71xx_oom_timer_handler(unsigned long data)
768 {
769 struct net_device *dev = (struct net_device *) data;
770 struct ag71xx *ag = netdev_priv(dev);
771
772 napi_schedule(&ag->napi);
773 }
774
775 static void ag71xx_tx_timeout(struct net_device *dev)
776 {
777 struct ag71xx *ag = netdev_priv(dev);
778
779 if (netif_msg_tx_err(ag))
780 pr_info("%s: tx timeout\n", ag->dev->name);
781
782 schedule_work(&ag->restart_work);
783 }
784
785 static void ag71xx_restart_work_func(struct work_struct *work)
786 {
787 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work);
788
789 if (ag71xx_get_pdata(ag)->is_ar724x) {
790 ag->link = 0;
791 ag71xx_link_adjust(ag);
792 return;
793 }
794
795 ag71xx_stop(ag->dev);
796 ag71xx_open(ag->dev);
797 }
798
799 static bool ag71xx_check_dma_stuck(struct ag71xx *ag, unsigned long timestamp)
800 {
801 u32 rx_sm, tx_sm, rx_fd;
802
803 if (likely(time_before(jiffies, timestamp + HZ/10)))
804 return false;
805
806 if (!netif_carrier_ok(ag->dev))
807 return false;
808
809 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
810 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
811 return true;
812
813 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
814 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
815 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
816 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
817 return true;
818
819 return false;
820 }
821
822 static int ag71xx_tx_packets(struct ag71xx *ag)
823 {
824 struct ag71xx_ring *ring = &ag->tx_ring;
825 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
826 int sent = 0;
827 int bytes_compl = 0;
828
829 DBG("%s: processing TX ring\n", ag->dev->name);
830
831 while (ring->dirty != ring->curr) {
832 unsigned int i = ring->dirty % ring->size;
833 struct ag71xx_desc *desc = ring->buf[i].desc;
834 struct sk_buff *skb = ring->buf[i].skb;
835 int len = ring->buf[i].len;
836
837 if (!ag71xx_desc_empty(desc)) {
838 if (pdata->is_ar7240 &&
839 ag71xx_check_dma_stuck(ag, ring->buf[i].timestamp))
840 schedule_work(&ag->restart_work);
841 break;
842 }
843
844 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
845
846 bytes_compl += len;
847 ag->dev->stats.tx_bytes += len;
848 ag->dev->stats.tx_packets++;
849
850 dev_kfree_skb_any(skb);
851 ring->buf[i].skb = NULL;
852
853 ring->dirty++;
854 sent++;
855 }
856
857 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
858
859 if (!sent)
860 return 0;
861
862 netdev_completed_queue(ag->dev, sent, bytes_compl);
863 if ((ring->curr - ring->dirty) < (ring->size * 3) / 4)
864 netif_wake_queue(ag->dev);
865
866 return sent;
867 }
868
869 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
870 {
871 struct net_device *dev = ag->dev;
872 struct ag71xx_ring *ring = &ag->rx_ring;
873 int offset = ag71xx_buffer_offset(ag);
874 unsigned int pktlen_mask = ag->desc_pktlen_mask;
875 int done = 0;
876
877 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
878 dev->name, limit, ring->curr, ring->dirty);
879
880 while (done < limit) {
881 unsigned int i = ring->curr % ring->size;
882 struct ag71xx_desc *desc = ring->buf[i].desc;
883 struct sk_buff *skb;
884 int pktlen;
885 int err = 0;
886
887 if (ag71xx_desc_empty(desc))
888 break;
889
890 if ((ring->dirty + ring->size) == ring->curr) {
891 ag71xx_assert(0);
892 break;
893 }
894
895 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
896
897 pktlen = desc->ctrl & pktlen_mask;
898 pktlen -= ETH_FCS_LEN;
899
900 dma_unmap_single(&dev->dev, ring->buf[i].dma_addr,
901 ag->rx_buf_size, DMA_FROM_DEVICE);
902
903 dev->stats.rx_packets++;
904 dev->stats.rx_bytes += pktlen;
905
906 skb = build_skb(ring->buf[i].rx_buf, 0);
907 if (!skb) {
908 kfree(ring->buf[i].rx_buf);
909 goto next;
910 }
911
912 skb_reserve(skb, offset);
913 skb_put(skb, pktlen);
914
915 if (ag71xx_has_ar8216(ag))
916 err = ag71xx_remove_ar8216_header(ag, skb, pktlen);
917
918 if (err) {
919 dev->stats.rx_dropped++;
920 kfree_skb(skb);
921 } else {
922 skb->dev = dev;
923 skb->ip_summed = CHECKSUM_NONE;
924 skb->protocol = eth_type_trans(skb, dev);
925 netif_receive_skb(skb);
926 }
927
928 next:
929 ring->buf[i].rx_buf = NULL;
930 done++;
931
932 ring->curr++;
933 }
934
935 ag71xx_ring_rx_refill(ag);
936
937 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
938 dev->name, ring->curr, ring->dirty, done);
939
940 return done;
941 }
942
943 static int ag71xx_poll(struct napi_struct *napi, int limit)
944 {
945 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
946 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
947 struct net_device *dev = ag->dev;
948 struct ag71xx_ring *rx_ring;
949 unsigned long flags;
950 u32 status;
951 int tx_done;
952 int rx_done;
953
954 pdata->ddr_flush();
955 tx_done = ag71xx_tx_packets(ag);
956
957 DBG("%s: processing RX ring\n", dev->name);
958 rx_done = ag71xx_rx_packets(ag, limit);
959
960 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
961
962 rx_ring = &ag->rx_ring;
963 if (rx_ring->buf[rx_ring->dirty % rx_ring->size].rx_buf == NULL)
964 goto oom;
965
966 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
967 if (unlikely(status & RX_STATUS_OF)) {
968 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
969 dev->stats.rx_fifo_errors++;
970
971 /* restart RX */
972 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
973 }
974
975 if (rx_done < limit) {
976 if (status & RX_STATUS_PR)
977 goto more;
978
979 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
980 if (status & TX_STATUS_PS)
981 goto more;
982
983 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
984 dev->name, rx_done, tx_done, limit);
985
986 napi_complete(napi);
987
988 /* enable interrupts */
989 spin_lock_irqsave(&ag->lock, flags);
990 ag71xx_int_enable(ag, AG71XX_INT_POLL);
991 spin_unlock_irqrestore(&ag->lock, flags);
992 return rx_done;
993 }
994
995 more:
996 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
997 dev->name, rx_done, tx_done, limit);
998 return rx_done;
999
1000 oom:
1001 if (netif_msg_rx_err(ag))
1002 pr_info("%s: out of memory\n", dev->name);
1003
1004 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
1005 napi_complete(napi);
1006 return 0;
1007 }
1008
1009 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
1010 {
1011 struct net_device *dev = dev_id;
1012 struct ag71xx *ag = netdev_priv(dev);
1013 u32 status;
1014
1015 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1016 ag71xx_dump_intr(ag, "raw", status);
1017
1018 if (unlikely(!status))
1019 return IRQ_NONE;
1020
1021 if (unlikely(status & AG71XX_INT_ERR)) {
1022 if (status & AG71XX_INT_TX_BE) {
1023 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1024 dev_err(&dev->dev, "TX BUS error\n");
1025 }
1026 if (status & AG71XX_INT_RX_BE) {
1027 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1028 dev_err(&dev->dev, "RX BUS error\n");
1029 }
1030 }
1031
1032 if (likely(status & AG71XX_INT_POLL)) {
1033 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1034 DBG("%s: enable polling mode\n", dev->name);
1035 napi_schedule(&ag->napi);
1036 }
1037
1038 ag71xx_debugfs_update_int_stats(ag, status);
1039
1040 return IRQ_HANDLED;
1041 }
1042
1043 #ifdef CONFIG_NET_POLL_CONTROLLER
1044 /*
1045 * Polling 'interrupt' - used by things like netconsole to send skbs
1046 * without having to re-enable interrupts. It's not called while
1047 * the interrupt routine is executing.
1048 */
1049 static void ag71xx_netpoll(struct net_device *dev)
1050 {
1051 disable_irq(dev->irq);
1052 ag71xx_interrupt(dev->irq, dev);
1053 enable_irq(dev->irq);
1054 }
1055 #endif
1056
1057 static int ag71xx_change_mtu(struct net_device *dev, int new_mtu)
1058 {
1059 struct ag71xx *ag = netdev_priv(dev);
1060 unsigned int max_frame_len;
1061
1062 max_frame_len = ag71xx_max_frame_len(new_mtu);
1063 if (new_mtu < 68 || max_frame_len > ag->max_frame_len)
1064 return -EINVAL;
1065
1066 dev->mtu = new_mtu;
1067 return 0;
1068 }
1069
1070 static const struct net_device_ops ag71xx_netdev_ops = {
1071 .ndo_open = ag71xx_open,
1072 .ndo_stop = ag71xx_stop,
1073 .ndo_start_xmit = ag71xx_hard_start_xmit,
1074 .ndo_do_ioctl = ag71xx_do_ioctl,
1075 .ndo_tx_timeout = ag71xx_tx_timeout,
1076 .ndo_change_mtu = ag71xx_change_mtu,
1077 .ndo_set_mac_address = eth_mac_addr,
1078 .ndo_validate_addr = eth_validate_addr,
1079 #ifdef CONFIG_NET_POLL_CONTROLLER
1080 .ndo_poll_controller = ag71xx_netpoll,
1081 #endif
1082 };
1083
1084 static const char *ag71xx_get_phy_if_mode_name(phy_interface_t mode)
1085 {
1086 switch (mode) {
1087 case PHY_INTERFACE_MODE_MII:
1088 return "MII";
1089 case PHY_INTERFACE_MODE_GMII:
1090 return "GMII";
1091 case PHY_INTERFACE_MODE_RMII:
1092 return "RMII";
1093 case PHY_INTERFACE_MODE_RGMII:
1094 return "RGMII";
1095 case PHY_INTERFACE_MODE_SGMII:
1096 return "SGMII";
1097 default:
1098 break;
1099 }
1100
1101 return "unknown";
1102 }
1103
1104
1105 static int ag71xx_probe(struct platform_device *pdev)
1106 {
1107 struct net_device *dev;
1108 struct resource *res;
1109 struct ag71xx *ag;
1110 struct ag71xx_platform_data *pdata;
1111 int err;
1112
1113 pdata = pdev->dev.platform_data;
1114 if (!pdata) {
1115 dev_err(&pdev->dev, "no platform data specified\n");
1116 err = -ENXIO;
1117 goto err_out;
1118 }
1119
1120 if (pdata->mii_bus_dev == NULL && pdata->phy_mask) {
1121 dev_err(&pdev->dev, "no MII bus device specified\n");
1122 err = -EINVAL;
1123 goto err_out;
1124 }
1125
1126 dev = alloc_etherdev(sizeof(*ag));
1127 if (!dev) {
1128 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1129 err = -ENOMEM;
1130 goto err_out;
1131 }
1132
1133 if (!pdata->max_frame_len || !pdata->desc_pktlen_mask)
1134 return -EINVAL;
1135
1136 SET_NETDEV_DEV(dev, &pdev->dev);
1137
1138 ag = netdev_priv(dev);
1139 ag->pdev = pdev;
1140 ag->dev = dev;
1141 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1142 AG71XX_DEFAULT_MSG_ENABLE);
1143 spin_lock_init(&ag->lock);
1144
1145 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
1146 if (!res) {
1147 dev_err(&pdev->dev, "no mac_base resource found\n");
1148 err = -ENXIO;
1149 goto err_out;
1150 }
1151
1152 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
1153 if (!ag->mac_base) {
1154 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
1155 err = -ENOMEM;
1156 goto err_free_dev;
1157 }
1158
1159 dev->irq = platform_get_irq(pdev, 0);
1160 err = request_irq(dev->irq, ag71xx_interrupt,
1161 IRQF_DISABLED,
1162 dev->name, dev);
1163 if (err) {
1164 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1165 goto err_unmap_base;
1166 }
1167
1168 dev->base_addr = (unsigned long)ag->mac_base;
1169 dev->netdev_ops = &ag71xx_netdev_ops;
1170 dev->ethtool_ops = &ag71xx_ethtool_ops;
1171
1172 INIT_WORK(&ag->restart_work, ag71xx_restart_work_func);
1173
1174 init_timer(&ag->oom_timer);
1175 ag->oom_timer.data = (unsigned long) dev;
1176 ag->oom_timer.function = ag71xx_oom_timer_handler;
1177
1178 ag->tx_ring.size = AG71XX_TX_RING_SIZE_DEFAULT;
1179 ag->rx_ring.size = AG71XX_RX_RING_SIZE_DEFAULT;
1180
1181 ag->max_frame_len = pdata->max_frame_len;
1182 ag->desc_pktlen_mask = pdata->desc_pktlen_mask;
1183
1184 ag->stop_desc = dma_alloc_coherent(NULL,
1185 sizeof(struct ag71xx_desc), &ag->stop_desc_dma, GFP_KERNEL);
1186
1187 if (!ag->stop_desc)
1188 goto err_free_irq;
1189
1190 ag->stop_desc->data = 0;
1191 ag->stop_desc->ctrl = 0;
1192 ag->stop_desc->next = (u32) ag->stop_desc_dma;
1193
1194 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
1195
1196 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1197
1198 ag71xx_dump_regs(ag);
1199
1200 ag71xx_hw_init(ag);
1201
1202 ag71xx_dump_regs(ag);
1203
1204 err = ag71xx_phy_connect(ag);
1205 if (err)
1206 goto err_free_desc;
1207
1208 err = ag71xx_debugfs_init(ag);
1209 if (err)
1210 goto err_phy_disconnect;
1211
1212 platform_set_drvdata(pdev, dev);
1213
1214 err = register_netdev(dev);
1215 if (err) {
1216 dev_err(&pdev->dev, "unable to register net device\n");
1217 goto err_debugfs_exit;
1218 }
1219
1220 pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n",
1221 dev->name, dev->base_addr, dev->irq,
1222 ag71xx_get_phy_if_mode_name(pdata->phy_if_mode));
1223
1224 return 0;
1225
1226 err_debugfs_exit:
1227 ag71xx_debugfs_exit(ag);
1228 err_phy_disconnect:
1229 ag71xx_phy_disconnect(ag);
1230 err_free_desc:
1231 dma_free_coherent(NULL, sizeof(struct ag71xx_desc), ag->stop_desc,
1232 ag->stop_desc_dma);
1233 err_free_irq:
1234 free_irq(dev->irq, dev);
1235 err_unmap_base:
1236 iounmap(ag->mac_base);
1237 err_free_dev:
1238 kfree(dev);
1239 err_out:
1240 platform_set_drvdata(pdev, NULL);
1241 return err;
1242 }
1243
1244 static int ag71xx_remove(struct platform_device *pdev)
1245 {
1246 struct net_device *dev = platform_get_drvdata(pdev);
1247
1248 if (dev) {
1249 struct ag71xx *ag = netdev_priv(dev);
1250
1251 ag71xx_debugfs_exit(ag);
1252 ag71xx_phy_disconnect(ag);
1253 unregister_netdev(dev);
1254 free_irq(dev->irq, dev);
1255 iounmap(ag->mac_base);
1256 kfree(dev);
1257 platform_set_drvdata(pdev, NULL);
1258 }
1259
1260 return 0;
1261 }
1262
1263 static struct platform_driver ag71xx_driver = {
1264 .probe = ag71xx_probe,
1265 .remove = ag71xx_remove,
1266 .driver = {
1267 .name = AG71XX_DRV_NAME,
1268 }
1269 };
1270
1271 static int __init ag71xx_module_init(void)
1272 {
1273 int ret;
1274
1275 ret = ag71xx_debugfs_root_init();
1276 if (ret)
1277 goto err_out;
1278
1279 ret = ag71xx_mdio_driver_init();
1280 if (ret)
1281 goto err_debugfs_exit;
1282
1283 ret = platform_driver_register(&ag71xx_driver);
1284 if (ret)
1285 goto err_mdio_exit;
1286
1287 return 0;
1288
1289 err_mdio_exit:
1290 ag71xx_mdio_driver_exit();
1291 err_debugfs_exit:
1292 ag71xx_debugfs_root_exit();
1293 err_out:
1294 return ret;
1295 }
1296
1297 static void __exit ag71xx_module_exit(void)
1298 {
1299 platform_driver_unregister(&ag71xx_driver);
1300 ag71xx_mdio_driver_exit();
1301 ag71xx_debugfs_root_exit();
1302 }
1303
1304 module_init(ag71xx_module_init);
1305 module_exit(ag71xx_module_exit);
1306
1307 MODULE_VERSION(AG71XX_DRV_VERSION);
1308 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1309 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1310 MODULE_LICENSE("GPL v2");
1311 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
OpenWrt Source Repository