target/linux/at91/patches-5.10/174-media-atmel-atmel-isc-extend-pipeline-with-extra-mod.patch

   1 From 58a6cc3c7eecd16208cd16b92b4eaf8385e69696 Mon Sep 17 00:00:00 2001
   2 From: Eugen Hristev <eugen.hristev@microchip.com>
   3 Date: Tue, 13 Apr 2021 12:57:16 +0200
   4 Subject: [PATCH 174/247] media: atmel: atmel-isc: extend pipeline with extra
   5  modules
   6
   7 Newer ISC pipelines have the additional modules of
   8 Defective Pixel Correction -> DPC itself,
   9 Defective Pixel Correction -> Green Disparity Correction (DPC_GDC)
  10 Defective Pixel Correction -> Black Level Correction (DPC_BLC)
  11 Vertical and Horizontal Scaler -> VHXS
  12
  13 Some products have this full pipeline (sama7g5), other products do not (sama5d2)
  14
  15 Add the modules to the isc base, and also extend the register range to include
  16 the modules.
  17
  18 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
  19 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
  20 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
  21 ---
  22  drivers/media/platform/atmel/atmel-isc-base.c | 11 ++++++--
  23  drivers/media/platform/atmel/atmel-isc.h      | 28 +++++++++++--------
  24  2 files changed, 25 insertions(+), 14 deletions(-)
  25
  26 --- a/drivers/media/platform/atmel/atmel-isc-base.c
  27 +++ b/drivers/media/platform/atmel/atmel-isc-base.c
  28 @@ -2324,8 +2324,14 @@ int isc_pipeline_init(struct isc_device
  29         struct regmap_field *regs;
  30         unsigned int i;
  31
  32 -       /* WB-->CFA-->CC-->GAM-->CSC-->CBC-->SUB422-->SUB420 */
  33 +       /*
  34 +        * DPCEN-->GDCEN-->BLCEN-->WB-->CFA-->CC-->
  35 +        * GAM-->VHXS-->CSC-->CBC-->SUB422-->SUB420
  36 +        */
  37         const struct reg_field regfields[ISC_PIPE_LINE_NODE_NUM] = {
  38 +               REG_FIELD(ISC_DPC_CTRL, 0, 0),
  39 +               REG_FIELD(ISC_DPC_CTRL, 1, 1),
  40 +               REG_FIELD(ISC_DPC_CTRL, 2, 2),
  41                 REG_FIELD(ISC_WB_CTRL, 0, 0),
  42                 REG_FIELD(ISC_CFA_CTRL, 0, 0),
  43                 REG_FIELD(ISC_CC_CTRL, 0, 0),
  44 @@ -2333,6 +2339,7 @@ int isc_pipeline_init(struct isc_device
  45                 REG_FIELD(ISC_GAM_CTRL, 1, 1),
  46                 REG_FIELD(ISC_GAM_CTRL, 2, 2),
  47                 REG_FIELD(ISC_GAM_CTRL, 3, 3),
  48 +               REG_FIELD(ISC_VHXS_CTRL, 0, 0),
  49                 REG_FIELD(ISC_CSC_CTRL + isc->offsets.csc, 0, 0),
  50                 REG_FIELD(ISC_CBC_CTRL + isc->offsets.cbc, 0, 0),
  51                 REG_FIELD(ISC_SUB422_CTRL + isc->offsets.sub422, 0, 0),
  52 @@ -2351,7 +2358,7 @@ int isc_pipeline_init(struct isc_device
  53  }
  54
  55  /* regmap configuration */
  56 -#define ATMEL_ISC_REG_MAX    0xbfc
  57 +#define ATMEL_ISC_REG_MAX    0xd5c
  58  const struct regmap_config isc_regmap_config = {
  59         .reg_bits       = 32,
  60         .reg_stride     = 4,
  61 --- a/drivers/media/platform/atmel/atmel-isc.h
  62 +++ b/drivers/media/platform/atmel/atmel-isc.h
  63 @@ -67,17 +67,21 @@ struct isc_format {
  64  };
  65
  66  /* Pipeline bitmap */
  67 -#define WB_ENABLE      BIT(0)
  68 -#define CFA_ENABLE     BIT(1)
  69 -#define CC_ENABLE      BIT(2)
  70 -#define GAM_ENABLE     BIT(3)
  71 -#define GAM_BENABLE    BIT(4)
  72 -#define GAM_GENABLE    BIT(5)
  73 -#define GAM_RENABLE    BIT(6)
  74 -#define CSC_ENABLE     BIT(7)
  75 -#define CBC_ENABLE     BIT(8)
  76 -#define SUB422_ENABLE  BIT(9)
  77 -#define SUB420_ENABLE  BIT(10)
  78 +#define DPC_DPCENABLE  BIT(0)
  79 +#define DPC_GDCENABLE  BIT(1)
  80 +#define DPC_BLCENABLE  BIT(2)
  81 +#define WB_ENABLE      BIT(3)
  82 +#define CFA_ENABLE     BIT(4)
  83 +#define CC_ENABLE      BIT(5)
  84 +#define GAM_ENABLE     BIT(6)
  85 +#define GAM_BENABLE    BIT(7)
  86 +#define GAM_GENABLE    BIT(8)
  87 +#define GAM_RENABLE    BIT(9)
  88 +#define VHXS_ENABLE    BIT(10)
  89 +#define CSC_ENABLE     BIT(11)
  90 +#define CBC_ENABLE     BIT(12)
  91 +#define SUB422_ENABLE  BIT(13)
  92 +#define SUB420_ENABLE  BIT(14)
  93
  94  #define GAM_ENABLES    (GAM_RENABLE | GAM_GENABLE | GAM_BENABLE | GAM_ENABLE)
  95
  96 @@ -141,7 +145,7 @@ struct isc_ctrls {
  97         u32 hist_minmax[HIST_BAYER][2];
  98  };
  99
 100 -#define ISC_PIPE_LINE_NODE_NUM 11
 101 +#define ISC_PIPE_LINE_NODE_NUM 15
 102
 103  /*
 104   * struct isc_reg_offsets - ISC device register offsets