target/linux/at91/patches-5.15/206-ARM-at91-sfrbu-add-sfrbu-registers-definitions-for-s.patch

   1 From c6b435625975d9a6daeffd81509a9877ddfb93b5 Mon Sep 17 00:00:00 2001
   2 From: Claudiu Beznea <claudiu.beznea@microchip.com>
   3 Date: Thu, 15 Apr 2021 13:49:56 +0300
   4 Subject: [PATCH 206/247] ARM: at91: sfrbu: add sfrbu registers definitions for
   5  sama7g5
   6
   7 Add SFRBU registers definitions for SAMA7G5.
   8
   9 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
  10 Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
  11 Link: https://lore.kernel.org/r/20210415105010.569620-11-claudiu.beznea@microchip.com
  12 ---
  13  include/soc/at91/sama7-sfrbu.h | 34 ++++++++++++++++++++++++++++++++++
  14  1 file changed, 34 insertions(+)
  15  create mode 100644 include/soc/at91/sama7-sfrbu.h
  16
  17 --- /dev/null
  18 +++ b/include/soc/at91/sama7-sfrbu.h
  19 @@ -0,0 +1,34 @@
  20 +/* SPDX-License-Identifier: GPL-2.0-only */
  21 +/*
  22 + * Microchip SAMA7 SFRBU registers offsets and bit definitions.
  23 + *
  24 + * Copyright (C) [2020] Microchip Technology Inc. and its subsidiaries
  25 + *
  26 + * Author: Claudu Beznea <claudiu.beznea@microchip.com>
  27 + */
  28 +
  29 +#ifndef __SAMA7_SFRBU_H__
  30 +#define __SAMA7_SFRBU_H__
  31 +
  32 +#ifdef CONFIG_SOC_SAMA7
  33 +
  34 +#define AT91_SFRBU_PSWBU                       (0x00)          /* SFRBU Power Switch BU Control Register */
  35 +#define                AT91_SFRBU_PSWBU_PSWKEY         (0x4BD20C << 8) /* Specific value mandatory to allow writing of other register bits */
  36 +#define                AT91_SFRBU_PSWBU_STATE          (1 << 2)        /* Power switch BU state */
  37 +#define                AT91_SFRBU_PSWBU_SOFTSWITCH     (1 << 1)        /* Power switch BU source selection */
  38 +#define                AT91_SFRBU_PSWBU_CTRL           (1 << 0)        /* Power switch BU control */
  39 +
  40 +#define AT91_SFRBU_25LDOCR                     (0x0C)          /* SFRBU 2.5V LDO Control Register */
  41 +#define                AT91_SFRBU_25LDOCR_LDOANAKEY    (0x3B6E18 << 8) /* Specific value mandatory to allow writing of other register bits. */
  42 +#define                AT91_SFRBU_25LDOCR_STATE        (1 << 3)        /* LDOANA Switch On/Off Control */
  43 +#define                AT91_SFRBU_25LDOCR_LP           (1 << 2)        /* LDOANA Low-Power Mode Control */
  44 +#define                AT91_SFRBU_PD_VALUE_MSK         (0x3)
  45 +#define                AT91_SFRBU_25LDOCR_PD_VALUE(v)  ((v) & AT91_SFRBU_PD_VALUE_MSK) /* LDOANA Pull-down value */
  46 +
  47 +#define AT91_FRBU_DDRPWR                       (0x10)          /* SFRBU DDR Power Control Register */
  48 +#define                AT91_FRBU_DDRPWR_STATE          (1 << 0)        /* DDR Power Mode State */
  49 +
  50 +#endif /* CONFIG_SOC_SAMA7 */
  51 +
  52 +#endif /* __SAMA7_SFRBU_H__ */
  53 +