target/linux/ath79/dts/ar9344_pcs_cr5000.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include "ar9344.dtsi"
   4
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/input/input.h>
   7
   8 / {
   9         model = "PowerCloud Systems CR5000";
  10         compatible = "pcs,cr5000", "qca,ar9344";
  11
  12         aliases {
  13                 led-boot = &led_power;
  14                 led-failsafe = &led_power;
  15                 led-running = &led_power;
  16                 led-upgrade = &led_power;
  17         };
  18
  19         keys {
  20                 compatible = "gpio-keys";
  21
  22                 pinctrl-names = "default";
  23                 pinctrl-0 = <&jtag_disable_pins>;
  24
  25                 reset {
  26                         label = "Reset button";
  27                         linux,code = <KEY_RESTART>;
  28                         gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
  29                         debounce-interval = <60>;
  30                 };
  31
  32                 wps {
  33                         label = "WPS button";
  34                         linux,code = <KEY_WPS_BUTTON>;
  35                         gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
  36                         debounce-interval = <60>;
  37                 };
  38         };
  39
  40         leds {
  41                 compatible = "gpio-leds";
  42
  43                 led_power: power {
  44                         label = "amber:power";
  45                         gpios = <&gpio 2 GPIO_ACTIVE_LOW>,
  46                                 <&gpio 4 GPIO_ACTIVE_LOW>;
  47                         default-state = "on";
  48                 };
  49
  50                 wlan2g {
  51                         label = "blue:wlan";
  52                         gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
  53                         linux,default-trigger = "phy0tpt";
  54                 };
  55
  56                 wps_white {
  57                         label = "white:wps";
  58                         gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
  59                 };
  60         };
  61 };
  62
  63 &ref {
  64         clock-frequency = <25000000>;
  65 };
  66
  67 &spi {
  68         status = "okay";
  69
  70         flash@0 {
  71                 compatible = "jedec,spi-nor";
  72                 reg = <0>;
  73                 spi-max-frequency = <25000000>;
  74
  75                 partitions {
  76                         compatible = "fixed-partitions";
  77                         #address-cells = <1>;
  78                         #size-cells = <1>;
  79
  80                         uboot: partition@0 {
  81                                 label = "u-boot";
  82                                 reg = <0x000000 0x040000>;
  83                                 read-only;
  84                         };
  85
  86                         partition@40000 {
  87                                 label = "u-boot-env";
  88                                 reg = <0x040000 0x010000>;
  89                                 read-only;
  90                         };
  91
  92                         partition@50000 {
  93                                 compatible = "denx,uimage";
  94                                 label = "firmware";
  95                                 reg = <0x050000 0x07a0000>;
  96                         };
  97
  98                         art: partition@7f0000 {
  99                                 label = "art";
 100                                 reg = <0x7f0000 0x010000>;
 101                                 read-only;
 102                         };
 103                 };
 104         };
 105 };
 106
 107 &usb {
 108         status = "okay";
 109         #address-cells = <1>;
 110         #size-cells = <0>;
 111
 112         hub_port1: port@1 {
 113                 reg = <1>;
 114                 #trigger-source-cells = <0>;
 115         };
 116 };
 117
 118 &usb_phy {
 119         status = "okay";
 120 };
 121
 122 &pcie {
 123         status = "okay";
 124
 125         ath9k: wifi@0,0 {
 126                 compatible = "pci168c,0030";
 127                 reg = <0x0000 0 0 0 0>;
 128                 nvmem-cells = <&macaddr_art_5002>;
 129                 nvmem-cell-names = "mac-address";
 130                 #gpio-cells = <2>;
 131                 gpio-controller;
 132         };
 133 };
 134
 135 &mdio0 {
 136         status = "okay";
 137
 138         phy-mask = <0>;
 139
 140         phy0: ethernet-phy@0 {
 141                 reg = <0>;
 142                 phy-mode = "rgmii";
 143                 qca,ar8327-initvals = <
 144                         0x04 0x07600000 /* PORT0 PAD MODE CTRL */
 145                         0x10 0x81000080 /* POWER_ON_STRAP */
 146                         0x50 0xcc35cc35 /* LED_CTRL0 */
 147                         0x54 0xca35ca35 /* LED_CTRL1 */
 148                         0x58 0xc935c935 /* LED_CTRL2 */
 149                         0x5c 0x03ffff00 /* LED_CTRL3 */
 150                         0x7c 0x0000007e /* PORT0_STATUS */
 151                 >;
 152         };
 153 };
 154
 155 &eth0 {
 156         #address-cells = <1>;
 157         #size-cells = <0>;
 158         status = "okay";
 159
 160         /* default for ar934x, except for 1000M */
 161         pll-data = <0x06000000 0x00000101 0x00001616>;
 162
 163         nvmem-cells = <&macaddr_art_0>;
 164         nvmem-cell-names = "mac-address";
 165
 166         phy-mode = "rgmii";
 167         phy-handle = <&phy0>;
 168
 169         aliases {
 170                 ag0 = &eth1;
 171         };
 172
 173         port@0 {
 174                 compatible = "swconfig,port";
 175                 reg = <0>;
 176                 swconfig,segment = "lan";
 177                 swconfig,portmap = <1 1>;
 178         };
 179
 180         port@1 {
 181                 compatible = "swconfig,port";
 182                 reg = <1>;
 183                 swconfig,segment = "lan";
 184                 swconfig,portmap = <2 2>;
 185         };
 186
 187         port@2 {
 188                 compatible = "swconfig,port";
 189                 reg = <2>;
 190                 swconfig,segment = "lan";
 191                 swconfig,portmap = <3 3>;
 192         };
 193
 194         port@3 {
 195                 compatible = "swconfig,port";
 196                 reg = <3>;
 197                 swconfig,segment = "lan";
 198                 swconfig,portmap = <4 4>;
 199         };
 200
 201         port@4 {
 202                 compatible = "swconfig,port";
 203                 reg = <4>;
 204                 swconfig,segment = "wan";
 205                 swconfig,portmap = <5 5>;
 206         };
 207 };
 208
 209 &wmac {
 210         status = "okay";
 211
 212         mtd-cal-data = <&art 0x1000>;
 213 };
 214
 215 &art {
 216         compatible = "nvmem-cells";
 217         #address-cells = <1>;
 218         #size-cells = <1>;
 219
 220         macaddr_art_0: macaddr@0 {
 221                 reg = <0x0 0x6>;
 222         };
 223
 224         macaddr_art_5002: macaddr@5002 {
 225                 reg = <0x5002 0x6>;
 226         };
 227 };