target/linux/ath79/dts/ar934x.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include "ath79.dtsi"
   4
   5 / {
   6         compatible = "qca,ar9340";
   7
   8         #address-cells = <1>;
   9         #size-cells = <1>;
  10
  11         chosen {
  12                 bootargs = "console=ttyS0,115200";
  13         };
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "mips,mips74Kc";
  22                         clocks = <&pll ATH79_CLK_CPU>;
  23                         reg = <0>;
  24                 };
  25         };
  26
  27         clocks {
  28                 #address-cells = <1>;
  29                 #size-cells = <1>;
  30                 ranges;
  31
  32                 ref: ref {
  33                         #clock-cells = <0>;
  34                         compatible = "fixed-clock";
  35                         clock-output-names = "ref";
  36                 };
  37         };
  38
  39         ahb: ahb {
  40                 compatible = "simple-bus";
  41                 ranges;
  42
  43                 #address-cells = <1>;
  44                 #size-cells = <1>;
  45
  46                 apb: apb {
  47                         compatible = "simple-bus";
  48                         ranges;
  49
  50                         #address-cells = <1>;
  51                         #size-cells = <1>;
  52
  53                         ddr_ctrl: memory-controller@18000000 {
  54                                 compatible = "qca,ar9340-ddr-controller",
  55                                                 "qca,ar7240-ddr-controller";
  56                                 reg = <0x18000000 0x12c>;
  57
  58                                 #qca,ddr-wb-channel-cells = <1>;
  59                         };
  60
  61                         uart: uart@18020000 {
  62                                 compatible = "ns16550a";
  63                                 reg = <0x18020000 0x2c>;
  64
  65                                 interrupts = <3>;
  66
  67                                 clocks = <&pll ATH79_CLK_REF>;
  68                                 clock-names = "uart";
  69
  70                                 reg-io-width = <4>;
  71                                 reg-shift = <2>;
  72                                 no-loopback-test;
  73
  74                                 status = "disabled";
  75                         };
  76
  77                         gpio: gpio@18040000 {
  78                                 compatible = "qca,ar9340-gpio";
  79                                 reg = <0x18040000 0x2c>;
  80
  81                                 interrupts = <2>;
  82                                 ngpios = <23>;
  83
  84                                 gpio-controller;
  85                                 #gpio-cells = <2>;
  86
  87                                 interrupt-controller;
  88                                 #interrupt-cells = <2>;
  89                         };
  90
  91                         pinmux: pinmux@1804002c {
  92                                 compatible = "pinctrl-single";
  93
  94                                 reg = <0x1804002c 0x44>;
  95
  96                                 #size-cells = <0>;
  97
  98                                 pinctrl-single,bit-per-mux;
  99                                 pinctrl-single,register-width = <32>;
 100                                 pinctrl-single,function-mask = <0x1>;
 101                                 #pinctrl-cells = <2>;
 102
 103                                 jtag_disable_pins: pinmux_jtag_disable_pins {
 104                                         pinctrl-single,bits = <0x40 0x2 0x2>;
 105                                 };
 106                         };
 107
 108                         pll: pll-controller@18050000 {
 109                                 compatible = "qca,ar9340-pll", "syscon";
 110                                 reg = <0x18050000 0x4c>;
 111
 112                                 #clock-cells = <1>;
 113                                 clocks = <&ref>;
 114                                 clock-names = "ref";
 115                                 clock-output-names = "cpu", "ddr", "ahb";
 116                         };
 117
 118                         wdt: wdt@18060008 {
 119                                 compatible = "qca,ar9340-wdt", "qca,ar7130-wdt";
 120                                 reg = <0x18060008 0x8>;
 121
 122                                 interrupts = <4>;
 123
 124                                 clocks = <&pll ATH79_CLK_AHB>;
 125                                 clock-names = "wdt";
 126                         };
 127
 128                         rst: reset-controller@1806001c {
 129                                 compatible = "qca,ar9340-reset", "qca,ar7100-reset";
 130                                 reg = <0x1806001c 0x4>;
 131
 132                                 #reset-cells = <1>;
 133                         };
 134
 135                         hs_uart: uart@18500000 {
 136                                 compatible = "qca,ar9330-uart";
 137                                 reg = <0x18500000 0x14>;
 138
 139                                 interrupts = <6>;
 140                                 interrupt-parent = <&miscintc>;
 141
 142                                 clocks = <&pll ATH79_CLK_UART1>;
 143                                 clock-names = "uart";
 144
 145                                 status = "disabled";
 146                         };
 147                 };
 148
 149                 gmac: gmac@18070000 {
 150                         compatible = "qca,ar9340-gmac";
 151                         reg = <0x18070000 0x14>;
 152                 };
 153
 154                 wmac: wmac@18100000 {
 155                         compatible = "qca,ar9340-wmac";
 156                         reg = <0x18100000 0x20000>;
 157
 158                         status = "disabled";
 159                 };
 160
 161                 usb: usb@1b000000 {
 162                         compatible = "generic-ehci";
 163                         reg = <0x1b000000 0x1d8>;
 164
 165                         interrupts = <3>;
 166                         resets = <&rst 5>;
 167                         reset-names = "usb-host";
 168
 169                         has-transaction-translator;
 170                         caps-offset = <0x100>;
 171
 172                         phy-names = "usb-phy";
 173                         phys = <&usb_phy>;
 174
 175                         status = "disabled";
 176                 };
 177
 178                 nand: nand@1b000200 {
 179                         compatible = "qca,ar934x-nand";
 180                         reg = <0x1b000200 0xb8>;
 181
 182                         interrupts = <21>;
 183                         interrupt-parent = <&miscintc>;
 184
 185                         resets = <&rst 14>;
 186                         reset-names = "nand";
 187
 188                         nand-ecc-mode = "hw";
 189
 190                         #address-cells = <1>;
 191                         #size-cells = <0>;
 192
 193                         status = "disabled";
 194                 };
 195
 196                 spi: spi@1f000000 {
 197                         compatible = "qca,ar934x-spi";
 198                         reg = <0x1f000000 0x1c>;
 199
 200                         clocks = <&pll ATH79_CLK_AHB>;
 201
 202                         #address-cells = <1>;
 203                         #size-cells = <0>;
 204
 205                         status = "disabled";
 206                 };
 207         };
 208
 209         usb_phy: usb-phy {
 210                 compatible = "qca,ar9340-usb-phy", "qca,ar7200-usb-phy";
 211
 212                 reset-names = "usb-phy-analog", "usb-phy", "usb-suspend-override";
 213                 resets = <&rst 11>, <&rst 4>, <&rst 3>;
 214
 215                 #phy-cells = <0>;
 216
 217                 status = "disabled";
 218         };
 219 };
 220
 221 &mdio0 {
 222         compatible = "qca,ar9340-mdio";
 223 };
 224
 225 &eth0 {
 226         compatible = "qca,ar9340-eth", "syscon";
 227
 228         pll-data = <0x16000000 0x00000101 0x00001616>;
 229         pll-reg = <0x4 0x2c 17>;
 230         pll-handle = <&pll>;
 231         resets = <&rst 9>, <&rst 22>;
 232         reset-names = "mac", "mdio";
 233         clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
 234         clock-names = "eth", "mdio";
 235 };
 236
 237 &mdio1 {
 238         status = "okay";
 239
 240         compatible = "qca,ar9340-mdio";
 241         resets = <&rst 23>;
 242         reset-names = "mdio";
 243         builtin-switch;
 244
 245         builtin_switch: switch0@1f {
 246                 compatible = "qca,ar8229";
 247
 248                 reg = <0x1f>;
 249                 resets = <&rst 8>;
 250                 reset-names = "switch";
 251                 phy-mode = "gmii";
 252                 qca,mib-poll-interval = <500>;
 253                 qca,phy4-mii-enable;
 254
 255                 mdio-bus {
 256                         #address-cells = <1>;
 257                         #size-cells = <0>;
 258
 259                         swphy0: ethernet-phy@0 {
 260                                 reg = <0>;
 261                                 phy-mode = "mii";
 262                         };
 263
 264                         swphy4: ethernet-phy@4 {
 265                                 reg = <4>;
 266                                 phy-mode = "mii";
 267                         };
 268                 };
 269         };
 270 };
 271
 272 &eth1 {
 273         compatible = "qca,ar9340-eth", "syscon";
 274
 275         resets = <&rst 13>;
 276         reset-names = "mac";
 277         clocks = <&pll ATH79_CLK_AHB>, <&pll ATH79_CLK_AHB>;
 278         clock-names = "eth", "mdio";
 279         phy-mode = "gmii";
 280
 281         fixed-link {
 282                 speed = <1000>;
 283                 full-duplex;
 284         };
 285 };