ath79: add support for ZTE MF281
[openwrt/openwrt.git] / target / linux / ath79 / dts / qca9563_zte_mf281.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 // Copyright (c) 2021 Cezary Jackiewicz
3 // Copyright (c) 2021, 2022 Lech Perczak
4 // Copyright (c) 2022 David Bauer <mail@david-bauer.net>
5
6 #include "qca956x.dtsi"
7
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/leds/common.h>
11
12 / {
13 model = "ZTE MF281";
14 compatible = "zte,mf281", "qca,qca9563";
15
16 aliases {
17 led-boot = &led_debug;
18 led-failsafe = &led_debug;
19 led-running = &led_debug;
20 led-upgrade = &led_debug;
21 label-mac-device = &eth0;
22 };
23
24 leds {
25 compatible = "gpio-leds";
26 pinctrl-names = "default";
27 pinctrl-0 = <&enable_wlan_led_gpio>;
28
29 /* Hidden SMD LED below signal strength LEDs.
30 * Visible through slits underside of the case.
31 */
32 led_debug: debug {
33 label = "green:debug";
34 gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
35 default-state = "on";
36 };
37 };
38
39 keys {
40 compatible = "gpio-keys";
41
42 reset {
43 label = "reset";
44 linux,code = <KEY_RESTART>;
45 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
46 debounce-interval = <60>;
47 };
48
49 wps {
50 label = "wps";
51 linux,code = <KEY_WPS_BUTTON>;
52 gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
53 debounce-interval = <60>;
54 };
55 };
56
57 /* This GPIO is used to reset whole board _including_ the modem */
58 gpio-restart {
59 compatible = "gpio-restart";
60 gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
61 active-delay = <3000>;
62 inactive-delay = <1000>;
63 };
64 };
65
66 &spi {
67 status = "okay";
68
69 flash@0 {
70 compatible = "jedec,spi-nor";
71 reg = <0>;
72 spi-max-frequency = <25000000>;
73
74 partitions {
75 compatible = "fixed-partitions";
76 #address-cells = <1>;
77 #size-cells = <1>;
78
79 partition@0 {
80 label = "u-boot";
81 reg = <0x0 0xa0000>;
82 read-only;
83 };
84
85 partition@80000 {
86 label = "u-boot-env";
87 reg = <0xa0000 0x20000>;
88 read-only;
89 };
90 };
91 };
92
93 flash@1 {
94 compatible = "spi-nand";
95 reg = <1>;
96 spi-max-frequency = <25000000>;
97
98 partitions {
99 compatible = "fixed-partitions";
100 #address-cells = <1>;
101 #size-cells = <1>;
102
103 partition@0 {
104 label = "fota-flag";
105 reg = <0x000000 0xa0000>;
106 read-only;
107 };
108
109 partition@a0000 {
110 label = "art";
111 reg = <0xa0000 0x80000>;
112 read-only;
113
114 compatible = "nvmem-cells";
115 #address-cells = <1>;
116 #size-cells = <1>;
117
118 cal_caldata_1000: cal@1000 {
119 reg = <0x1000 0x440>;
120 };
121
122 cal_caldata_5000: cal@5000 {
123 reg = <0x5000 0x2f20>;
124 };
125 };
126
127 partition@120000 {
128 label = "mac";
129 reg = <0x120000 0x80000>;
130 read-only;
131
132 compatible = "nvmem-cells";
133 #address-cells = <1>;
134 #size-cells = <1>;
135
136 macaddr_mac_0: macaddr@0 {
137 reg = <0x0 0x6>;
138 };
139 };
140
141 partition@1a0000 {
142 label = "reserved2";
143 reg = <0x1a0000 0xc0000>;
144 read-only;
145 };
146
147 partition@260000 {
148 label = "cfg-param";
149 reg = <0x260000 0x400000>;
150 read-only;
151 };
152
153 partition@660000 {
154 label = "log";
155 reg = <0x660000 0x400000>;
156 read-only;
157 };
158
159 partition@a60000 {
160 label = "oops";
161 reg = <0xa60000 0xa0000>;
162 read-only;
163 };
164
165 partition@b00000 {
166 label = "reserved3";
167 reg = <0xb00000 0x500000>;
168 read-only;
169 };
170
171 partition@1000000 {
172 label = "web";
173 reg = <0x1000000 0x800000>;
174 read-only;
175 };
176
177 partition@1800000 {
178 label = "firmware";
179 reg = <0x1800000 0x1d00000>;
180
181 compatible = "fixed-partitions";
182 #address-cells = <1>;
183 #size-cells = <1>;
184
185 partition@0 {
186 label = "kernel";
187 reg = <0x0 0x600000>;
188 };
189
190 partition@600000 {
191 label = "ubi";
192 reg = <0x600000 0x1700000>;
193 };
194 };
195
196 partition@3500000 {
197 label = "data";
198 reg = <0x3500000 0x1900000>;
199 read-only;
200 };
201
202 partition@4e00000 {
203 label = "fota";
204 reg = <0x4e00000 0x3200000>;
205 read-only;
206 };
207 };
208 };
209 };
210
211 &mdio0 {
212 status = "okay";
213
214 phy0: ethernet-phy@0 {
215 reg = <0>;
216 phy-mode = "sgmii";
217
218 qca,ar8327-initvals = <
219 0x04 0x00080080 /* PORT0 PAD MODE CTRL */
220 0x7c 0x0000007e /* PORT0_STATUS */
221 >;
222 };
223 };
224
225 &eth0 {
226 status = "okay";
227
228 phy-mode = "sgmii";
229 phy-handle = <&phy0>;
230
231 nvmem-cells = <&macaddr_mac_0>;
232 nvmem-cell-names = "mac-address";
233 };
234
235 &pcie {
236 status = "okay";
237
238 wifi@0,0 {
239 compatible = "qcom,ath10k";
240 reg = <0x0 0 0 0 0>;
241
242 nvmem-cells = <&macaddr_mac_0>, <&cal_caldata_5000>;
243 nvmem-cell-names = "mac-address", "pre-calibration";
244 mac-address-increment = <1>;
245 };
246 };
247
248 &pinmux {
249 enable_wlan_led_gpio: pinmux_wlan_led_gpio {
250 pinctrl-single,bits = <0x10 0x0 0xff000000>;
251 };
252 };
253
254 &wmac {
255 status = "okay";
256
257 nvmem-cells = <&macaddr_mac_0>, <&cal_caldata_1000>;
258 nvmem-cell-names = "mac-address", "calibration";
259 };
260
261 &usb_phy0 {
262 status = "okay";
263 };
264
265 &usb0 {
266 status = "okay";
267 };
268
269 &usb_phy1 {
270 status = "okay";
271 };
272
273 &usb1 {
274 status = "okay";
275 };