projects / openwrt / openwrt.git / blob
? search:


ddc6d6d882c2619787eef7392e06101dbd3ce61e
[openwrt/openwrt.git] / target / linux / ath79 / files / drivers / mtd / nand / raw / ar934x_nand.c
1 /*
2 * Driver for the built-in NAND controller of the Atheros AR934x SoCs
3 *
4 * Copyright (C) 2011-2013 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 */
10
11 #include <linux/version.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/module.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/mtd/mtd.h>
17 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,9,0)
18 #include <linux/mtd/nand.h>
19 #endif
20 #include <linux/mtd/rawnand.h>
21 #include <linux/mtd/partitions.h>
22 #include <linux/platform_device.h>
23 #include <linux/delay.h>
24 #include <linux/slab.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27 #include <linux/reset.h>
28
29 #define AR934X_NFC_DRIVER_NAME "ar934x-nand"
30
31 #define AR934X_NFC_REG_CMD 0x00
32 #define AR934X_NFC_REG_CTRL 0x04
33 #define AR934X_NFC_REG_STATUS 0x08
34 #define AR934X_NFC_REG_INT_MASK 0x0c
35 #define AR934X_NFC_REG_INT_STATUS 0x10
36 #define AR934X_NFC_REG_ECC_CTRL 0x14
37 #define AR934X_NFC_REG_ECC_OFFSET 0x18
38 #define AR934X_NFC_REG_ADDR0_0 0x1c
39 #define AR934X_NFC_REG_ADDR0_1 0x24
40 #define AR934X_NFC_REG_ADDR1_0 0x20
41 #define AR934X_NFC_REG_ADDR1_1 0x28
42 #define AR934X_NFC_REG_SPARE_SIZE 0x30
43 #define AR934X_NFC_REG_PROTECT 0x38
44 #define AR934X_NFC_REG_LOOKUP_EN 0x40
45 #define AR934X_NFC_REG_LOOKUP(_x) (0x44 + (_i) * 4)
46 #define AR934X_NFC_REG_DMA_ADDR 0x64
47 #define AR934X_NFC_REG_DMA_COUNT 0x68
48 #define AR934X_NFC_REG_DMA_CTRL 0x6c
49 #define AR934X_NFC_REG_MEM_CTRL 0x80
50 #define AR934X_NFC_REG_DATA_SIZE 0x84
51 #define AR934X_NFC_REG_READ_STATUS 0x88
52 #define AR934X_NFC_REG_TIME_SEQ 0x8c
53 #define AR934X_NFC_REG_TIMINGS_ASYN 0x90
54 #define AR934X_NFC_REG_TIMINGS_SYN 0x94
55 #define AR934X_NFC_REG_FIFO_DATA 0x98
56 #define AR934X_NFC_REG_TIME_MODE 0x9c
57 #define AR934X_NFC_REG_DMA_ADDR_OFFS 0xa0
58 #define AR934X_NFC_REG_FIFO_INIT 0xb0
59 #define AR934X_NFC_REG_GEN_SEQ_CTRL 0xb4
60
61 #define AR934X_NFC_CMD_CMD_SEQ_S 0
62 #define AR934X_NFC_CMD_CMD_SEQ_M 0x3f
63 #define AR934X_NFC_CMD_SEQ_1C 0x00
64 #define AR934X_NFC_CMD_SEQ_ERASE 0x0e
65 #define AR934X_NFC_CMD_SEQ_12 0x0c
66 #define AR934X_NFC_CMD_SEQ_1C1AXR 0x21
67 #define AR934X_NFC_CMD_SEQ_S 0x24
68 #define AR934X_NFC_CMD_SEQ_1C3AXR 0x27
69 #define AR934X_NFC_CMD_SEQ_1C5A1CXR 0x2a
70 #define AR934X_NFC_CMD_SEQ_18 0x32
71 #define AR934X_NFC_CMD_INPUT_SEL_SIU 0
72 #define AR934X_NFC_CMD_INPUT_SEL_DMA BIT(6)
73 #define AR934X_NFC_CMD_ADDR_SEL_0 0
74 #define AR934X_NFC_CMD_ADDR_SEL_1 BIT(7)
75 #define AR934X_NFC_CMD_CMD0_S 8
76 #define AR934X_NFC_CMD_CMD0_M 0xff
77 #define AR934X_NFC_CMD_CMD1_S 16
78 #define AR934X_NFC_CMD_CMD1_M 0xff
79 #define AR934X_NFC_CMD_CMD2_S 24
80 #define AR934X_NFC_CMD_CMD2_M 0xff
81
82 #define AR934X_NFC_CTRL_ADDR_CYCLE0_M 0x7
83 #define AR934X_NFC_CTRL_ADDR_CYCLE0_S 0
84 #define AR934X_NFC_CTRL_SPARE_EN BIT(3)
85 #define AR934X_NFC_CTRL_INT_EN BIT(4)
86 #define AR934X_NFC_CTRL_ECC_EN BIT(5)
87 #define AR934X_NFC_CTRL_BLOCK_SIZE_S 6
88 #define AR934X_NFC_CTRL_BLOCK_SIZE_M 0x3
89 #define AR934X_NFC_CTRL_BLOCK_SIZE_32 0
90 #define AR934X_NFC_CTRL_BLOCK_SIZE_64 1
91 #define AR934X_NFC_CTRL_BLOCK_SIZE_128 2
92 #define AR934X_NFC_CTRL_BLOCK_SIZE_256 3
93 #define AR934X_NFC_CTRL_PAGE_SIZE_S 8
94 #define AR934X_NFC_CTRL_PAGE_SIZE_M 0x7
95 #define AR934X_NFC_CTRL_PAGE_SIZE_256 0
96 #define AR934X_NFC_CTRL_PAGE_SIZE_512 1
97 #define AR934X_NFC_CTRL_PAGE_SIZE_1024 2
98 #define AR934X_NFC_CTRL_PAGE_SIZE_2048 3
99 #define AR934X_NFC_CTRL_PAGE_SIZE_4096 4
100 #define AR934X_NFC_CTRL_PAGE_SIZE_8192 5
101 #define AR934X_NFC_CTRL_PAGE_SIZE_16384 6
102 #define AR934X_NFC_CTRL_CUSTOM_SIZE_EN BIT(11)
103 #define AR934X_NFC_CTRL_IO_WIDTH_8BITS 0
104 #define AR934X_NFC_CTRL_IO_WIDTH_16BITS BIT(12)
105 #define AR934X_NFC_CTRL_LOOKUP_EN BIT(13)
106 #define AR934X_NFC_CTRL_PROT_EN BIT(14)
107 #define AR934X_NFC_CTRL_WORK_MODE_ASYNC 0
108 #define AR934X_NFC_CTRL_WORK_MODE_SYNC BIT(15)
109 #define AR934X_NFC_CTRL_ADDR0_AUTO_INC BIT(16)
110 #define AR934X_NFC_CTRL_ADDR1_AUTO_INC BIT(17)
111 #define AR934X_NFC_CTRL_ADDR_CYCLE1_M 0x7
112 #define AR934X_NFC_CTRL_ADDR_CYCLE1_S 18
113 #define AR934X_NFC_CTRL_SMALL_PAGE BIT(21)
114
115 #define AR934X_NFC_DMA_CTRL_DMA_START BIT(7)
116 #define AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE 0
117 #define AR934X_NFC_DMA_CTRL_DMA_DIR_READ BIT(6)
118 #define AR934X_NFC_DMA_CTRL_DMA_MODE_SG BIT(5)
119 #define AR934X_NFC_DMA_CTRL_DMA_BURST_S 2
120 #define AR934X_NFC_DMA_CTRL_DMA_BURST_0 0
121 #define AR934X_NFC_DMA_CTRL_DMA_BURST_1 1
122 #define AR934X_NFC_DMA_CTRL_DMA_BURST_2 2
123 #define AR934X_NFC_DMA_CTRL_DMA_BURST_3 3
124 #define AR934X_NFC_DMA_CTRL_DMA_BURST_4 4
125 #define AR934X_NFC_DMA_CTRL_DMA_BURST_5 5
126 #define AR934X_NFC_DMA_CTRL_ERR_FLAG BIT(1)
127 #define AR934X_NFC_DMA_CTRL_DMA_READY BIT(0)
128
129 #define AR934X_NFC_INT_DEV_RDY(_x) BIT(4 + (_x))
130 #define AR934X_NFC_INT_CMD_END BIT(1)
131
132 #define AR934X_NFC_ECC_CTRL_ERR_THRES_S 8
133 #define AR934X_NFC_ECC_CTRL_ERR_THRES_M 0x1f
134 #define AR934X_NFC_ECC_CTRL_ECC_CAP_S 5
135 #define AR934X_NFC_ECC_CTRL_ECC_CAP_M 0x7
136 #define AR934X_NFC_ECC_CTRL_ECC_CAP_2 0
137 #define AR934X_NFC_ECC_CTRL_ECC_CAP_4 1
138 #define AR934X_NFC_ECC_CTRL_ECC_CAP_6 2
139 #define AR934X_NFC_ECC_CTRL_ECC_CAP_8 3
140 #define AR934X_NFC_ECC_CTRL_ECC_CAP_10 4
141 #define AR934X_NFC_ECC_CTRL_ECC_CAP_12 5
142 #define AR934X_NFC_ECC_CTRL_ECC_CAP_14 6
143 #define AR934X_NFC_ECC_CTRL_ECC_CAP_16 7
144 #define AR934X_NFC_ECC_CTRL_ERR_OVER BIT(2)
145 #define AR934X_NFC_ECC_CTRL_ERR_UNCORRECT BIT(1)
146 #define AR934X_NFC_ECC_CTRL_ERR_CORRECT BIT(0)
147
148 #define AR934X_NFC_ECC_OFFS_OFSET_M 0xffff
149
150 /* default timing values */
151 #define AR934X_NFC_TIME_SEQ_DEFAULT 0x7fff
152 #define AR934X_NFC_TIMINGS_ASYN_DEFAULT 0x22
153 #define AR934X_NFC_TIMINGS_SYN_DEFAULT 0xf
154
155 #define AR934X_NFC_ID_BUF_SIZE 8
156 #define AR934X_NFC_DEV_READY_TIMEOUT 25 /* msecs */
157 #define AR934X_NFC_DMA_READY_TIMEOUT 25 /* msecs */
158 #define AR934X_NFC_DONE_TIMEOUT 1000
159 #define AR934X_NFC_DMA_RETRIES 20
160
161 #define AR934X_NFC_USE_IRQ true
162 #define AR934X_NFC_IRQ_MASK AR934X_NFC_INT_DEV_RDY(0)
163
164 #define AR934X_NFC_GENSEQ_SMALL_PAGE_READ 0x30043
165
166 #undef AR934X_NFC_DEBUG_DATA
167 #undef AR934X_NFC_DEBUG
168
169 struct mtd_info;
170 struct mtd_partition;
171 struct ar934x_nfc;
172
173 struct ar934x_nfc {
174 struct nand_chip nand_chip;
175 struct device *parent;
176 void __iomem *base;
177 bool swap_dma;
178 int irq;
179 wait_queue_head_t irq_waitq;
180
181 bool spurious_irq_expected;
182 u32 irq_status;
183
184 u32 ctrl_reg;
185 u32 ecc_ctrl_reg;
186 u32 ecc_offset_reg;
187 u32 ecc_thres;
188 u32 ecc_oob_pos;
189
190 bool small_page;
191 unsigned int addr_count0;
192 unsigned int addr_count1;
193
194 u8 *buf;
195 dma_addr_t buf_dma;
196 unsigned int buf_size;
197 int buf_index;
198
199 bool read_id;
200
201 int erase1_page_addr;
202
203 int rndout_page_addr;
204 int rndout_read_cmd;
205
206 int seqin_page_addr;
207 int seqin_column;
208 int seqin_read_cmd;
209
210 struct reset_control *rst;
211 };
212
213 static inline __printf(2, 3)
214 void _nfc_dbg(struct ar934x_nfc *nfc, const char *fmt, ...)
215 {
216 }
217
218 #ifdef AR934X_NFC_DEBUG
219 #define nfc_dbg(_nfc, fmt, ...) \
220 dev_info((_nfc)->parent, fmt, ##__VA_ARGS__)
221 #else
222 #define nfc_dbg(_nfc, fmt, ...) \
223 _nfc_dbg((_nfc), fmt, ##__VA_ARGS__)
224 #endif /* AR934X_NFC_DEBUG */
225
226 #ifdef AR934X_NFC_DEBUG_DATA
227 static void nfc_debug_data(const char *label, void *data, int len)
228 {
229 print_hex_dump(KERN_WARNING, label, DUMP_PREFIX_OFFSET, 16, 1,
230 data, len, 0);
231 }
232 #else
233 static inline void nfc_debug_data(const char *label, void *data, int len) {}
234 #endif /* AR934X_NFC_DEBUG_DATA */
235
236 static void ar934x_nfc_restart(struct ar934x_nfc *nfc);
237
238 static inline bool is_all_ff(u8 *buf, int len)
239 {
240 while (len--)
241 if (buf[len] != 0xff)
242 return false;
243
244 return true;
245 }
246
247 static inline void ar934x_nfc_wr(struct ar934x_nfc *nfc, unsigned reg, u32 val)
248 {
249 __raw_writel(val, nfc->base + reg);
250 }
251
252 static inline u32 ar934x_nfc_rr(struct ar934x_nfc *nfc, unsigned reg)
253 {
254 return __raw_readl(nfc->base + reg);
255 }
256
257 static inline struct ar934x_nfc *mtd_to_ar934x_nfc(struct mtd_info *mtd)
258 {
259 struct nand_chip *chip = mtd_to_nand(mtd);
260
261 return container_of(chip, struct ar934x_nfc, nand_chip);
262 }
263
264 static struct mtd_info *ar934x_nfc_to_mtd(struct ar934x_nfc *nfc)
265 {
266 return nand_to_mtd(&nfc->nand_chip);
267 }
268
269 static inline bool ar934x_nfc_use_irq(struct ar934x_nfc *nfc)
270 {
271 return AR934X_NFC_USE_IRQ;
272 }
273
274 static inline void ar934x_nfc_write_cmd_reg(struct ar934x_nfc *nfc, u32 cmd_reg)
275 {
276 wmb();
277
278 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CMD, cmd_reg);
279 /* flush write */
280 ar934x_nfc_rr(nfc, AR934X_NFC_REG_CMD);
281 }
282
283 static bool __ar934x_nfc_dev_ready(struct ar934x_nfc *nfc)
284 {
285 u32 status;
286
287 status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_STATUS);
288 return (status & 0xff) == 0xff;
289 }
290
291 static inline bool __ar934x_nfc_is_dma_ready(struct ar934x_nfc *nfc)
292 {
293 u32 status;
294
295 status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_DMA_CTRL);
296 return (status & AR934X_NFC_DMA_CTRL_DMA_READY) != 0;
297 }
298
299 static int ar934x_nfc_wait_dev_ready(struct ar934x_nfc *nfc)
300 {
301 unsigned long timeout;
302
303 timeout = jiffies + msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT);
304 do {
305 if (__ar934x_nfc_dev_ready(nfc))
306 return 0;
307 } while time_before(jiffies, timeout);
308
309 nfc_dbg(nfc, "timeout waiting for device ready, status:%08x int:%08x\n",
310 ar934x_nfc_rr(nfc, AR934X_NFC_REG_STATUS),
311 ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS));
312 return -ETIMEDOUT;
313 }
314
315 static int ar934x_nfc_wait_dma_ready(struct ar934x_nfc *nfc)
316 {
317 unsigned long timeout;
318
319 timeout = jiffies + msecs_to_jiffies(AR934X_NFC_DMA_READY_TIMEOUT);
320 do {
321 if (__ar934x_nfc_is_dma_ready(nfc))
322 return 0;
323 } while time_before(jiffies, timeout);
324
325 nfc_dbg(nfc, "timeout waiting for DMA ready, dma_ctrl:%08x\n",
326 ar934x_nfc_rr(nfc, AR934X_NFC_REG_DMA_CTRL));
327 return -ETIMEDOUT;
328 }
329
330 static int ar934x_nfc_wait_irq(struct ar934x_nfc *nfc)
331 {
332 long timeout;
333 int ret;
334
335 timeout = wait_event_timeout(nfc->irq_waitq,
336 (nfc->irq_status & AR934X_NFC_IRQ_MASK) != 0,
337 msecs_to_jiffies(AR934X_NFC_DEV_READY_TIMEOUT));
338
339 ret = 0;
340 if (!timeout) {
341 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_MASK, 0);
342 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
343 /* flush write */
344 ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
345
346 nfc_dbg(nfc,
347 "timeout waiting for interrupt, status:%08x\n",
348 nfc->irq_status);
349 ret = -ETIMEDOUT;
350 }
351
352 nfc->irq_status = 0;
353 return ret;
354 }
355
356 static int ar934x_nfc_wait_done(struct ar934x_nfc *nfc)
357 {
358 int ret;
359
360 if (ar934x_nfc_use_irq(nfc))
361 ret = ar934x_nfc_wait_irq(nfc);
362 else
363 ret = ar934x_nfc_wait_dev_ready(nfc);
364
365 if (ret)
366 return ret;
367
368 return ar934x_nfc_wait_dma_ready(nfc);
369 }
370
371 static int ar934x_nfc_alloc_buf(struct ar934x_nfc *nfc, unsigned size)
372 {
373 nfc->buf = dma_alloc_coherent(nfc->parent, size,
374 &nfc->buf_dma, GFP_KERNEL);
375 if (nfc->buf == NULL) {
376 dev_err(nfc->parent, "no memory for DMA buffer\n");
377 return -ENOMEM;
378 }
379
380 nfc->buf_size = size;
381 nfc_dbg(nfc, "buf:%p size:%u\n", nfc->buf, nfc->buf_size);
382
383 return 0;
384 }
385
386 static void ar934x_nfc_free_buf(struct ar934x_nfc *nfc)
387 {
388 dma_free_coherent(nfc->parent, nfc->buf_size, nfc->buf, nfc->buf_dma);
389 }
390
391 static void ar934x_nfc_get_addr(struct ar934x_nfc *nfc, int column,
392 int page_addr, u32 *addr0, u32 *addr1)
393 {
394 u32 a0, a1;
395
396 a0 = 0;
397 a1 = 0;
398
399 if (column == -1) {
400 /* ERASE1 */
401 a0 = (page_addr & 0xffff) << 16;
402 a1 = (page_addr >> 16) & 0xf;
403 } else if (page_addr != -1) {
404 /* SEQIN, READ0, etc.. */
405
406 /* TODO: handle 16bit bus width */
407 if (nfc->small_page) {
408 a0 = column & 0xff;
409 a0 |= (page_addr & 0xff) << 8;
410 a0 |= ((page_addr >> 8) & 0xff) << 16;
411 a0 |= ((page_addr >> 16) & 0xff) << 24;
412 } else {
413 a0 = column & 0x0FFF;
414 a0 |= (page_addr & 0xffff) << 16;
415
416 if (nfc->addr_count0 > 4)
417 a1 = (page_addr >> 16) & 0xf;
418 }
419 }
420
421 *addr0 = a0;
422 *addr1 = a1;
423 }
424
425 static void ar934x_nfc_send_cmd(struct ar934x_nfc *nfc, unsigned command)
426 {
427 u32 cmd_reg;
428
429 cmd_reg = AR934X_NFC_CMD_INPUT_SEL_SIU | AR934X_NFC_CMD_ADDR_SEL_0 |
430 AR934X_NFC_CMD_SEQ_1C;
431 cmd_reg |= (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
432
433 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
434 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
435
436 ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
437 ar934x_nfc_wait_dev_ready(nfc);
438 }
439
440 static int ar934x_nfc_do_rw_command(struct ar934x_nfc *nfc, int column,
441 int page_addr, int len, u32 cmd_reg,
442 u32 ctrl_reg, bool write)
443 {
444 u32 addr0, addr1;
445 u32 dma_ctrl;
446 int dir;
447 int err;
448 int retries = 0;
449
450 WARN_ON(len & 3);
451
452 if (WARN_ON(len > nfc->buf_size))
453 dev_err(nfc->parent, "len=%d > buf_size=%d", len,
454 nfc->buf_size);
455
456 if (write) {
457 dma_ctrl = AR934X_NFC_DMA_CTRL_DMA_DIR_WRITE;
458 dir = DMA_TO_DEVICE;
459 } else {
460 dma_ctrl = AR934X_NFC_DMA_CTRL_DMA_DIR_READ;
461 dir = DMA_FROM_DEVICE;
462 }
463
464 ar934x_nfc_get_addr(nfc, column, page_addr, &addr0, &addr1);
465
466 dma_ctrl |= AR934X_NFC_DMA_CTRL_DMA_START |
467 (AR934X_NFC_DMA_CTRL_DMA_BURST_3 <<
468 AR934X_NFC_DMA_CTRL_DMA_BURST_S);
469
470 cmd_reg |= AR934X_NFC_CMD_INPUT_SEL_DMA | AR934X_NFC_CMD_ADDR_SEL_0;
471 ctrl_reg |= AR934X_NFC_CTRL_INT_EN;
472
473 nfc_dbg(nfc, "%s a0:%08x a1:%08x len:%x cmd:%08x dma:%08x ctrl:%08x\n",
474 (write) ? "write" : "read",
475 addr0, addr1, len, cmd_reg, dma_ctrl, ctrl_reg);
476
477 retry:
478 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
479 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_0, addr0);
480 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_1, addr1);
481 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_ADDR, nfc->buf_dma);
482 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_COUNT, len);
483 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DATA_SIZE, len);
484 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, ctrl_reg);
485 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_CTRL, dma_ctrl);
486 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ECC_CTRL, nfc->ecc_ctrl_reg);
487 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ECC_OFFSET, nfc->ecc_offset_reg);
488
489 if (ar934x_nfc_use_irq(nfc)) {
490 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_MASK,
491 AR934X_NFC_IRQ_MASK);
492 /* flush write */
493 ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_MASK);
494 }
495
496 ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
497 err = ar934x_nfc_wait_done(nfc);
498 if (err) {
499 dev_dbg(nfc->parent, "%s operation stuck at page %d\n",
500 (write) ? "write" : "read", page_addr);
501
502 ar934x_nfc_restart(nfc);
503 if (retries++ < AR934X_NFC_DMA_RETRIES)
504 goto retry;
505
506 dev_err(nfc->parent, "%s operation failed on page %d\n",
507 (write) ? "write" : "read", page_addr);
508 }
509
510 return err;
511 }
512
513 static int ar934x_nfc_send_readid(struct ar934x_nfc *nfc, unsigned command)
514 {
515 u32 cmd_reg;
516 int err;
517
518 nfc_dbg(nfc, "readid, cmd:%02x\n", command);
519
520 cmd_reg = AR934X_NFC_CMD_SEQ_1C1AXR;
521 cmd_reg |= (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
522
523 err = ar934x_nfc_do_rw_command(nfc, -1, -1, AR934X_NFC_ID_BUF_SIZE,
524 cmd_reg, nfc->ctrl_reg, false);
525
526 nfc_debug_data("[id] ", nfc->buf, AR934X_NFC_ID_BUF_SIZE);
527
528 return err;
529 }
530
531 static int ar934x_nfc_send_read(struct ar934x_nfc *nfc, unsigned command,
532 int column, int page_addr, int len)
533 {
534 u32 cmd_reg;
535 int err;
536
537 nfc_dbg(nfc, "read, column=%d page=%d len=%d\n",
538 column, page_addr, len);
539
540 cmd_reg = (command & AR934X_NFC_CMD_CMD0_M) << AR934X_NFC_CMD_CMD0_S;
541
542 if (nfc->small_page) {
543 cmd_reg |= AR934X_NFC_CMD_SEQ_18;
544 } else {
545 cmd_reg |= NAND_CMD_READSTART << AR934X_NFC_CMD_CMD1_S;
546 cmd_reg |= AR934X_NFC_CMD_SEQ_1C5A1CXR;
547 }
548
549 err = ar934x_nfc_do_rw_command(nfc, column, page_addr, len,
550 cmd_reg, nfc->ctrl_reg, false);
551
552 nfc_debug_data("[data] ", nfc->buf, len);
553
554 return err;
555 }
556
557 static void ar934x_nfc_send_erase(struct ar934x_nfc *nfc, unsigned command,
558 int column, int page_addr)
559 {
560 u32 addr0, addr1;
561 u32 ctrl_reg;
562 u32 cmd_reg;
563
564 ar934x_nfc_get_addr(nfc, column, page_addr, &addr0, &addr1);
565
566 ctrl_reg = nfc->ctrl_reg;
567 if (nfc->small_page) {
568 /* override number of address cycles for the erase command */
569 ctrl_reg &= ~(AR934X_NFC_CTRL_ADDR_CYCLE0_M <<
570 AR934X_NFC_CTRL_ADDR_CYCLE0_S);
571 ctrl_reg &= ~(AR934X_NFC_CTRL_ADDR_CYCLE1_M <<
572 AR934X_NFC_CTRL_ADDR_CYCLE1_S);
573 ctrl_reg &= ~(AR934X_NFC_CTRL_SMALL_PAGE);
574 ctrl_reg |= (nfc->addr_count0 + 1) <<
575 AR934X_NFC_CTRL_ADDR_CYCLE0_S;
576 }
577
578 cmd_reg = NAND_CMD_ERASE1 << AR934X_NFC_CMD_CMD0_S;
579 cmd_reg |= command << AR934X_NFC_CMD_CMD1_S;
580 cmd_reg |= AR934X_NFC_CMD_SEQ_ERASE;
581
582 nfc_dbg(nfc, "erase page %d, a0:%08x a1:%08x cmd:%08x ctrl:%08x\n",
583 page_addr, addr0, addr1, cmd_reg, ctrl_reg);
584
585 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
586 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, ctrl_reg);
587 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_0, addr0);
588 ar934x_nfc_wr(nfc, AR934X_NFC_REG_ADDR0_1, addr1);
589
590 ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
591 ar934x_nfc_wait_dev_ready(nfc);
592 }
593
594 static int ar934x_nfc_send_write(struct ar934x_nfc *nfc, unsigned command,
595 int column, int page_addr, int len)
596 {
597 u32 cmd_reg;
598
599 nfc_dbg(nfc, "write, column=%d page=%d len=%d\n",
600 column, page_addr, len);
601
602 nfc_debug_data("[data] ", nfc->buf, len);
603
604 cmd_reg = NAND_CMD_SEQIN << AR934X_NFC_CMD_CMD0_S;
605 cmd_reg |= command << AR934X_NFC_CMD_CMD1_S;
606 cmd_reg |= AR934X_NFC_CMD_SEQ_12;
607
608 return ar934x_nfc_do_rw_command(nfc, column, page_addr, len,
609 cmd_reg, nfc->ctrl_reg, true);
610 }
611
612 static void ar934x_nfc_read_status(struct ar934x_nfc *nfc)
613 {
614 u32 cmd_reg;
615 u32 status;
616
617 cmd_reg = NAND_CMD_STATUS << AR934X_NFC_CMD_CMD0_S;
618 cmd_reg |= AR934X_NFC_CMD_SEQ_S;
619
620 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
621 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
622
623 ar934x_nfc_write_cmd_reg(nfc, cmd_reg);
624 ar934x_nfc_wait_dev_ready(nfc);
625
626 status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_READ_STATUS);
627
628 nfc_dbg(nfc, "read status, cmd:%08x status:%02x\n",
629 cmd_reg, (status & 0xff));
630
631 if (nfc->swap_dma)
632 nfc->buf[0 ^ 3] = status;
633 else
634 nfc->buf[0] = status;
635 }
636
637 static void ar934x_nfc_cmdfunc(struct nand_chip *nand, unsigned int command,
638 int column, int page_addr)
639 {
640 struct mtd_info *mtd = nand_to_mtd(nand);
641 struct ar934x_nfc *nfc = nand->priv;
642
643 nfc->read_id = false;
644 if (command != NAND_CMD_PAGEPROG)
645 nfc->buf_index = 0;
646
647 switch (command) {
648 case NAND_CMD_RESET:
649 ar934x_nfc_send_cmd(nfc, command);
650 break;
651
652 case NAND_CMD_READID:
653 nfc->read_id = true;
654 ar934x_nfc_send_readid(nfc, command);
655 break;
656
657 case NAND_CMD_READ0:
658 case NAND_CMD_READ1:
659 if (nfc->small_page) {
660 ar934x_nfc_send_read(nfc, command, column, page_addr,
661 mtd->writesize + mtd->oobsize);
662 } else {
663 ar934x_nfc_send_read(nfc, command, 0, page_addr,
664 mtd->writesize + mtd->oobsize);
665 nfc->buf_index = column;
666 nfc->rndout_page_addr = page_addr;
667 nfc->rndout_read_cmd = command;
668 }
669 break;
670
671 case NAND_CMD_READOOB:
672 if (nfc->small_page)
673 ar934x_nfc_send_read(nfc, NAND_CMD_READOOB,
674 column, page_addr,
675 mtd->oobsize);
676 else
677 ar934x_nfc_send_read(nfc, NAND_CMD_READ0,
678 mtd->writesize, page_addr,
679 mtd->oobsize);
680 break;
681
682 case NAND_CMD_RNDOUT:
683 if (WARN_ON(nfc->small_page))
684 break;
685
686 /* emulate subpage read */
687 ar934x_nfc_send_read(nfc, nfc->rndout_read_cmd, 0,
688 nfc->rndout_page_addr,
689 mtd->writesize + mtd->oobsize);
690 nfc->buf_index = column;
691 break;
692
693 case NAND_CMD_ERASE1:
694 nfc->erase1_page_addr = page_addr;
695 break;
696
697 case NAND_CMD_ERASE2:
698 ar934x_nfc_send_erase(nfc, command, -1, nfc->erase1_page_addr);
699 break;
700
701 case NAND_CMD_STATUS:
702 ar934x_nfc_read_status(nfc);
703 break;
704
705 case NAND_CMD_SEQIN:
706 if (nfc->small_page) {
707 /* output read command */
708 if (column >= mtd->writesize) {
709 column -= mtd->writesize;
710 nfc->seqin_read_cmd = NAND_CMD_READOOB;
711 } else if (column < 256) {
712 nfc->seqin_read_cmd = NAND_CMD_READ0;
713 } else {
714 column -= 256;
715 nfc->seqin_read_cmd = NAND_CMD_READ1;
716 }
717 } else {
718 nfc->seqin_read_cmd = NAND_CMD_READ0;
719 }
720 nfc->seqin_column = column;
721 nfc->seqin_page_addr = page_addr;
722 break;
723
724 case NAND_CMD_PAGEPROG:
725 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,9,0)
726 if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) {
727 #else
728 if (nand->ecc.mode == NAND_ECC_HW) {
729 #endif
730 /* the data is already written */
731 break;
732 }
733
734 if (nfc->small_page)
735 ar934x_nfc_send_cmd(nfc, nfc->seqin_read_cmd);
736
737 ar934x_nfc_send_write(nfc, command, nfc->seqin_column,
738 nfc->seqin_page_addr,
739 nfc->buf_index);
740 break;
741
742 default:
743 dev_err(nfc->parent,
744 "unsupported command: %x, column:%d page_addr=%d\n",
745 command, column, page_addr);
746 break;
747 }
748 }
749
750 static int ar934x_nfc_dev_ready(struct nand_chip *chip)
751 {
752 struct ar934x_nfc *nfc = chip->priv;
753
754 return __ar934x_nfc_dev_ready(nfc);
755 }
756
757 static u8 ar934x_nfc_read_byte(struct nand_chip *chip)
758 {
759 struct ar934x_nfc *nfc = chip->priv;
760 u8 data;
761
762 WARN_ON(nfc->buf_index >= nfc->buf_size);
763
764 if (nfc->swap_dma || nfc->read_id)
765 data = nfc->buf[nfc->buf_index ^ 3];
766 else
767 data = nfc->buf[nfc->buf_index];
768
769 nfc->buf_index++;
770
771 return data;
772 }
773
774 static void ar934x_nfc_write_buf(struct nand_chip *chip, const u8 *buf, int len)
775 {
776 struct ar934x_nfc *nfc = chip->priv;
777 int i;
778
779 WARN_ON(nfc->buf_index + len > nfc->buf_size);
780
781 if (nfc->swap_dma) {
782 for (i = 0; i < len; i++) {
783 nfc->buf[nfc->buf_index ^ 3] = buf[i];
784 nfc->buf_index++;
785 }
786 } else {
787 for (i = 0; i < len; i++) {
788 nfc->buf[nfc->buf_index] = buf[i];
789 nfc->buf_index++;
790 }
791 }
792 }
793
794 static void ar934x_nfc_read_buf(struct nand_chip *chip, u8 *buf, int len)
795 {
796 struct ar934x_nfc *nfc = chip->priv;
797 int buf_index;
798 int i;
799
800 WARN_ON(nfc->buf_index + len > nfc->buf_size);
801
802 buf_index = nfc->buf_index;
803
804 if (nfc->swap_dma || nfc->read_id) {
805 for (i = 0; i < len; i++) {
806 buf[i] = nfc->buf[buf_index ^ 3];
807 buf_index++;
808 }
809 } else {
810 for (i = 0; i < len; i++) {
811 buf[i] = nfc->buf[buf_index];
812 buf_index++;
813 }
814 }
815
816 nfc->buf_index = buf_index;
817 }
818
819 static inline void ar934x_nfc_enable_hwecc(struct ar934x_nfc *nfc)
820 {
821 nfc->ctrl_reg |= AR934X_NFC_CTRL_ECC_EN;
822 nfc->ctrl_reg &= ~AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
823 }
824
825 static inline void ar934x_nfc_disable_hwecc(struct ar934x_nfc *nfc)
826 {
827 nfc->ctrl_reg &= ~AR934X_NFC_CTRL_ECC_EN;
828 nfc->ctrl_reg |= AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
829 }
830
831 static int ar934x_nfc_read_oob(struct nand_chip *chip,
832 int page)
833 {
834 struct ar934x_nfc *nfc = chip->priv;
835 struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);
836 int err;
837
838 nfc_dbg(nfc, "read_oob: page:%d\n", page);
839
840 err = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, mtd->writesize, page,
841 mtd->oobsize);
842 if (err)
843 return err;
844
845 memcpy(chip->oob_poi, nfc->buf, mtd->oobsize);
846
847 return 0;
848 }
849
850 static int ar934x_nfc_write_oob(struct nand_chip *chip,
851 int page)
852 {
853 struct ar934x_nfc *nfc = chip->priv;
854 struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);
855 nfc_dbg(nfc, "write_oob: page:%d\n", page);
856
857 memcpy(nfc->buf, chip->oob_poi, mtd->oobsize);
858
859 return ar934x_nfc_send_write(nfc, NAND_CMD_PAGEPROG, mtd->writesize,
860 page, mtd->oobsize);
861 }
862
863 static int ar934x_nfc_read_page_raw(
864 struct nand_chip *chip, u8 *buf,
865 int oob_required, int page)
866 {
867 struct ar934x_nfc *nfc = chip->priv;
868 struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);
869 int len;
870 int err;
871
872 nfc_dbg(nfc, "read_page_raw: page:%d oob:%d\n", page, oob_required);
873
874 len = mtd->writesize;
875 if (oob_required)
876 len += mtd->oobsize;
877
878 err = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, 0, page, len);
879 if (err)
880 return err;
881
882 memcpy(buf, nfc->buf, mtd->writesize);
883
884 if (oob_required)
885 memcpy(chip->oob_poi, &nfc->buf[mtd->writesize], mtd->oobsize);
886
887 return 0;
888 }
889
890 static int ar934x_nfc_read_page(struct nand_chip *chip,
891 u8 *buf, int oob_required, int page)
892 {
893 struct ar934x_nfc *nfc = chip->priv;
894 struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);
895 u32 ecc_ctrl;
896 int max_bitflips = 0;
897 bool ecc_failed;
898 bool ecc_corrected;
899 int err;
900
901 nfc_dbg(nfc, "read_page: page:%d oob:%d\n", page, oob_required);
902
903 ar934x_nfc_enable_hwecc(nfc);
904 err = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, 0, page,
905 mtd->writesize);
906 ar934x_nfc_disable_hwecc(nfc);
907
908 if (err)
909 return err;
910
911 /* TODO: optimize to avoid memcpy */
912 memcpy(buf, nfc->buf, mtd->writesize);
913
914 /* read the ECC status */
915 ecc_ctrl = ar934x_nfc_rr(nfc, AR934X_NFC_REG_ECC_CTRL);
916 ecc_failed = ecc_ctrl & AR934X_NFC_ECC_CTRL_ERR_UNCORRECT;
917 ecc_corrected = ecc_ctrl & AR934X_NFC_ECC_CTRL_ERR_CORRECT;
918
919 if (oob_required || ecc_failed) {
920 err = ar934x_nfc_send_read(nfc, NAND_CMD_READ0, mtd->writesize,
921 page, mtd->oobsize);
922 if (err)
923 return err;
924
925 if (oob_required)
926 memcpy(chip->oob_poi, nfc->buf, mtd->oobsize);
927 }
928
929 if (ecc_failed) {
930 /*
931 * The hardware ECC engine reports uncorrectable errors
932 * on empty pages. Check the ECC bytes and the data. If
933 * both contains 0xff bytes only, dont report a failure.
934 *
935 * TODO: prebuild a buffer with 0xff bytes and use memcmp
936 * for better performance?
937 */
938 if (!is_all_ff(&nfc->buf[nfc->ecc_oob_pos], chip->ecc.total) ||
939 !is_all_ff(buf, mtd->writesize))
940 mtd->ecc_stats.failed++;
941 } else if (ecc_corrected) {
942 /*
943 * The hardware does not report the exact count of the
944 * corrected bitflips, use assumptions based on the
945 * threshold.
946 */
947 if (ecc_ctrl & AR934X_NFC_ECC_CTRL_ERR_OVER) {
948 /*
949 * The number of corrected bitflips exceeds the
950 * threshold. Assume the maximum.
951 */
952 max_bitflips = chip->ecc.strength * chip->ecc.steps;
953 } else {
954 max_bitflips = nfc->ecc_thres * chip->ecc.steps;
955 }
956
957 mtd->ecc_stats.corrected += max_bitflips;
958 }
959
960 return max_bitflips;
961 }
962
963 static int ar934x_nfc_write_page_raw(
964 struct nand_chip *chip, const u8 *buf,
965 int oob_required, int page)
966 {
967 struct ar934x_nfc *nfc = chip->priv;
968 struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);
969 int len;
970
971 nfc_dbg(nfc, "write_page_raw: page:%d oob:%d\n", page, oob_required);
972
973 memcpy(nfc->buf, buf, mtd->writesize);
974 len = mtd->writesize;
975
976 if (oob_required) {
977 memcpy(&nfc->buf[mtd->writesize], chip->oob_poi, mtd->oobsize);
978 len += mtd->oobsize;
979 }
980
981 return ar934x_nfc_send_write(nfc, NAND_CMD_PAGEPROG, 0, page, len);
982 }
983
984 static int ar934x_nfc_write_page(struct nand_chip *chip,
985 const u8 *buf, int oob_required, int page)
986 {
987 struct ar934x_nfc *nfc = chip->priv;
988 struct mtd_info *mtd = ar934x_nfc_to_mtd(nfc);
989 int err;
990
991 nfc_dbg(nfc, "write_page: page:%d oob:%d\n", page, oob_required);
992
993 /* write OOB first */
994 if (oob_required &&
995 !is_all_ff(chip->oob_poi, mtd->oobsize)) {
996 err = ar934x_nfc_write_oob(chip, page);
997 if (err)
998 return err;
999 }
1000
1001 /* TODO: optimize to avoid memcopy */
1002 memcpy(nfc->buf, buf, mtd->writesize);
1003
1004 ar934x_nfc_enable_hwecc(nfc);
1005 err = ar934x_nfc_send_write(nfc, NAND_CMD_PAGEPROG, 0, page,
1006 mtd->writesize);
1007 ar934x_nfc_disable_hwecc(nfc);
1008
1009 return err;
1010 }
1011
1012 static int ar934x_nfc_hw_reset_assert(struct ar934x_nfc *nfc)
1013 {
1014 int err;
1015
1016 err = reset_control_assert(nfc->rst);
1017 udelay(250);
1018 return err;
1019 }
1020
1021 static int ar934x_nfc_hw_reset_deassert(struct ar934x_nfc *nfc)
1022 {
1023 int err;
1024
1025 err = reset_control_deassert(nfc->rst);
1026 udelay(250);
1027 return err;
1028 }
1029
1030 static int ar934x_nfc_hw_init(struct ar934x_nfc *nfc)
1031 {
1032 ar934x_nfc_hw_reset_assert(nfc);
1033 ar934x_nfc_hw_reset_deassert(nfc);
1034 /*
1035 * setup timings
1036 * TODO: make it configurable via platform data or DT
1037 */
1038 ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIME_SEQ,
1039 AR934X_NFC_TIME_SEQ_DEFAULT);
1040 ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIMINGS_ASYN,
1041 AR934X_NFC_TIMINGS_ASYN_DEFAULT);
1042 ar934x_nfc_wr(nfc, AR934X_NFC_REG_TIMINGS_SYN,
1043 AR934X_NFC_TIMINGS_SYN_DEFAULT);
1044
1045 /* disable WP on all chips, and select chip 0 */
1046 ar934x_nfc_wr(nfc, AR934X_NFC_REG_MEM_CTRL, 0xff00);
1047
1048 ar934x_nfc_wr(nfc, AR934X_NFC_REG_DMA_ADDR_OFFS, 0);
1049
1050 /* initialize Control register */
1051 nfc->ctrl_reg = AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
1052 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
1053
1054 if (nfc->small_page) {
1055 /* Setup generic sequence register for small page reads. */
1056 ar934x_nfc_wr(nfc, AR934X_NFC_REG_GEN_SEQ_CTRL,
1057 AR934X_NFC_GENSEQ_SMALL_PAGE_READ);
1058 }
1059
1060 return 0;
1061 }
1062
1063 static void ar934x_nfc_restart(struct ar934x_nfc *nfc)
1064 {
1065 u32 ctrl_reg;
1066
1067 ctrl_reg = nfc->ctrl_reg;
1068 ar934x_nfc_hw_init(nfc);
1069 nfc->ctrl_reg = ctrl_reg;
1070
1071 ar934x_nfc_send_cmd(nfc, NAND_CMD_RESET);
1072 }
1073
1074 static irqreturn_t ar934x_nfc_irq_handler(int irq, void *data)
1075 {
1076 struct ar934x_nfc *nfc = data;
1077 u32 status;
1078
1079 status = ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
1080
1081 ar934x_nfc_wr(nfc, AR934X_NFC_REG_INT_STATUS, 0);
1082 /* flush write */
1083 ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_STATUS);
1084
1085 status &= ar934x_nfc_rr(nfc, AR934X_NFC_REG_INT_MASK);
1086 if (status) {
1087 nfc_dbg(nfc, "got IRQ, status:%08x\n", status);
1088
1089 nfc->irq_status = status;
1090 nfc->spurious_irq_expected = true;
1091 wake_up(&nfc->irq_waitq);
1092 } else {
1093 if (nfc->spurious_irq_expected)
1094 nfc->spurious_irq_expected = false;
1095 else
1096 dev_warn(nfc->parent, "spurious interrupt\n");
1097 }
1098
1099 return IRQ_HANDLED;
1100 }
1101
1102 static int ar934x_nfc_init_tail(struct mtd_info *mtd)
1103 {
1104 struct ar934x_nfc *nfc = mtd_to_ar934x_nfc(mtd);
1105 struct nand_chip *chip = &nfc->nand_chip;
1106 u64 chipsize = nanddev_target_size(&chip->base);
1107 u32 ctrl;
1108 u32 t;
1109 int err;
1110
1111 switch (mtd->oobsize) {
1112 case 16:
1113 case 64:
1114 case 128:
1115 ar934x_nfc_wr(nfc, AR934X_NFC_REG_SPARE_SIZE, mtd->oobsize);
1116 break;
1117
1118 default:
1119 dev_err(nfc->parent, "unsupported OOB size: %d bytes\n",
1120 mtd->oobsize);
1121 return -ENXIO;
1122 }
1123
1124 ctrl = AR934X_NFC_CTRL_CUSTOM_SIZE_EN;
1125
1126 switch (mtd->erasesize / mtd->writesize) {
1127 case 32:
1128 t = AR934X_NFC_CTRL_BLOCK_SIZE_32;
1129 break;
1130
1131 case 64:
1132 t = AR934X_NFC_CTRL_BLOCK_SIZE_64;
1133 break;
1134
1135 case 128:
1136 t = AR934X_NFC_CTRL_BLOCK_SIZE_128;
1137 break;
1138
1139 case 256:
1140 t = AR934X_NFC_CTRL_BLOCK_SIZE_256;
1141 break;
1142
1143 default:
1144 dev_err(nfc->parent, "unsupported block size: %u\n",
1145 mtd->erasesize / mtd->writesize);
1146 return -ENXIO;
1147 }
1148
1149 ctrl |= t << AR934X_NFC_CTRL_BLOCK_SIZE_S;
1150
1151 switch (mtd->writesize) {
1152 case 256:
1153 nfc->small_page = 1;
1154 t = AR934X_NFC_CTRL_PAGE_SIZE_256;
1155 break;
1156
1157 case 512:
1158 nfc->small_page = 1;
1159 t = AR934X_NFC_CTRL_PAGE_SIZE_512;
1160 break;
1161
1162 case 1024:
1163 t = AR934X_NFC_CTRL_PAGE_SIZE_1024;
1164 break;
1165
1166 case 2048:
1167 t = AR934X_NFC_CTRL_PAGE_SIZE_2048;
1168 break;
1169
1170 case 4096:
1171 t = AR934X_NFC_CTRL_PAGE_SIZE_4096;
1172 break;
1173
1174 case 8192:
1175 t = AR934X_NFC_CTRL_PAGE_SIZE_8192;
1176 break;
1177
1178 case 16384:
1179 t = AR934X_NFC_CTRL_PAGE_SIZE_16384;
1180 break;
1181
1182 default:
1183 dev_err(nfc->parent, "unsupported write size: %d bytes\n",
1184 mtd->writesize);
1185 return -ENXIO;
1186 }
1187
1188 ctrl |= t << AR934X_NFC_CTRL_PAGE_SIZE_S;
1189
1190 if (nfc->small_page) {
1191 ctrl |= AR934X_NFC_CTRL_SMALL_PAGE;
1192
1193 if (chipsize > (32 << 20)) {
1194 nfc->addr_count0 = 4;
1195 nfc->addr_count1 = 3;
1196 } else if (chipsize > (2 << 16)) {
1197 nfc->addr_count0 = 3;
1198 nfc->addr_count1 = 2;
1199 } else {
1200 nfc->addr_count0 = 2;
1201 nfc->addr_count1 = 1;
1202 }
1203 } else {
1204 if (chipsize > (128 << 20)) {
1205 nfc->addr_count0 = 5;
1206 nfc->addr_count1 = 3;
1207 } else if (chipsize > (8 << 16)) {
1208 nfc->addr_count0 = 4;
1209 nfc->addr_count1 = 2;
1210 } else {
1211 nfc->addr_count0 = 3;
1212 nfc->addr_count1 = 1;
1213 }
1214 }
1215
1216 ctrl |= nfc->addr_count0 << AR934X_NFC_CTRL_ADDR_CYCLE0_S;
1217 ctrl |= nfc->addr_count1 << AR934X_NFC_CTRL_ADDR_CYCLE1_S;
1218
1219 nfc->ctrl_reg = ctrl;
1220 ar934x_nfc_wr(nfc, AR934X_NFC_REG_CTRL, nfc->ctrl_reg);
1221
1222 ar934x_nfc_free_buf(nfc);
1223 err = ar934x_nfc_alloc_buf(nfc, mtd->writesize + mtd->oobsize);
1224
1225 return err;
1226 }
1227
1228 static int ar934x_nfc_ooblayout_ecc(struct mtd_info *mtd, int section,
1229 struct mtd_oob_region *oobregion)
1230 {
1231 if (section)
1232 return -ERANGE;
1233
1234 oobregion->offset = 20;
1235 oobregion->length = 28;
1236
1237 return 0;
1238 }
1239
1240 static int ar934x_nfc_ooblayout_free(struct mtd_info *mtd, int section,
1241 struct mtd_oob_region *oobregion)
1242 {
1243 switch (section) {
1244 case 0:
1245 oobregion->offset = 4;
1246 oobregion->length = 16;
1247 return 0;
1248 case 1:
1249 oobregion->offset = 48;
1250 oobregion->length = 16;
1251 return 0;
1252 default:
1253 return -ERANGE;
1254 }
1255 }
1256
1257 static const struct mtd_ooblayout_ops ar934x_nfc_ecclayout_ops = {
1258 .ecc = ar934x_nfc_ooblayout_ecc,
1259 .free = ar934x_nfc_ooblayout_free,
1260 };
1261
1262 static int ar934x_nfc_setup_hwecc(struct ar934x_nfc *nfc)
1263 {
1264 struct nand_chip *nand = &nfc->nand_chip;
1265 struct mtd_info *mtd = nand_to_mtd(nand);
1266 u32 ecc_cap;
1267 u32 ecc_thres;
1268 struct mtd_oob_region oobregion;
1269
1270 switch (mtd->writesize) {
1271 case 2048:
1272 /*
1273 * Writing a subpage separately is not supported, because
1274 * the controller only does ECC on full-page accesses.
1275 */
1276 nand->options = NAND_NO_SUBPAGE_WRITE;
1277
1278 nand->ecc.size = 512;
1279 nand->ecc.bytes = 7;
1280 nand->ecc.strength = 4;
1281 mtd_set_ooblayout(mtd, &ar934x_nfc_ecclayout_ops);
1282 break;
1283
1284 default:
1285 dev_err(nfc->parent,
1286 "hardware ECC is not available for %d byte pages\n",
1287 mtd->writesize);
1288 return -EINVAL;
1289 }
1290
1291 BUG_ON(!mtd->ooblayout->ecc);
1292
1293 switch (nand->ecc.strength) {
1294 case 4:
1295 ecc_cap = AR934X_NFC_ECC_CTRL_ECC_CAP_4;
1296 ecc_thres = 4;
1297 break;
1298
1299 default:
1300 dev_err(nfc->parent, "unsupported ECC strength %u\n",
1301 nand->ecc.strength);
1302 return -EINVAL;
1303 }
1304
1305 nfc->ecc_thres = ecc_thres;
1306 mtd->ooblayout->ecc(mtd, 0, &oobregion);
1307 nfc->ecc_oob_pos = oobregion.offset;
1308
1309 nfc->ecc_ctrl_reg = ecc_cap << AR934X_NFC_ECC_CTRL_ECC_CAP_S;
1310 nfc->ecc_ctrl_reg |= ecc_thres << AR934X_NFC_ECC_CTRL_ERR_THRES_S;
1311
1312 nfc->ecc_offset_reg = mtd->writesize + nfc->ecc_oob_pos;
1313
1314 nand->ecc.read_page = ar934x_nfc_read_page;
1315 nand->ecc.read_page_raw = ar934x_nfc_read_page_raw;
1316 nand->ecc.write_page = ar934x_nfc_write_page;
1317 nand->ecc.write_page_raw = ar934x_nfc_write_page_raw;
1318 nand->ecc.read_oob = ar934x_nfc_read_oob;
1319 nand->ecc.write_oob = ar934x_nfc_write_oob;
1320
1321 return 0;
1322 }
1323
1324 static int ar934x_nfc_attach_chip(struct nand_chip *nand)
1325 {
1326 struct mtd_info *mtd = nand_to_mtd(nand);
1327 struct ar934x_nfc *nfc = nand_get_controller_data(nand);
1328 struct device *dev = mtd->dev.parent;
1329 int ret;
1330
1331 ret = ar934x_nfc_init_tail(mtd);
1332 if (ret)
1333 return ret;
1334
1335 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,9,0)
1336 if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) {
1337 #else
1338 if (nand->ecc.mode == NAND_ECC_HW) {
1339 #endif
1340 ret = ar934x_nfc_setup_hwecc(nfc);
1341 if (ret)
1342 return ret;
1343 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,9,0)
1344 } else if (nand->ecc.engine_type != NAND_ECC_ENGINE_TYPE_SOFT) {
1345 dev_err(dev, "unknown ECC mode %d\n", nand->ecc.engine_type);
1346 #else
1347 } else if (nand->ecc.mode != NAND_ECC_SOFT) {
1348 dev_err(dev, "unknown ECC mode %d\n", nand->ecc.mode);
1349 #endif
1350 return -EINVAL;
1351 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,9,0)
1352 } else if ((nand->ecc.algo != NAND_ECC_ALGO_BCH) &&
1353 (nand->ecc.algo != NAND_ECC_ALGO_HAMMING)) {
1354 #else
1355 } else if ((nand->ecc.algo != NAND_ECC_BCH) &&
1356 (nand->ecc.algo != NAND_ECC_HAMMING)) {
1357 #endif
1358 dev_err(dev, "unknown software ECC algo %d\n", nand->ecc.algo);
1359 return -EINVAL;
1360 }
1361
1362 return 0;
1363 }
1364
1365 static u64 ar934x_nfc_dma_mask = DMA_BIT_MASK(32);
1366
1367 static void ar934x_nfc_cmd_ctrl(struct nand_chip *chip, int dat,
1368 unsigned int ctrl)
1369 {
1370 WARN_ON(dat != NAND_CMD_NONE);
1371 }
1372
1373 static const struct nand_controller_ops ar934x_nfc_controller_ops = {
1374 .attach_chip = ar934x_nfc_attach_chip,
1375 };
1376
1377 static int ar934x_nfc_probe(struct platform_device *pdev)
1378 {
1379 struct ar934x_nfc *nfc;
1380 struct resource *res;
1381 struct mtd_info *mtd;
1382 struct nand_chip *nand;
1383 int ret;
1384
1385 pdev->dev.dma_mask = &ar934x_nfc_dma_mask;
1386 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
1387
1388 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1389 if (!res) {
1390 dev_err(&pdev->dev, "failed to get I/O memory\n");
1391 return -EINVAL;
1392 }
1393
1394 nfc = devm_kzalloc(&pdev->dev, sizeof(struct ar934x_nfc), GFP_KERNEL);
1395 if (!nfc) {
1396 dev_err(&pdev->dev, "failed to allocate driver data\n");
1397 return -ENOMEM;
1398 }
1399
1400 nfc->base = devm_ioremap_resource(&pdev->dev, res);
1401 if (IS_ERR(nfc->base)) {
1402 dev_err(&pdev->dev, "failed to remap I/O memory\n");
1403 return PTR_ERR(nfc->base);
1404 }
1405
1406 nfc->irq = platform_get_irq(pdev, 0);
1407 if (nfc->irq < 0) {
1408 dev_err(&pdev->dev, "no IRQ resource specified\n");
1409 return -EINVAL;
1410 }
1411
1412 init_waitqueue_head(&nfc->irq_waitq);
1413 ret = devm_request_irq(&pdev->dev, nfc->irq, ar934x_nfc_irq_handler,
1414 0, AR934X_NFC_DRIVER_NAME, nfc);
1415 if (ret) {
1416 dev_err(&pdev->dev, "devm_request_irq failed, err:%d\n", ret);
1417 return ret;
1418 }
1419
1420 nfc->rst = devm_reset_control_get(&pdev->dev, "nand");
1421 if (IS_ERR(nfc->rst)) {
1422 dev_err(&pdev->dev, "Failed to get reset\n");
1423 return PTR_ERR(nfc->rst);
1424 }
1425
1426 nfc->parent = &pdev->dev;
1427 nfc->swap_dma = of_property_read_bool(pdev->dev.of_node,
1428 "qca,nand-swap-dma");
1429
1430 nand = &nfc->nand_chip;
1431 mtd = nand_to_mtd(nand);
1432
1433 mtd->owner = THIS_MODULE;
1434 mtd->dev.parent = &pdev->dev;
1435 mtd->name = AR934X_NFC_DRIVER_NAME;
1436
1437 nand_set_controller_data(nand, nfc);
1438 nand_set_flash_node(nand, pdev->dev.of_node);
1439 nand->legacy.chip_delay = 25;
1440 nand->legacy.dev_ready = ar934x_nfc_dev_ready;
1441 nand->legacy.cmdfunc = ar934x_nfc_cmdfunc;
1442 nand->legacy.cmd_ctrl = ar934x_nfc_cmd_ctrl; /* dummy */
1443 nand->legacy.read_byte = ar934x_nfc_read_byte;
1444 nand->legacy.write_buf = ar934x_nfc_write_buf;
1445 nand->legacy.read_buf = ar934x_nfc_read_buf;
1446 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,9,0)
1447 nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; /* default */
1448 #else
1449 nand->ecc.mode = NAND_ECC_HW; /* default */
1450 #endif
1451 nand->priv = nfc;
1452 platform_set_drvdata(pdev, nfc);
1453
1454 ret = ar934x_nfc_alloc_buf(nfc, AR934X_NFC_ID_BUF_SIZE);
1455 if (ret)
1456 return ret;
1457
1458 ret = ar934x_nfc_hw_init(nfc);
1459 if (ret) {
1460 dev_err(&pdev->dev, "hardware init failed, err:%d\n", ret);
1461 goto err_free_buf;
1462 }
1463
1464 nand->legacy.dummy_controller.ops = &ar934x_nfc_controller_ops;
1465 ret = nand_scan(nand, 1);
1466 if (ret) {
1467 dev_err(&pdev->dev, "nand_scan failed, err:%d\n", ret);
1468 goto err_free_buf;
1469 }
1470
1471 ret = mtd_device_register(mtd, NULL, 0);
1472 if (ret) {
1473 dev_err(&pdev->dev, "unable to register mtd, err:%d\n", ret);
1474 goto err_free_buf;
1475 }
1476
1477 return 0;
1478
1479 err_free_buf:
1480 ar934x_nfc_free_buf(nfc);
1481 return ret;
1482 }
1483
1484 static int ar934x_nfc_remove(struct platform_device *pdev)
1485 {
1486 struct ar934x_nfc *nfc;
1487
1488 nfc = platform_get_drvdata(pdev);
1489 if (nfc) {
1490 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,8,0)
1491 mtd_device_unregister(nand_to_mtd(&nfc->nand_chip));
1492 nand_cleanup(&nfc->nand_chip);
1493 #else
1494 nand_release(&nfc->nand_chip);
1495 #endif
1496 ar934x_nfc_free_buf(nfc);
1497 }
1498
1499 return 0;
1500 }
1501
1502 static const struct of_device_id ar934x_nfc_match[] = {
1503 { .compatible = "qca," AR934X_NFC_DRIVER_NAME },
1504 {},
1505 };
1506
1507 MODULE_DEVICE_TABLE(of, ar934x_nfc_match);
1508
1509 static struct platform_driver ar934x_nfc_driver = {
1510 .probe = ar934x_nfc_probe,
1511 .remove = ar934x_nfc_remove,
1512 .driver = {
1513 .name = AR934X_NFC_DRIVER_NAME,
1514 .owner = THIS_MODULE,
1515 .of_match_table = ar934x_nfc_match,
1516 },
1517 };
1518
1519 module_platform_driver(ar934x_nfc_driver);
1520
1521 MODULE_LICENSE("GPL v2");
1522 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1523 MODULE_DESCRIPTION("Atheros AR934x NAND Flash Controller driver");
1524 MODULE_ALIAS("platform:" AR934X_NFC_DRIVER_NAME);
OpenWrt Source Repository