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[openwrt/openwrt.git] / target / linux / ath79 / files / drivers / net / ethernet / atheros / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include <linux/sizes.h>
15 #include <linux/of_net.h>
16 #include <linux/of_address.h>
17 #include <linux/of_platform.h>
18 #include "ag71xx.h"
19
20 #define AG71XX_DEFAULT_MSG_ENABLE \
21 (NETIF_MSG_DRV \
22 | NETIF_MSG_PROBE \
23 | NETIF_MSG_LINK \
24 | NETIF_MSG_TIMER \
25 | NETIF_MSG_IFDOWN \
26 | NETIF_MSG_IFUP \
27 | NETIF_MSG_RX_ERR \
28 | NETIF_MSG_TX_ERR)
29
30 static int ag71xx_msg_level = -1;
31
32 module_param_named(msg_level, ag71xx_msg_level, int, 0);
33 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
34
35 #define ETH_SWITCH_HEADER_LEN 2
36
37 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush);
38
39 static inline unsigned int ag71xx_max_frame_len(unsigned int mtu)
40 {
41 return ETH_SWITCH_HEADER_LEN + ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN;
42 }
43
44 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
45 {
46 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
47 ag->dev->name,
48 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
49 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
50 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
51
52 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
53 ag->dev->name,
54 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
55 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
56 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
57 }
58
59 static void ag71xx_dump_regs(struct ag71xx *ag)
60 {
61 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
62 ag->dev->name,
63 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
64 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
65 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
66 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
67 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
68 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
69 ag->dev->name,
70 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
71 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
72 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
73 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
74 ag->dev->name,
75 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
76 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
77 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
78 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
79 ag->dev->name,
80 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
81 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
82 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
83 }
84
85 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
86 {
87 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
88 ag->dev->name, label, intr,
89 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
90 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
91 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
92 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
93 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
94 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
95 }
96
97 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
98 {
99 struct ag71xx_ring *ring = &ag->tx_ring;
100 struct net_device *dev = ag->dev;
101 int ring_mask = BIT(ring->order) - 1;
102 u32 bytes_compl = 0, pkts_compl = 0;
103
104 while (ring->curr != ring->dirty) {
105 struct ag71xx_desc *desc;
106 u32 i = ring->dirty & ring_mask;
107
108 desc = ag71xx_ring_desc(ring, i);
109 if (!ag71xx_desc_empty(desc)) {
110 desc->ctrl = 0;
111 dev->stats.tx_errors++;
112 }
113
114 if (ring->buf[i].skb) {
115 bytes_compl += ring->buf[i].len;
116 pkts_compl++;
117 dev_kfree_skb_any(ring->buf[i].skb);
118 }
119 ring->buf[i].skb = NULL;
120 ring->dirty++;
121 }
122
123 /* flush descriptors */
124 wmb();
125
126 netdev_completed_queue(dev, pkts_compl, bytes_compl);
127 }
128
129 static void ag71xx_ring_tx_init(struct ag71xx *ag)
130 {
131 struct ag71xx_ring *ring = &ag->tx_ring;
132 int ring_size = BIT(ring->order);
133 int ring_mask = BIT(ring->order) - 1;
134 int i;
135
136 for (i = 0; i < ring_size; i++) {
137 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
138
139 desc->next = (u32) (ring->descs_dma +
140 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
141
142 desc->ctrl = DESC_EMPTY;
143 ring->buf[i].skb = NULL;
144 }
145
146 /* flush descriptors */
147 wmb();
148
149 ring->curr = 0;
150 ring->dirty = 0;
151 netdev_reset_queue(ag->dev);
152 }
153
154 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
155 {
156 struct ag71xx_ring *ring = &ag->rx_ring;
157 int ring_size = BIT(ring->order);
158 int i;
159
160 if (!ring->buf)
161 return;
162
163 for (i = 0; i < ring_size; i++)
164 if (ring->buf[i].rx_buf) {
165 dma_unmap_single(&ag->pdev->dev, ring->buf[i].dma_addr,
166 ag->rx_buf_size, DMA_FROM_DEVICE);
167 skb_free_frag(ring->buf[i].rx_buf);
168 }
169 }
170
171 static int ag71xx_buffer_size(struct ag71xx *ag)
172 {
173 return ag->rx_buf_size +
174 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
175 }
176
177 static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf,
178 int offset,
179 void *(*alloc)(unsigned int size))
180 {
181 struct ag71xx_ring *ring = &ag->rx_ring;
182 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]);
183 void *data;
184
185 data = alloc(ag71xx_buffer_size(ag));
186 if (!data)
187 return false;
188
189 buf->rx_buf = data;
190 buf->dma_addr = dma_map_single(&ag->pdev->dev, data, ag->rx_buf_size,
191 DMA_FROM_DEVICE);
192 desc->data = (u32) buf->dma_addr + offset;
193 return true;
194 }
195
196 static int ag71xx_ring_rx_init(struct ag71xx *ag)
197 {
198 struct ag71xx_ring *ring = &ag->rx_ring;
199 int ring_size = BIT(ring->order);
200 int ring_mask = BIT(ring->order) - 1;
201 unsigned int i;
202 int ret;
203
204 ret = 0;
205 for (i = 0; i < ring_size; i++) {
206 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
207
208 desc->next = (u32) (ring->descs_dma +
209 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
210
211 DBG("ag71xx: RX desc at %p, next is %08x\n",
212 desc, desc->next);
213 }
214
215 for (i = 0; i < ring_size; i++) {
216 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
217
218 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], ag->rx_buf_offset,
219 netdev_alloc_frag)) {
220 ret = -ENOMEM;
221 break;
222 }
223
224 desc->ctrl = DESC_EMPTY;
225 }
226
227 /* flush descriptors */
228 wmb();
229
230 ring->curr = 0;
231 ring->dirty = 0;
232
233 return ret;
234 }
235
236 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
237 {
238 struct ag71xx_ring *ring = &ag->rx_ring;
239 int ring_mask = BIT(ring->order) - 1;
240 unsigned int count;
241 int offset = ag->rx_buf_offset;
242
243 count = 0;
244 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
245 struct ag71xx_desc *desc;
246 unsigned int i;
247
248 i = ring->dirty & ring_mask;
249 desc = ag71xx_ring_desc(ring, i);
250
251 if (!ring->buf[i].rx_buf &&
252 !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset,
253 napi_alloc_frag))
254 break;
255
256 desc->ctrl = DESC_EMPTY;
257 count++;
258 }
259
260 /* flush descriptors */
261 wmb();
262
263 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
264
265 return count;
266 }
267
268 static int ag71xx_rings_init(struct ag71xx *ag)
269 {
270 struct ag71xx_ring *tx = &ag->tx_ring;
271 struct ag71xx_ring *rx = &ag->rx_ring;
272 int ring_size = BIT(tx->order) + BIT(rx->order);
273 int tx_size = BIT(tx->order);
274
275 tx->buf = kzalloc(ring_size * sizeof(*tx->buf), GFP_KERNEL);
276 if (!tx->buf)
277 return -ENOMEM;
278
279 tx->descs_cpu = dma_alloc_coherent(&ag->pdev->dev, ring_size * AG71XX_DESC_SIZE,
280 &tx->descs_dma, GFP_KERNEL);
281 if (!tx->descs_cpu) {
282 kfree(tx->buf);
283 tx->buf = NULL;
284 return -ENOMEM;
285 }
286
287 rx->buf = &tx->buf[tx_size];
288 rx->descs_cpu = ((void *)tx->descs_cpu) + tx_size * AG71XX_DESC_SIZE;
289 rx->descs_dma = tx->descs_dma + tx_size * AG71XX_DESC_SIZE;
290
291 ag71xx_ring_tx_init(ag);
292 return ag71xx_ring_rx_init(ag);
293 }
294
295 static void ag71xx_rings_free(struct ag71xx *ag)
296 {
297 struct ag71xx_ring *tx = &ag->tx_ring;
298 struct ag71xx_ring *rx = &ag->rx_ring;
299 int ring_size = BIT(tx->order) + BIT(rx->order);
300
301 if (tx->descs_cpu)
302 dma_free_coherent(&ag->pdev->dev, ring_size * AG71XX_DESC_SIZE,
303 tx->descs_cpu, tx->descs_dma);
304
305 kfree(tx->buf);
306
307 tx->descs_cpu = NULL;
308 rx->descs_cpu = NULL;
309 tx->buf = NULL;
310 rx->buf = NULL;
311 }
312
313 static void ag71xx_rings_cleanup(struct ag71xx *ag)
314 {
315 ag71xx_ring_rx_clean(ag);
316 ag71xx_ring_tx_clean(ag);
317 ag71xx_rings_free(ag);
318
319 netdev_reset_queue(ag->dev);
320 }
321
322 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
323 {
324 switch (ag->speed) {
325 case SPEED_1000:
326 return "1000";
327 case SPEED_100:
328 return "100";
329 case SPEED_10:
330 return "10";
331 }
332
333 return "?";
334 }
335
336 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
337 {
338 u32 t;
339
340 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
341 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
342
343 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
344
345 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
346 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
347 }
348
349 static void ag71xx_dma_reset(struct ag71xx *ag)
350 {
351 u32 val;
352 int i;
353
354 ag71xx_dump_dma_regs(ag);
355
356 /* stop RX and TX */
357 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
358 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
359
360 /*
361 * give the hardware some time to really stop all rx/tx activity
362 * clearing the descriptors too early causes random memory corruption
363 */
364 mdelay(1);
365
366 /* clear descriptor addresses */
367 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
368 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
369
370 /* clear pending RX/TX interrupts */
371 for (i = 0; i < 256; i++) {
372 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
373 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
374 }
375
376 /* clear pending errors */
377 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
378 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
379
380 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
381 if (val)
382 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
383 ag->dev->name, val);
384
385 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
386
387 /* mask out reserved bits */
388 val &= ~0xff000000;
389
390 if (val)
391 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
392 ag->dev->name, val);
393
394 ag71xx_dump_dma_regs(ag);
395 }
396
397 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
398 MAC_CFG1_SRX | MAC_CFG1_STX)
399
400 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
401
402 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
403 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
404 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
405 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
406 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
407 FIFO_CFG4_VT)
408
409 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
410 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
411 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
412 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
413 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
414 FIFO_CFG5_17 | FIFO_CFG5_SF)
415
416 static void ag71xx_hw_stop(struct ag71xx *ag)
417 {
418 /* disable all interrupts and stop the rx/tx engine */
419 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
420 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
421 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
422 }
423
424 static void ag71xx_hw_setup(struct ag71xx *ag)
425 {
426 struct device_node *np = ag->pdev->dev.of_node;
427 u32 init = MAC_CFG1_INIT;
428
429 /* setup MAC configuration registers */
430 if (of_property_read_bool(np, "flow-control"))
431 init |= MAC_CFG1_TFC | MAC_CFG1_RFC;
432 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, init);
433
434 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
435 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
436
437 /* setup max frame length to zero */
438 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);
439
440 /* setup FIFO configuration registers */
441 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
442 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, ag->fifodata[0]);
443 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, ag->fifodata[1]);
444 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
445 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
446 }
447
448 static void ag71xx_hw_init(struct ag71xx *ag)
449 {
450 ag71xx_hw_stop(ag);
451
452 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
453 udelay(20);
454
455 reset_control_assert(ag->mac_reset);
456 if (ag->mdio_reset)
457 reset_control_assert(ag->mdio_reset);
458 msleep(100);
459 reset_control_deassert(ag->mac_reset);
460 if (ag->mdio_reset)
461 reset_control_deassert(ag->mdio_reset);
462 msleep(200);
463
464 ag71xx_hw_setup(ag);
465
466 ag71xx_dma_reset(ag);
467 }
468
469 static void ag71xx_fast_reset(struct ag71xx *ag)
470 {
471 struct net_device *dev = ag->dev;
472 u32 rx_ds;
473 u32 mii_reg;
474
475 ag71xx_hw_stop(ag);
476 wmb();
477
478 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
479 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
480
481 ag71xx_tx_packets(ag, true);
482
483 reset_control_assert(ag->mac_reset);
484 udelay(10);
485 reset_control_deassert(ag->mac_reset);
486 udelay(10);
487
488 ag71xx_dma_reset(ag);
489 ag71xx_hw_setup(ag);
490 ag->tx_ring.curr = 0;
491 ag->tx_ring.dirty = 0;
492 netdev_reset_queue(ag->dev);
493
494 /* setup max frame length */
495 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
496 ag71xx_max_frame_len(ag->dev->mtu));
497
498 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
499 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
500 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
501
502 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
503 }
504
505 static void ag71xx_hw_start(struct ag71xx *ag)
506 {
507 /* start RX engine */
508 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
509
510 /* enable interrupts */
511 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
512
513 netif_wake_queue(ag->dev);
514 }
515
516 static void ath79_set_pllval(struct ag71xx *ag)
517 {
518 u32 pll_reg = ag->pllreg[1];
519 u32 pll_val;
520
521 if (!ag->pllregmap)
522 return;
523
524 switch (ag->speed) {
525 case SPEED_10:
526 pll_val = ag->plldata[2];
527 break;
528 case SPEED_100:
529 pll_val = ag->plldata[1];
530 break;
531 case SPEED_1000:
532 pll_val = ag->plldata[0];
533 break;
534 default:
535 BUG();
536 }
537
538 if (pll_val)
539 regmap_write(ag->pllregmap, pll_reg, pll_val);
540 }
541
542 static void ath79_set_pll(struct ag71xx *ag)
543 {
544 u32 pll_cfg = ag->pllreg[0];
545 u32 pll_shift = ag->pllreg[2];
546
547 if (!ag->pllregmap)
548 return;
549
550 regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 2 << pll_shift);
551 udelay(100);
552
553 ath79_set_pllval(ag);
554
555 regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 3 << pll_shift);
556 udelay(100);
557
558 regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 0);
559 udelay(100);
560 }
561
562 static void ag71xx_bit_set(void __iomem *reg, u32 bit)
563 {
564 u32 val;
565
566 val = __raw_readl(reg) | bit;
567 __raw_writel(val, reg);
568 __raw_readl(reg);
569 }
570
571 static void ag71xx_bit_clear(void __iomem *reg, u32 bit)
572 {
573 u32 val;
574
575 val = __raw_readl(reg) & ~bit;
576 __raw_writel(val, reg);
577 __raw_readl(reg);
578 }
579
580 static void ag71xx_sgmii_serdes_init_qca956x(struct device_node *np)
581 {
582 struct device_node *np_dev;
583 void __iomem *gmac_base;
584 u32 serdes_cal;
585 u32 t;
586
587 np = of_get_child_by_name(np, "gmac-config");
588 if (!np)
589 return;
590
591 if (of_property_read_u32(np, "serdes-cal", &serdes_cal))
592 /* By default, use middle value for resistor calibration */
593 serdes_cal = 0x7;
594
595 np_dev = of_parse_phandle(np, "device", 0);
596 if (!np_dev)
597 goto out;
598
599 gmac_base = of_iomap(np_dev, 0);
600 if (!gmac_base) {
601 pr_err("%pOF: can't map GMAC registers\n", np_dev);
602 goto err_iomap;
603 }
604
605 pr_debug("%pOF: fixup SERDES calibration to value %i\n",
606 np_dev, serdes_cal);
607 t = __raw_readl(gmac_base + QCA956X_GMAC_REG_SGMII_SERDES);
608 t &= ~(QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK
609 << QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT);
610 t |= (serdes_cal & QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK)
611 << QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT;
612 __raw_writel(t, gmac_base + QCA956X_GMAC_REG_SGMII_SERDES);
613
614 ath79_pll_wr(QCA956X_PLL_ETH_SGMII_SERDES_REG,
615 QCA956X_PLL_ETH_SGMII_SERDES_LOCK_DETECT
616 | QCA956X_PLL_ETH_SGMII_SERDES_EN_PLL);
617
618 t = __raw_readl(gmac_base + QCA956X_GMAC_REG_SGMII_SERDES);
619
620 /* missing in QCA u-boot code, clear before setting */
621 t &= ~(QCA956X_SGMII_SERDES_CDR_BW_MASK
622 << QCA956X_SGMII_SERDES_CDR_BW_SHIFT |
623 QCA956X_SGMII_SERDES_TX_DR_CTRL_MASK
624 << QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT |
625 QCA956X_SGMII_SERDES_VCO_REG_MASK
626 << QCA956X_SGMII_SERDES_VCO_REG_SHIFT);
627
628 t |= (3 << QCA956X_SGMII_SERDES_CDR_BW_SHIFT) |
629 (1 << QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT) |
630 QCA956X_SGMII_SERDES_PLL_BW |
631 QCA956X_SGMII_SERDES_EN_SIGNAL_DETECT |
632 QCA956X_SGMII_SERDES_FIBER_SDO |
633 (3 << QCA956X_SGMII_SERDES_VCO_REG_SHIFT);
634
635 __raw_writel(t, gmac_base + QCA956X_GMAC_REG_SGMII_SERDES);
636
637 ath79_device_reset_clear(QCA956X_RESET_SGMII_ANALOG);
638 ath79_device_reset_clear(QCA956X_RESET_SGMII);
639
640 while (!(__raw_readl(gmac_base + QCA956X_GMAC_REG_SGMII_SERDES)
641 & QCA956X_SGMII_SERDES_LOCK_DETECT_STATUS))
642 ;
643
644 iounmap(gmac_base);
645 err_iomap:
646 of_node_put(np_dev);
647 out:
648 of_node_put(np);
649 }
650
651 static void ag71xx_sgmii_init_qca955x(struct device_node *np)
652 {
653 struct device_node *np_dev;
654 void __iomem *gmac_base;
655 u32 mr_an_status;
656 u32 sgmii_status;
657 u8 tries = 0;
658 int err = 0;
659
660 np = of_get_child_by_name(np, "gmac-config");
661 if (!np)
662 return;
663
664 np_dev = of_parse_phandle(np, "device", 0);
665 if (!np_dev)
666 goto out;
667
668 gmac_base = of_iomap(np_dev, 0);
669 if (!gmac_base) {
670 pr_err("%pOF: can't map GMAC registers\n", np_dev);
671 err = -ENOMEM;
672 goto err_iomap;
673 }
674
675 mr_an_status = __raw_readl(gmac_base + QCA955X_GMAC_REG_MR_AN_STATUS);
676 if (!(mr_an_status & QCA955X_MR_AN_STATUS_AN_ABILITY))
677 goto sgmii_out;
678
679 /* SGMII reset sequence */
680 __raw_writel(QCA955X_SGMII_RESET_RX_CLK_N_RESET,
681 gmac_base + QCA955X_GMAC_REG_SGMII_RESET);
682 __raw_readl(gmac_base + QCA955X_GMAC_REG_SGMII_RESET);
683 udelay(10);
684
685 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
686 QCA955X_SGMII_RESET_HW_RX_125M_N);
687 udelay(10);
688
689 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
690 QCA955X_SGMII_RESET_RX_125M_N);
691 udelay(10);
692
693 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
694 QCA955X_SGMII_RESET_TX_125M_N);
695 udelay(10);
696
697 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
698 QCA955X_SGMII_RESET_RX_CLK_N);
699 udelay(10);
700
701 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_SGMII_RESET,
702 QCA955X_SGMII_RESET_TX_CLK_N);
703 udelay(10);
704
705 /*
706 * The following is what QCA has to say about what happens here:
707 *
708 * Across resets SGMII link status goes to weird state.
709 * If SGMII_DEBUG register reads other than 0x1f or 0x10,
710 * we are for sure in a bad state.
711 *
712 * Issue a PHY reset in MR_AN_CONTROL to keep going.
713 */
714 do {
715 ag71xx_bit_set(gmac_base + QCA955X_GMAC_REG_MR_AN_CONTROL,
716 QCA955X_MR_AN_CONTROL_PHY_RESET |
717 QCA955X_MR_AN_CONTROL_AN_ENABLE);
718 udelay(200);
719 ag71xx_bit_clear(gmac_base + QCA955X_GMAC_REG_MR_AN_CONTROL,
720 QCA955X_MR_AN_CONTROL_PHY_RESET);
721 mdelay(300);
722 sgmii_status = __raw_readl(gmac_base + QCA955X_GMAC_REG_SGMII_DEBUG) &
723 QCA955X_SGMII_DEBUG_TX_STATE_MASK;
724
725 if (tries++ >= 20) {
726 pr_err("ag71xx: max retries for SGMII fixup exceeded\n");
727 break;
728 }
729 } while (!(sgmii_status == 0xf || sgmii_status == 0x10));
730
731 sgmii_out:
732 iounmap(gmac_base);
733 err_iomap:
734 of_node_put(np_dev);
735 out:
736 of_node_put(np);
737 }
738
739 static void ag71xx_mux_select_sgmii_qca956x(struct device_node *np)
740 {
741 struct device_node *np_dev;
742 void __iomem *gmac_base;
743 u32 t;
744
745 np = of_get_child_by_name(np, "gmac-config");
746 if (!np)
747 return;
748
749 np_dev = of_parse_phandle(np, "device", 0);
750 if (!np_dev)
751 goto out;
752
753 gmac_base = of_iomap(np_dev, 0);
754 if (!gmac_base) {
755 pr_err("%pOF: can't map GMAC registers\n", np_dev);
756 goto err_iomap;
757 }
758
759 t = __raw_readl(gmac_base + QCA956X_GMAC_REG_ETH_CFG);
760 t |= QCA956X_ETH_CFG_GE0_SGMII;
761 __raw_writel(t, gmac_base + QCA956X_GMAC_REG_ETH_CFG);
762
763 iounmap(gmac_base);
764 err_iomap:
765 of_node_put(np_dev);
766 out:
767 of_node_put(np);
768 }
769
770 static void ath79_mii_ctrl_set_if(struct ag71xx *ag, unsigned int mii_if)
771 {
772 u32 t;
773
774 t = __raw_readl(ag->mii_base);
775 t &= ~(AR71XX_MII_CTRL_IF_MASK);
776 t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
777 __raw_writel(t, ag->mii_base);
778 }
779
780 static void ath79_mii0_ctrl_set_if(struct ag71xx *ag)
781 {
782 unsigned int mii_if;
783
784 switch (ag->phy_if_mode) {
785 case PHY_INTERFACE_MODE_MII:
786 mii_if = AR71XX_MII0_CTRL_IF_MII;
787 break;
788 case PHY_INTERFACE_MODE_GMII:
789 mii_if = AR71XX_MII0_CTRL_IF_GMII;
790 break;
791 case PHY_INTERFACE_MODE_RGMII:
792 case PHY_INTERFACE_MODE_RGMII_ID:
793 case PHY_INTERFACE_MODE_RGMII_RXID:
794 case PHY_INTERFACE_MODE_RGMII_TXID:
795 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
796 break;
797 case PHY_INTERFACE_MODE_RMII:
798 mii_if = AR71XX_MII0_CTRL_IF_RMII;
799 break;
800 default:
801 WARN(1, "Impossible PHY mode defined.\n");
802 return;
803 }
804
805 ath79_mii_ctrl_set_if(ag, mii_if);
806 }
807
808 static void ath79_mii1_ctrl_set_if(struct ag71xx *ag)
809 {
810 unsigned int mii_if;
811
812 switch (ag->phy_if_mode) {
813 case PHY_INTERFACE_MODE_RMII:
814 mii_if = AR71XX_MII1_CTRL_IF_RMII;
815 break;
816 case PHY_INTERFACE_MODE_RGMII:
817 case PHY_INTERFACE_MODE_RGMII_ID:
818 case PHY_INTERFACE_MODE_RGMII_RXID:
819 case PHY_INTERFACE_MODE_RGMII_TXID:
820 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
821 break;
822 default:
823 WARN(1, "Impossible PHY mode defined.\n");
824 return;
825 }
826
827 ath79_mii_ctrl_set_if(ag, mii_if);
828 }
829
830 static void ath79_mii_ctrl_set_speed(struct ag71xx *ag)
831 {
832 unsigned int mii_speed;
833 u32 t;
834
835 if (!ag->mii_base)
836 return;
837
838 switch (ag->speed) {
839 case SPEED_10:
840 mii_speed = AR71XX_MII_CTRL_SPEED_10;
841 break;
842 case SPEED_100:
843 mii_speed = AR71XX_MII_CTRL_SPEED_100;
844 break;
845 case SPEED_1000:
846 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
847 break;
848 default:
849 BUG();
850 }
851
852 t = __raw_readl(ag->mii_base);
853 t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
854 t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
855 __raw_writel(t, ag->mii_base);
856 }
857
858 static void
859 __ag71xx_link_adjust(struct ag71xx *ag, bool update)
860 {
861 struct device_node *np = ag->pdev->dev.of_node;
862 u32 cfg2;
863 u32 ifctl;
864 u32 fifo5;
865
866 if (!ag->link && update) {
867 ag71xx_hw_stop(ag);
868 netif_carrier_off(ag->dev);
869 if (netif_msg_link(ag))
870 pr_info("%s: link down\n", ag->dev->name);
871 return;
872 }
873
874 if (!of_device_is_compatible(np, "qca,ar9130-eth") &&
875 !of_device_is_compatible(np, "qca,ar7100-eth"))
876 ag71xx_fast_reset(ag);
877
878 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
879 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
880 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
881
882 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
883 ifctl &= ~(MAC_IFCTL_SPEED);
884
885 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
886 fifo5 &= ~FIFO_CFG5_BM;
887
888 switch (ag->speed) {
889 case SPEED_1000:
890 cfg2 |= MAC_CFG2_IF_1000;
891 fifo5 |= FIFO_CFG5_BM;
892 break;
893 case SPEED_100:
894 cfg2 |= MAC_CFG2_IF_10_100;
895 ifctl |= MAC_IFCTL_SPEED;
896 break;
897 case SPEED_10:
898 cfg2 |= MAC_CFG2_IF_10_100;
899 break;
900 default:
901 BUG();
902 return;
903 }
904
905 if (ag->tx_ring.desc_split) {
906 ag->fifodata[2] &= 0xffff;
907 ag->fifodata[2] |= ((2048 - ag->tx_ring.desc_split) / 4) << 16;
908 }
909
910 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, ag->fifodata[2]);
911
912 if (update) {
913 if (of_device_is_compatible(np, "qca,ar7100-eth") ||
914 of_device_is_compatible(np, "qca,ar9130-eth")) {
915 ath79_set_pll(ag);
916 ath79_mii_ctrl_set_speed(ag);
917 } else if (of_device_is_compatible(np, "qca,ar7242-eth") ||
918 of_device_is_compatible(np, "qca,ar9340-eth") ||
919 of_device_is_compatible(np, "qca,qca9550-eth") ||
920 of_device_is_compatible(np, "qca,qca9560-eth")) {
921 ath79_set_pllval(ag);
922 if (of_property_read_bool(np, "qca955x-sgmii-fixup"))
923 ag71xx_sgmii_init_qca955x(np);
924 }
925 }
926
927 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
928 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
929 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
930
931 if (of_device_is_compatible(np, "qca,qca9530-eth") ||
932 of_device_is_compatible(np, "qca,qca9560-eth")) {
933 /*
934 * The rx ring buffer can stall on small packets on QCA953x and
935 * QCA956x. Disabling the inline checksum engine fixes the stall.
936 * The wr, rr functions cannot be used since this hidden register
937 * is outside of the normal ag71xx register block.
938 */
939 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,9,0)
940 void __iomem *dam = ioremap(0xb90001bc, 0x4);
941 #else
942 void __iomem *dam = ioremap_nocache(0xb90001bc, 0x4);
943 #endif
944 if (dam) {
945 __raw_writel(__raw_readl(dam) & ~BIT(27), dam);
946 (void)__raw_readl(dam);
947 iounmap(dam);
948 }
949 }
950
951 ag71xx_hw_start(ag);
952
953 netif_carrier_on(ag->dev);
954 if (update && netif_msg_link(ag))
955 pr_info("%s: link up (%sMbps/%s duplex)\n",
956 ag->dev->name,
957 ag71xx_speed_str(ag),
958 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
959
960 ag71xx_dump_regs(ag);
961 }
962
963 void ag71xx_link_adjust(struct ag71xx *ag)
964 {
965 __ag71xx_link_adjust(ag, true);
966 }
967
968 static int ag71xx_hw_enable(struct ag71xx *ag)
969 {
970 int ret;
971
972 ret = ag71xx_rings_init(ag);
973 if (ret)
974 return ret;
975
976 napi_enable(&ag->napi);
977 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
978 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
979 netif_start_queue(ag->dev);
980
981 return 0;
982 }
983
984 static void ag71xx_hw_disable(struct ag71xx *ag)
985 {
986 netif_stop_queue(ag->dev);
987
988 ag71xx_hw_stop(ag);
989 ag71xx_dma_reset(ag);
990
991 napi_disable(&ag->napi);
992 del_timer_sync(&ag->oom_timer);
993
994 ag71xx_rings_cleanup(ag);
995 }
996
997 static int ag71xx_open(struct net_device *dev)
998 {
999 struct ag71xx *ag = netdev_priv(dev);
1000 unsigned int max_frame_len;
1001 int ret;
1002
1003 netif_carrier_off(dev);
1004 max_frame_len = ag71xx_max_frame_len(dev->mtu);
1005 ag->rx_buf_size = SKB_DATA_ALIGN(max_frame_len + NET_SKB_PAD + NET_IP_ALIGN);
1006
1007 /* setup max frame length */
1008 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);
1009 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
1010
1011 ret = ag71xx_hw_enable(ag);
1012 if (ret)
1013 goto err;
1014
1015 phy_start(ag->phy_dev);
1016
1017 return 0;
1018
1019 err:
1020 ag71xx_rings_cleanup(ag);
1021 return ret;
1022 }
1023
1024 static int ag71xx_stop(struct net_device *dev)
1025 {
1026 unsigned long flags;
1027 struct ag71xx *ag = netdev_priv(dev);
1028
1029 netif_carrier_off(dev);
1030 phy_stop(ag->phy_dev);
1031
1032 spin_lock_irqsave(&ag->lock, flags);
1033 if (ag->link) {
1034 ag->link = 0;
1035 ag71xx_link_adjust(ag);
1036 }
1037 spin_unlock_irqrestore(&ag->lock, flags);
1038
1039 ag71xx_hw_disable(ag);
1040
1041 return 0;
1042 }
1043
1044 static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len)
1045 {
1046 int i;
1047 struct ag71xx_desc *desc;
1048 int ring_mask = BIT(ring->order) - 1;
1049 int ndesc = 0;
1050 int split = ring->desc_split;
1051
1052 if (!split)
1053 split = len;
1054
1055 while (len > 0) {
1056 unsigned int cur_len = len;
1057
1058 i = (ring->curr + ndesc) & ring_mask;
1059 desc = ag71xx_ring_desc(ring, i);
1060
1061 if (!ag71xx_desc_empty(desc))
1062 return -1;
1063
1064 if (cur_len > split) {
1065 cur_len = split;
1066
1067 /*
1068 * TX will hang if DMA transfers <= 4 bytes,
1069 * make sure next segment is more than 4 bytes long.
1070 */
1071 if (len <= split + 4)
1072 cur_len -= 4;
1073 }
1074
1075 desc->data = addr;
1076 addr += cur_len;
1077 len -= cur_len;
1078
1079 if (len > 0)
1080 cur_len |= DESC_MORE;
1081
1082 /* prevent early tx attempt of this descriptor */
1083 if (!ndesc)
1084 cur_len |= DESC_EMPTY;
1085
1086 desc->ctrl = cur_len;
1087 ndesc++;
1088 }
1089
1090 return ndesc;
1091 }
1092
1093 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
1094 struct net_device *dev)
1095 {
1096 struct ag71xx *ag = netdev_priv(dev);
1097 struct ag71xx_ring *ring = &ag->tx_ring;
1098 int ring_mask = BIT(ring->order) - 1;
1099 int ring_size = BIT(ring->order);
1100 struct ag71xx_desc *desc;
1101 dma_addr_t dma_addr;
1102 int i, n, ring_min;
1103
1104 if (skb->len <= 4) {
1105 DBG("%s: packet len is too small\n", ag->dev->name);
1106 goto err_drop;
1107 }
1108
1109 dma_addr = dma_map_single(&ag->pdev->dev, skb->data, skb->len,
1110 DMA_TO_DEVICE);
1111
1112 i = ring->curr & ring_mask;
1113 desc = ag71xx_ring_desc(ring, i);
1114
1115 /* setup descriptor fields */
1116 n = ag71xx_fill_dma_desc(ring, (u32) dma_addr, skb->len & ag->desc_pktlen_mask);
1117 if (n < 0)
1118 goto err_drop_unmap;
1119
1120 i = (ring->curr + n - 1) & ring_mask;
1121 ring->buf[i].len = skb->len;
1122 ring->buf[i].skb = skb;
1123
1124 netdev_sent_queue(dev, skb->len);
1125
1126 skb_tx_timestamp(skb);
1127
1128 desc->ctrl &= ~DESC_EMPTY;
1129 ring->curr += n;
1130
1131 /* flush descriptor */
1132 wmb();
1133
1134 ring_min = 2;
1135 if (ring->desc_split)
1136 ring_min *= AG71XX_TX_RING_DS_PER_PKT;
1137
1138 if (ring->curr - ring->dirty >= ring_size - ring_min) {
1139 DBG("%s: tx queue full\n", dev->name);
1140 netif_stop_queue(dev);
1141 }
1142
1143 DBG("%s: packet injected into TX queue\n", ag->dev->name);
1144
1145 /* enable TX engine */
1146 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
1147
1148 return NETDEV_TX_OK;
1149
1150 err_drop_unmap:
1151 dma_unmap_single(&ag->pdev->dev, dma_addr, skb->len, DMA_TO_DEVICE);
1152
1153 err_drop:
1154 dev->stats.tx_dropped++;
1155
1156 dev_kfree_skb(skb);
1157 return NETDEV_TX_OK;
1158 }
1159
1160 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1161 {
1162 struct ag71xx *ag = netdev_priv(dev);
1163
1164
1165 switch (cmd) {
1166 case SIOCSIFHWADDR:
1167 if (copy_from_user
1168 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
1169 return -EFAULT;
1170 return 0;
1171
1172 case SIOCGIFHWADDR:
1173 if (copy_to_user
1174 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
1175 return -EFAULT;
1176 return 0;
1177
1178 case SIOCGMIIPHY:
1179 case SIOCGMIIREG:
1180 case SIOCSMIIREG:
1181 if (ag->phy_dev == NULL)
1182 break;
1183
1184 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
1185
1186 default:
1187 break;
1188 }
1189
1190 return -EOPNOTSUPP;
1191 }
1192
1193 static void ag71xx_oom_timer_handler(struct timer_list *t)
1194 {
1195 struct ag71xx *ag = from_timer(ag, t, oom_timer);
1196
1197 napi_schedule(&ag->napi);
1198 }
1199
1200 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,6,0)
1201 static void ag71xx_tx_timeout(struct net_device *dev, unsigned int txqueue)
1202 #else
1203 static void ag71xx_tx_timeout(struct net_device *dev)
1204 #endif
1205 {
1206 struct ag71xx *ag = netdev_priv(dev);
1207
1208 if (netif_msg_tx_err(ag))
1209 pr_info("%s: tx timeout\n", ag->dev->name);
1210
1211 schedule_delayed_work(&ag->restart_work, 1);
1212 }
1213
1214 static void ag71xx_restart_work_func(struct work_struct *work)
1215 {
1216 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work.work);
1217
1218 rtnl_lock();
1219 ag71xx_hw_disable(ag);
1220 ag71xx_hw_enable(ag);
1221 if (ag->link)
1222 __ag71xx_link_adjust(ag, false);
1223 rtnl_unlock();
1224 }
1225
1226 static bool ag71xx_check_dma_stuck(struct ag71xx *ag)
1227 {
1228 unsigned long timestamp;
1229 u32 rx_sm, tx_sm, rx_fd;
1230
1231 timestamp = netdev_get_tx_queue(ag->dev, 0)->trans_start;
1232 if (likely(time_before(jiffies, timestamp + HZ/10)))
1233 return false;
1234
1235 if (!netif_carrier_ok(ag->dev))
1236 return false;
1237
1238 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
1239 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
1240 return true;
1241
1242 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
1243 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
1244 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
1245 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
1246 return true;
1247
1248 return false;
1249 }
1250
1251 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush)
1252 {
1253 struct ag71xx_ring *ring = &ag->tx_ring;
1254 bool dma_stuck = false;
1255 int ring_mask = BIT(ring->order) - 1;
1256 int ring_size = BIT(ring->order);
1257 int sent = 0;
1258 int bytes_compl = 0;
1259 int n = 0;
1260
1261 DBG("%s: processing TX ring\n", ag->dev->name);
1262
1263 while (ring->dirty + n != ring->curr) {
1264 unsigned int i = (ring->dirty + n) & ring_mask;
1265 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1266 struct sk_buff *skb = ring->buf[i].skb;
1267
1268 if (!flush && !ag71xx_desc_empty(desc)) {
1269 if (ag->tx_hang_workaround &&
1270 ag71xx_check_dma_stuck(ag)) {
1271 schedule_delayed_work(&ag->restart_work, HZ / 2);
1272 dma_stuck = true;
1273 }
1274 break;
1275 }
1276
1277 if (flush)
1278 desc->ctrl |= DESC_EMPTY;
1279
1280 n++;
1281 if (!skb)
1282 continue;
1283
1284 dev_kfree_skb_any(skb);
1285 ring->buf[i].skb = NULL;
1286
1287 bytes_compl += ring->buf[i].len;
1288
1289 sent++;
1290 ring->dirty += n;
1291
1292 while (n > 0) {
1293 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
1294 n--;
1295 }
1296 }
1297
1298 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
1299
1300 if (!sent)
1301 return 0;
1302
1303 ag->dev->stats.tx_bytes += bytes_compl;
1304 ag->dev->stats.tx_packets += sent;
1305
1306 netdev_completed_queue(ag->dev, sent, bytes_compl);
1307 if ((ring->curr - ring->dirty) < (ring_size * 3) / 4)
1308 netif_wake_queue(ag->dev);
1309
1310 if (!dma_stuck)
1311 cancel_delayed_work(&ag->restart_work);
1312
1313 return sent;
1314 }
1315
1316 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
1317 {
1318 struct net_device *dev = ag->dev;
1319 struct ag71xx_ring *ring = &ag->rx_ring;
1320 unsigned int pktlen_mask = ag->desc_pktlen_mask;
1321 unsigned int offset = ag->rx_buf_offset;
1322 int ring_mask = BIT(ring->order) - 1;
1323 int ring_size = BIT(ring->order);
1324 struct list_head rx_list;
1325 struct sk_buff *next;
1326 struct sk_buff *skb;
1327 int done = 0;
1328
1329 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
1330 dev->name, limit, ring->curr, ring->dirty);
1331 INIT_LIST_HEAD(&rx_list);
1332
1333 while (done < limit) {
1334 unsigned int i = ring->curr & ring_mask;
1335 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1336 int pktlen;
1337 int err = 0;
1338
1339 if (ag71xx_desc_empty(desc))
1340 break;
1341
1342 if ((ring->dirty + ring_size) == ring->curr) {
1343 ag71xx_assert(0);
1344 break;
1345 }
1346
1347 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
1348
1349 pktlen = desc->ctrl & pktlen_mask;
1350 pktlen -= ETH_FCS_LEN;
1351
1352 dma_unmap_single(&ag->pdev->dev, ring->buf[i].dma_addr,
1353 ag->rx_buf_size, DMA_FROM_DEVICE);
1354
1355 dev->stats.rx_packets++;
1356 dev->stats.rx_bytes += pktlen;
1357
1358 skb = build_skb(ring->buf[i].rx_buf, ag71xx_buffer_size(ag));
1359 if (!skb) {
1360 skb_free_frag(ring->buf[i].rx_buf);
1361 goto next;
1362 }
1363
1364 skb_reserve(skb, offset);
1365 skb_put(skb, pktlen);
1366
1367 if (err) {
1368 dev->stats.rx_dropped++;
1369 kfree_skb(skb);
1370 } else {
1371 skb->dev = dev;
1372 skb->ip_summed = CHECKSUM_NONE;
1373 list_add_tail(&skb->list, &rx_list);
1374 }
1375
1376 next:
1377 ring->buf[i].rx_buf = NULL;
1378 done++;
1379
1380 ring->curr++;
1381 }
1382
1383 ag71xx_ring_rx_refill(ag);
1384
1385 list_for_each_entry_safe(skb, next, &rx_list, list)
1386 skb->protocol = eth_type_trans(skb, dev);
1387 netif_receive_skb_list(&rx_list);
1388
1389 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
1390 dev->name, ring->curr, ring->dirty, done);
1391
1392 return done;
1393 }
1394
1395 static int ag71xx_poll(struct napi_struct *napi, int limit)
1396 {
1397 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
1398 struct net_device *dev = ag->dev;
1399 struct ag71xx_ring *rx_ring = &ag->rx_ring;
1400 int rx_ring_size = BIT(rx_ring->order);
1401 unsigned long flags;
1402 u32 status;
1403 int tx_done;
1404 int rx_done;
1405
1406 tx_done = ag71xx_tx_packets(ag, false);
1407
1408 DBG("%s: processing RX ring\n", dev->name);
1409 rx_done = ag71xx_rx_packets(ag, limit);
1410
1411 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
1412
1413 if (rx_ring->buf[rx_ring->dirty % rx_ring_size].rx_buf == NULL)
1414 goto oom;
1415
1416 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
1417 if (unlikely(status & RX_STATUS_OF)) {
1418 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
1419 dev->stats.rx_fifo_errors++;
1420
1421 /* restart RX */
1422 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
1423 }
1424
1425 if (rx_done < limit) {
1426 if (status & RX_STATUS_PR)
1427 goto more;
1428
1429 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
1430 if (status & TX_STATUS_PS)
1431 goto more;
1432
1433 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
1434 dev->name, rx_done, tx_done, limit);
1435
1436 napi_complete(napi);
1437
1438 /* enable interrupts */
1439 spin_lock_irqsave(&ag->lock, flags);
1440 ag71xx_int_enable(ag, AG71XX_INT_POLL);
1441 spin_unlock_irqrestore(&ag->lock, flags);
1442 return rx_done;
1443 }
1444
1445 more:
1446 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
1447 dev->name, rx_done, tx_done, limit);
1448 return limit;
1449
1450 oom:
1451 if (netif_msg_rx_err(ag))
1452 pr_info("%s: out of memory\n", dev->name);
1453
1454 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
1455 napi_complete(napi);
1456 return 0;
1457 }
1458
1459 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
1460 {
1461 struct net_device *dev = dev_id;
1462 struct ag71xx *ag = netdev_priv(dev);
1463 u32 status;
1464
1465 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1466 ag71xx_dump_intr(ag, "raw", status);
1467
1468 if (unlikely(!status))
1469 return IRQ_NONE;
1470
1471 if (unlikely(status & AG71XX_INT_ERR)) {
1472 if (status & AG71XX_INT_TX_BE) {
1473 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1474 dev_err(&dev->dev, "TX BUS error\n");
1475 }
1476 if (status & AG71XX_INT_RX_BE) {
1477 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1478 dev_err(&dev->dev, "RX BUS error\n");
1479 }
1480 }
1481
1482 if (likely(status & AG71XX_INT_POLL)) {
1483 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1484 DBG("%s: enable polling mode\n", dev->name);
1485 napi_schedule(&ag->napi);
1486 }
1487
1488 ag71xx_debugfs_update_int_stats(ag, status);
1489
1490 return IRQ_HANDLED;
1491 }
1492
1493 static int ag71xx_change_mtu(struct net_device *dev, int new_mtu)
1494 {
1495 struct ag71xx *ag = netdev_priv(dev);
1496
1497 dev->mtu = new_mtu;
1498 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
1499 ag71xx_max_frame_len(dev->mtu));
1500
1501 return 0;
1502 }
1503
1504 static const struct net_device_ops ag71xx_netdev_ops = {
1505 .ndo_open = ag71xx_open,
1506 .ndo_stop = ag71xx_stop,
1507 .ndo_start_xmit = ag71xx_hard_start_xmit,
1508 .ndo_do_ioctl = ag71xx_do_ioctl,
1509 .ndo_tx_timeout = ag71xx_tx_timeout,
1510 .ndo_change_mtu = ag71xx_change_mtu,
1511 .ndo_set_mac_address = eth_mac_addr,
1512 .ndo_validate_addr = eth_validate_addr,
1513 };
1514
1515 static int ag71xx_probe(struct platform_device *pdev)
1516 {
1517 struct device_node *np = pdev->dev.of_node;
1518 struct net_device *dev;
1519 struct resource *res;
1520 struct ag71xx *ag;
1521 const void *mac_addr;
1522 u32 max_frame_len;
1523 int tx_size, err;
1524
1525 if (!np)
1526 return -ENODEV;
1527
1528 dev = devm_alloc_etherdev(&pdev->dev, sizeof(*ag));
1529 if (!dev)
1530 return -ENOMEM;
1531
1532 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1533 if (!res)
1534 return -EINVAL;
1535
1536 if (of_property_read_bool(np, "qca956x-serdes-fixup")) {
1537 ag71xx_sgmii_serdes_init_qca956x(np);
1538 ag71xx_sgmii_init_qca955x(np);
1539 }
1540
1541 err = ag71xx_setup_gmac(np);
1542 if (err)
1543 return err;
1544
1545 SET_NETDEV_DEV(dev, &pdev->dev);
1546
1547 ag = netdev_priv(dev);
1548 ag->pdev = pdev;
1549 ag->dev = dev;
1550 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1551 AG71XX_DEFAULT_MSG_ENABLE);
1552 spin_lock_init(&ag->lock);
1553
1554 ag->mac_reset = devm_reset_control_get_exclusive(&pdev->dev, "mac");
1555 if (IS_ERR(ag->mac_reset)) {
1556 dev_err(&pdev->dev, "missing mac reset\n");
1557 return PTR_ERR(ag->mac_reset);
1558 }
1559
1560 ag->mdio_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "mdio");
1561
1562 if (of_property_read_u32_array(np, "fifo-data", ag->fifodata, 3)) {
1563 if (of_device_is_compatible(np, "qca,ar9130-eth") ||
1564 of_device_is_compatible(np, "qca,ar7100-eth")) {
1565 ag->fifodata[0] = 0x0fff0000;
1566 ag->fifodata[1] = 0x00001fff;
1567 } else {
1568 ag->fifodata[0] = 0x0010ffff;
1569 ag->fifodata[1] = 0x015500aa;
1570 ag->fifodata[2] = 0x01f00140;
1571 }
1572 if (of_device_is_compatible(np, "qca,ar9130-eth"))
1573 ag->fifodata[2] = 0x00780fff;
1574 else if (of_device_is_compatible(np, "qca,ar7100-eth"))
1575 ag->fifodata[2] = 0x008001ff;
1576 }
1577
1578 if (of_property_read_u32_array(np, "pll-data", ag->plldata, 3))
1579 dev_dbg(&pdev->dev, "failed to read pll-data property\n");
1580
1581 if (of_property_read_u32_array(np, "pll-reg", ag->pllreg, 3))
1582 dev_dbg(&pdev->dev, "failed to read pll-reg property\n");
1583
1584 ag->pllregmap = syscon_regmap_lookup_by_phandle(np, "pll-handle");
1585 if (IS_ERR(ag->pllregmap)) {
1586 dev_dbg(&pdev->dev, "failed to read pll-handle property\n");
1587 ag->pllregmap = NULL;
1588 }
1589
1590 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,9,0)
1591 ag->mac_base = devm_ioremap(&pdev->dev, res->start,
1592 res->end - res->start + 1);
1593 #else
1594 ag->mac_base = devm_ioremap_nocache(&pdev->dev, res->start,
1595 res->end - res->start + 1);
1596 #endif
1597 if (!ag->mac_base)
1598 return -ENOMEM;
1599
1600 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1601 if (res) {
1602 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,9,0)
1603 ag->mii_base = devm_ioremap(&pdev->dev, res->start,
1604 res->end - res->start + 1);
1605 #else
1606 ag->mii_base = devm_ioremap_nocache(&pdev->dev, res->start,
1607 res->end - res->start + 1);
1608 #endif
1609 if (!ag->mii_base)
1610 return -ENOMEM;
1611 }
1612
1613 dev->irq = platform_get_irq(pdev, 0);
1614 err = devm_request_irq(&pdev->dev, dev->irq, ag71xx_interrupt,
1615 0x0, dev_name(&pdev->dev), dev);
1616 if (err) {
1617 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1618 return err;
1619 }
1620
1621 dev->netdev_ops = &ag71xx_netdev_ops;
1622 dev->ethtool_ops = &ag71xx_ethtool_ops;
1623
1624 INIT_DELAYED_WORK(&ag->restart_work, ag71xx_restart_work_func);
1625
1626 timer_setup(&ag->oom_timer, ag71xx_oom_timer_handler, 0);
1627
1628 tx_size = AG71XX_TX_RING_SIZE_DEFAULT;
1629 ag->rx_ring.order = ag71xx_ring_size_order(AG71XX_RX_RING_SIZE_DEFAULT);
1630
1631 if (of_device_is_compatible(np, "qca,ar9340-eth") ||
1632 of_device_is_compatible(np, "qca,qca9530-eth") ||
1633 of_device_is_compatible(np, "qca,qca9550-eth") ||
1634 of_device_is_compatible(np, "qca,qca9560-eth"))
1635 ag->desc_pktlen_mask = SZ_16K - 1;
1636 else
1637 ag->desc_pktlen_mask = SZ_4K - 1;
1638
1639 if (ag->desc_pktlen_mask == SZ_16K - 1 &&
1640 !of_device_is_compatible(np, "qca,qca9550-eth") &&
1641 !of_device_is_compatible(np, "qca,qca9560-eth"))
1642 max_frame_len = ag->desc_pktlen_mask;
1643 else
1644 max_frame_len = 1540;
1645
1646 dev->min_mtu = 68;
1647 dev->max_mtu = max_frame_len - ag71xx_max_frame_len(0);
1648
1649 if (of_device_is_compatible(np, "qca,ar7240-eth") ||
1650 of_device_is_compatible(np, "qca,ar7241-eth") ||
1651 of_device_is_compatible(np, "qca,ar7242-eth") ||
1652 of_device_is_compatible(np, "qca,ar9330-eth") ||
1653 of_device_is_compatible(np, "qca,ar9340-eth") ||
1654 of_device_is_compatible(np, "qca,qca9530-eth") ||
1655 of_device_is_compatible(np, "qca,qca9550-eth") ||
1656 of_device_is_compatible(np, "qca,qca9560-eth"))
1657 ag->tx_hang_workaround = 1;
1658
1659 ag->rx_buf_offset = NET_SKB_PAD;
1660 if (!of_device_is_compatible(np, "qca,ar7100-eth") &&
1661 !of_device_is_compatible(np, "qca,ar9130-eth"))
1662 ag->rx_buf_offset += NET_IP_ALIGN;
1663
1664 if (of_device_is_compatible(np, "qca,ar7100-eth")) {
1665 ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT;
1666 tx_size *= AG71XX_TX_RING_DS_PER_PKT;
1667 }
1668 ag->tx_ring.order = ag71xx_ring_size_order(tx_size);
1669
1670 ag->stop_desc = dmam_alloc_coherent(&pdev->dev,
1671 sizeof(struct ag71xx_desc),
1672 &ag->stop_desc_dma, GFP_KERNEL);
1673 if (!ag->stop_desc)
1674 return -ENOMEM;
1675
1676 ag->stop_desc->data = 0;
1677 ag->stop_desc->ctrl = 0;
1678 ag->stop_desc->next = (u32) ag->stop_desc_dma;
1679
1680 mac_addr = of_get_mac_address(np);
1681 if (IS_ERR_OR_NULL(mac_addr) || !is_valid_ether_addr(mac_addr)) {
1682 dev_err(&pdev->dev, "invalid MAC address, using random address\n");
1683 eth_random_addr(dev->dev_addr);
1684 } else {
1685 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
1686 }
1687
1688 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,10,0)
1689 of_get_phy_mode(np, &ag->phy_if_mode);
1690 #else
1691 ag->phy_if_mode = of_get_phy_mode(np);
1692 #endif
1693
1694 if (ag->phy_if_mode < 0) {
1695 dev_err(&pdev->dev, "missing phy-mode property in DT\n");
1696 return ag->phy_if_mode;
1697 }
1698
1699 if (of_device_is_compatible(np, "qca,qca9560-eth") &&
1700 ag->phy_if_mode == PHY_INTERFACE_MODE_SGMII)
1701 ag71xx_mux_select_sgmii_qca956x(np);
1702
1703 if (of_property_read_u32(np, "qca,mac-idx", &ag->mac_idx))
1704 ag->mac_idx = -1;
1705 if (ag->mii_base)
1706 switch (ag->mac_idx) {
1707 case 0:
1708 ath79_mii0_ctrl_set_if(ag);
1709 break;
1710 case 1:
1711 ath79_mii1_ctrl_set_if(ag);
1712 break;
1713 default:
1714 break;
1715 }
1716
1717 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1718
1719 ag71xx_dump_regs(ag);
1720
1721 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, 0);
1722
1723 ag71xx_hw_init(ag);
1724
1725 ag71xx_dump_regs(ag);
1726
1727 /*
1728 * populate current node to register mdio-bus as a subdevice.
1729 * the mdio bus works independently on ar7241 and later chips
1730 * and we need to load mdio1 before gmac0, which can be done
1731 * by adding a "simple-mfd" compatible to gmac node. The
1732 * following code checks OF_POPULATED_BUS flag before populating
1733 * to avoid duplicated population.
1734 */
1735 if (!of_node_check_flag(np, OF_POPULATED_BUS)) {
1736 err = of_platform_populate(np, NULL, NULL, &pdev->dev);
1737 if (err)
1738 return err;
1739 }
1740
1741 err = ag71xx_phy_connect(ag);
1742 if (err)
1743 return err;
1744
1745 err = ag71xx_debugfs_init(ag);
1746 if (err)
1747 goto err_phy_disconnect;
1748
1749 platform_set_drvdata(pdev, dev);
1750
1751 err = register_netdev(dev);
1752 if (err) {
1753 dev_err(&pdev->dev, "unable to register net device\n");
1754 platform_set_drvdata(pdev, NULL);
1755 ag71xx_debugfs_exit(ag);
1756 goto err_phy_disconnect;
1757 }
1758
1759 pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode: %s\n",
1760 dev->name, (unsigned long) ag->mac_base, dev->irq,
1761 phy_modes(ag->phy_if_mode));
1762
1763 return 0;
1764
1765 err_phy_disconnect:
1766 ag71xx_phy_disconnect(ag);
1767 return err;
1768 }
1769
1770 static int ag71xx_remove(struct platform_device *pdev)
1771 {
1772 struct net_device *dev = platform_get_drvdata(pdev);
1773 struct ag71xx *ag;
1774
1775 if (!dev)
1776 return 0;
1777
1778 ag = netdev_priv(dev);
1779 ag71xx_debugfs_exit(ag);
1780 ag71xx_phy_disconnect(ag);
1781 unregister_netdev(dev);
1782 platform_set_drvdata(pdev, NULL);
1783 return 0;
1784 }
1785
1786 static const struct of_device_id ag71xx_match[] = {
1787 { .compatible = "qca,ar7100-eth" },
1788 { .compatible = "qca,ar7240-eth" },
1789 { .compatible = "qca,ar7241-eth" },
1790 { .compatible = "qca,ar7242-eth" },
1791 { .compatible = "qca,ar9130-eth" },
1792 { .compatible = "qca,ar9330-eth" },
1793 { .compatible = "qca,ar9340-eth" },
1794 { .compatible = "qca,qca9530-eth" },
1795 { .compatible = "qca,qca9550-eth" },
1796 { .compatible = "qca,qca9560-eth" },
1797 {}
1798 };
1799
1800 static struct platform_driver ag71xx_driver = {
1801 .probe = ag71xx_probe,
1802 .remove = ag71xx_remove,
1803 .driver = {
1804 .name = AG71XX_DRV_NAME,
1805 .of_match_table = ag71xx_match,
1806 }
1807 };
1808
1809 static int __init ag71xx_module_init(void)
1810 {
1811 int ret;
1812
1813 ret = ag71xx_debugfs_root_init();
1814 if (ret)
1815 goto err_out;
1816
1817 ret = platform_driver_register(&ag71xx_driver);
1818 if (ret)
1819 goto err_debugfs_exit;
1820
1821 return 0;
1822
1823 err_debugfs_exit:
1824 ag71xx_debugfs_root_exit();
1825 err_out:
1826 return ret;
1827 }
1828
1829 static void __exit ag71xx_module_exit(void)
1830 {
1831 platform_driver_unregister(&ag71xx_driver);
1832 ag71xx_debugfs_root_exit();
1833 }
1834
1835 module_init(ag71xx_module_init);
1836 module_exit(ag71xx_module_exit);
1837
1838 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1839 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1840 MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
1841 MODULE_LICENSE("GPL v2");
1842 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
OpenWrt Source Repository