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ar71xx/ath79: ag71xx: fix sleep in atomic
[openwrt/openwrt.git] / target / linux / ath79 / files / drivers / net / ethernet / atheros / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include <linux/sizes.h>
15 #include <linux/of_net.h>
16 #include <linux/of_address.h>
17 #include <linux/of_platform.h>
18 #include "ag71xx.h"
19
20 #define AG71XX_DEFAULT_MSG_ENABLE \
21 (NETIF_MSG_DRV \
22 | NETIF_MSG_PROBE \
23 | NETIF_MSG_LINK \
24 | NETIF_MSG_TIMER \
25 | NETIF_MSG_IFDOWN \
26 | NETIF_MSG_IFUP \
27 | NETIF_MSG_RX_ERR \
28 | NETIF_MSG_TX_ERR)
29
30 static int ag71xx_msg_level = -1;
31
32 module_param_named(msg_level, ag71xx_msg_level, int, 0);
33 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
34
35 #define ETH_SWITCH_HEADER_LEN 2
36
37 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush);
38
39 static inline unsigned int ag71xx_max_frame_len(unsigned int mtu)
40 {
41 return ETH_SWITCH_HEADER_LEN + ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN;
42 }
43
44 static void ag71xx_dump_dma_regs(struct ag71xx *ag)
45 {
46 DBG("%s: dma_tx_ctrl=%08x, dma_tx_desc=%08x, dma_tx_status=%08x\n",
47 ag->dev->name,
48 ag71xx_rr(ag, AG71XX_REG_TX_CTRL),
49 ag71xx_rr(ag, AG71XX_REG_TX_DESC),
50 ag71xx_rr(ag, AG71XX_REG_TX_STATUS));
51
52 DBG("%s: dma_rx_ctrl=%08x, dma_rx_desc=%08x, dma_rx_status=%08x\n",
53 ag->dev->name,
54 ag71xx_rr(ag, AG71XX_REG_RX_CTRL),
55 ag71xx_rr(ag, AG71XX_REG_RX_DESC),
56 ag71xx_rr(ag, AG71XX_REG_RX_STATUS));
57 }
58
59 static void ag71xx_dump_regs(struct ag71xx *ag)
60 {
61 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
62 ag->dev->name,
63 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
64 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
65 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
66 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
67 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
68 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
69 ag->dev->name,
70 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
71 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
72 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
73 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
74 ag->dev->name,
75 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
76 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
77 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
78 DBG("%s: fifo_cfg3=%08x, fifo_cfg4=%08x, fifo_cfg5=%08x\n",
79 ag->dev->name,
80 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
81 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
82 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
83 }
84
85 static inline void ag71xx_dump_intr(struct ag71xx *ag, char *label, u32 intr)
86 {
87 DBG("%s: %s intr=%08x %s%s%s%s%s%s\n",
88 ag->dev->name, label, intr,
89 (intr & AG71XX_INT_TX_PS) ? "TXPS " : "",
90 (intr & AG71XX_INT_TX_UR) ? "TXUR " : "",
91 (intr & AG71XX_INT_TX_BE) ? "TXBE " : "",
92 (intr & AG71XX_INT_RX_PR) ? "RXPR " : "",
93 (intr & AG71XX_INT_RX_OF) ? "RXOF " : "",
94 (intr & AG71XX_INT_RX_BE) ? "RXBE " : "");
95 }
96
97 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
98 {
99 struct ag71xx_ring *ring = &ag->tx_ring;
100 struct net_device *dev = ag->dev;
101 int ring_mask = BIT(ring->order) - 1;
102 u32 bytes_compl = 0, pkts_compl = 0;
103
104 while (ring->curr != ring->dirty) {
105 struct ag71xx_desc *desc;
106 u32 i = ring->dirty & ring_mask;
107
108 desc = ag71xx_ring_desc(ring, i);
109 if (!ag71xx_desc_empty(desc)) {
110 desc->ctrl = 0;
111 dev->stats.tx_errors++;
112 }
113
114 if (ring->buf[i].skb) {
115 bytes_compl += ring->buf[i].len;
116 pkts_compl++;
117 dev_kfree_skb_any(ring->buf[i].skb);
118 }
119 ring->buf[i].skb = NULL;
120 ring->dirty++;
121 }
122
123 /* flush descriptors */
124 wmb();
125
126 netdev_completed_queue(dev, pkts_compl, bytes_compl);
127 }
128
129 static void ag71xx_ring_tx_init(struct ag71xx *ag)
130 {
131 struct ag71xx_ring *ring = &ag->tx_ring;
132 int ring_size = BIT(ring->order);
133 int ring_mask = ring_size - 1;
134 int i;
135
136 for (i = 0; i < ring_size; i++) {
137 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
138
139 desc->next = (u32) (ring->descs_dma +
140 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
141
142 desc->ctrl = DESC_EMPTY;
143 ring->buf[i].skb = NULL;
144 }
145
146 /* flush descriptors */
147 wmb();
148
149 ring->curr = 0;
150 ring->dirty = 0;
151 netdev_reset_queue(ag->dev);
152 }
153
154 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
155 {
156 struct ag71xx_ring *ring = &ag->rx_ring;
157 int ring_size = BIT(ring->order);
158 int i;
159
160 if (!ring->buf)
161 return;
162
163 for (i = 0; i < ring_size; i++)
164 if (ring->buf[i].rx_buf) {
165 dma_unmap_single(&ag->pdev->dev, ring->buf[i].dma_addr,
166 ag->rx_buf_size, DMA_FROM_DEVICE);
167 skb_free_frag(ring->buf[i].rx_buf);
168 }
169 }
170
171 static int ag71xx_buffer_size(struct ag71xx *ag)
172 {
173 return ag->rx_buf_size +
174 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
175 }
176
177 static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf,
178 int offset,
179 void *(*alloc)(unsigned int size))
180 {
181 struct ag71xx_ring *ring = &ag->rx_ring;
182 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]);
183 void *data;
184
185 data = alloc(ag71xx_buffer_size(ag));
186 if (!data)
187 return false;
188
189 buf->rx_buf = data;
190 buf->dma_addr = dma_map_single(&ag->pdev->dev, data, ag->rx_buf_size,
191 DMA_FROM_DEVICE);
192 desc->data = (u32) buf->dma_addr + offset;
193 return true;
194 }
195
196 static int ag71xx_ring_rx_init(struct ag71xx *ag)
197 {
198 struct ag71xx_ring *ring = &ag->rx_ring;
199 int ring_size = BIT(ring->order);
200 int ring_mask = BIT(ring->order) - 1;
201 unsigned int i;
202 int ret;
203
204 ret = 0;
205 for (i = 0; i < ring_size; i++) {
206 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
207
208 desc->next = (u32) (ring->descs_dma +
209 AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
210
211 DBG("ag71xx: RX desc at %p, next is %08x\n",
212 desc, desc->next);
213 }
214
215 for (i = 0; i < ring_size; i++) {
216 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
217
218 if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], ag->rx_buf_offset,
219 netdev_alloc_frag)) {
220 ret = -ENOMEM;
221 break;
222 }
223
224 desc->ctrl = DESC_EMPTY;
225 }
226
227 /* flush descriptors */
228 wmb();
229
230 ring->curr = 0;
231 ring->dirty = 0;
232
233 return ret;
234 }
235
236 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
237 {
238 struct ag71xx_ring *ring = &ag->rx_ring;
239 int ring_mask = BIT(ring->order) - 1;
240 unsigned int count;
241 int offset = ag->rx_buf_offset;
242
243 count = 0;
244 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
245 struct ag71xx_desc *desc;
246 unsigned int i;
247
248 i = ring->dirty & ring_mask;
249 desc = ag71xx_ring_desc(ring, i);
250
251 if (!ring->buf[i].rx_buf &&
252 !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset,
253 napi_alloc_frag))
254 break;
255
256 desc->ctrl = DESC_EMPTY;
257 count++;
258 }
259
260 /* flush descriptors */
261 wmb();
262
263 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
264
265 return count;
266 }
267
268 static int ag71xx_rings_init(struct ag71xx *ag)
269 {
270 struct ag71xx_ring *tx = &ag->tx_ring;
271 struct ag71xx_ring *rx = &ag->rx_ring;
272 int ring_size = BIT(tx->order) + BIT(rx->order);
273 int tx_size = BIT(tx->order);
274
275 tx->buf = kzalloc(ring_size * sizeof(*tx->buf), GFP_KERNEL);
276 if (!tx->buf)
277 return -ENOMEM;
278
279 tx->descs_cpu = dma_alloc_coherent(&ag->pdev->dev, ring_size * AG71XX_DESC_SIZE,
280 &tx->descs_dma, GFP_ATOMIC);
281 if (!tx->descs_cpu) {
282 kfree(tx->buf);
283 tx->buf = NULL;
284 return -ENOMEM;
285 }
286
287 rx->buf = &tx->buf[BIT(tx->order)];
288 rx->descs_cpu = ((void *)tx->descs_cpu) + tx_size * AG71XX_DESC_SIZE;
289 rx->descs_dma = tx->descs_dma + tx_size * AG71XX_DESC_SIZE;
290
291 ag71xx_ring_tx_init(ag);
292 return ag71xx_ring_rx_init(ag);
293 }
294
295 static void ag71xx_rings_free(struct ag71xx *ag)
296 {
297 struct ag71xx_ring *tx = &ag->tx_ring;
298 struct ag71xx_ring *rx = &ag->rx_ring;
299 int ring_size = BIT(tx->order) + BIT(rx->order);
300
301 if (tx->descs_cpu)
302 dma_free_coherent(&ag->pdev->dev, ring_size * AG71XX_DESC_SIZE,
303 tx->descs_cpu, tx->descs_dma);
304
305 kfree(tx->buf);
306
307 tx->descs_cpu = NULL;
308 rx->descs_cpu = NULL;
309 tx->buf = NULL;
310 rx->buf = NULL;
311 }
312
313 static void ag71xx_rings_cleanup(struct ag71xx *ag)
314 {
315 ag71xx_ring_rx_clean(ag);
316 ag71xx_ring_tx_clean(ag);
317 ag71xx_rings_free(ag);
318
319 netdev_reset_queue(ag->dev);
320 }
321
322 static unsigned char *ag71xx_speed_str(struct ag71xx *ag)
323 {
324 switch (ag->speed) {
325 case SPEED_1000:
326 return "1000";
327 case SPEED_100:
328 return "100";
329 case SPEED_10:
330 return "10";
331 }
332
333 return "?";
334 }
335
336 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
337 {
338 u32 t;
339
340 t = (((u32) mac[5]) << 24) | (((u32) mac[4]) << 16)
341 | (((u32) mac[3]) << 8) | ((u32) mac[2]);
342
343 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
344
345 t = (((u32) mac[1]) << 24) | (((u32) mac[0]) << 16);
346 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
347 }
348
349 static void ag71xx_dma_reset(struct ag71xx *ag)
350 {
351 u32 val;
352 int i;
353
354 ag71xx_dump_dma_regs(ag);
355
356 /* stop RX and TX */
357 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
358 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
359
360 /*
361 * give the hardware some time to really stop all rx/tx activity
362 * clearing the descriptors too early causes random memory corruption
363 */
364 mdelay(1);
365
366 /* clear descriptor addresses */
367 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
368 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
369
370 /* clear pending RX/TX interrupts */
371 for (i = 0; i < 256; i++) {
372 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
373 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
374 }
375
376 /* clear pending errors */
377 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
378 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
379
380 val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
381 if (val)
382 pr_alert("%s: unable to clear DMA Rx status: %08x\n",
383 ag->dev->name, val);
384
385 val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
386
387 /* mask out reserved bits */
388 val &= ~0xff000000;
389
390 if (val)
391 pr_alert("%s: unable to clear DMA Tx status: %08x\n",
392 ag->dev->name, val);
393
394 ag71xx_dump_dma_regs(ag);
395 }
396
397 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
398 MAC_CFG1_SRX | MAC_CFG1_STX)
399
400 #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
401
402 #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
403 FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
404 FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
405 FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
406 FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
407 FIFO_CFG4_VT)
408
409 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
410 FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
411 FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
412 FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
413 FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
414 FIFO_CFG5_17 | FIFO_CFG5_SF)
415
416 static void ag71xx_hw_stop(struct ag71xx *ag)
417 {
418 /* disable all interrupts and stop the rx/tx engine */
419 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
420 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
421 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
422 }
423
424 static void ag71xx_hw_setup(struct ag71xx *ag)
425 {
426 struct device_node *np = ag->pdev->dev.of_node;
427 u32 init = MAC_CFG1_INIT;
428
429 /* setup MAC configuration registers */
430 if (of_property_read_bool(np, "flow-control"))
431 init |= MAC_CFG1_TFC | MAC_CFG1_RFC;
432 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, init);
433
434 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
435 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
436
437 /* setup max frame length to zero */
438 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);
439
440 /* setup FIFO configuration registers */
441 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
442 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, ag->fifodata[0]);
443 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, ag->fifodata[1]);
444 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
445 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
446 }
447
448 static void ag71xx_hw_init(struct ag71xx *ag)
449 {
450 ag71xx_hw_stop(ag);
451
452 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
453 udelay(20);
454
455 reset_control_assert(ag->mac_reset);
456 if (ag->mdio_reset)
457 reset_control_assert(ag->mdio_reset);
458 msleep(100);
459 reset_control_deassert(ag->mac_reset);
460 if (ag->mdio_reset)
461 reset_control_deassert(ag->mdio_reset);
462 msleep(200);
463
464 ag71xx_hw_setup(ag);
465
466 ag71xx_dma_reset(ag);
467 }
468
469 static void ag71xx_fast_reset(struct ag71xx *ag)
470 {
471 struct net_device *dev = ag->dev;
472 u32 rx_ds;
473 u32 mii_reg;
474
475 ag71xx_hw_stop(ag);
476 wmb();
477
478 mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
479 rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
480
481 ag71xx_tx_packets(ag, true);
482
483 reset_control_assert(ag->mac_reset);
484 udelay(10);
485 reset_control_deassert(ag->mac_reset);
486 udelay(10);
487
488 ag71xx_dma_reset(ag);
489 ag71xx_hw_setup(ag);
490 ag->tx_ring.curr = 0;
491 ag->tx_ring.dirty = 0;
492 netdev_reset_queue(ag->dev);
493
494 /* setup max frame length */
495 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
496 ag71xx_max_frame_len(ag->dev->mtu));
497
498 ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
499 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
500 ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
501
502 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
503 }
504
505 static void ag71xx_hw_start(struct ag71xx *ag)
506 {
507 /* start RX engine */
508 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
509
510 /* enable interrupts */
511 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
512
513 netif_wake_queue(ag->dev);
514 }
515
516 static void ath79_set_pllval(struct ag71xx *ag)
517 {
518 u32 pll_reg = ag->pllreg[1];
519 u32 pll_val;
520
521 if (!ag->pllregmap)
522 return;
523
524 switch (ag->speed) {
525 case SPEED_10:
526 pll_val = ag->plldata[2];
527 break;
528 case SPEED_100:
529 pll_val = ag->plldata[1];
530 break;
531 case SPEED_1000:
532 pll_val = ag->plldata[0];
533 break;
534 default:
535 BUG();
536 }
537
538 if (pll_val)
539 regmap_write(ag->pllregmap, pll_reg, pll_val);
540 }
541
542 static void ath79_set_pll(struct ag71xx *ag)
543 {
544 u32 pll_cfg = ag->pllreg[0];
545 u32 pll_shift = ag->pllreg[2];
546
547 if (!ag->pllregmap)
548 return;
549
550 regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 2 << pll_shift);
551 udelay(100);
552
553 ath79_set_pllval(ag);
554
555 regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 3 << pll_shift);
556 udelay(100);
557
558 regmap_update_bits(ag->pllregmap, pll_cfg, 3 << pll_shift, 0);
559 udelay(100);
560 }
561
562 static void ath79_mii_ctrl_set_if(struct ag71xx *ag, unsigned int mii_if)
563 {
564 u32 t;
565
566 t = __raw_readl(ag->mii_base);
567 t &= ~(AR71XX_MII_CTRL_IF_MASK);
568 t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
569 __raw_writel(t, ag->mii_base);
570 }
571
572 static void ath79_mii0_ctrl_set_if(struct ag71xx *ag)
573 {
574 unsigned int mii_if;
575
576 switch (ag->phy_if_mode) {
577 case PHY_INTERFACE_MODE_MII:
578 mii_if = AR71XX_MII0_CTRL_IF_MII;
579 break;
580 case PHY_INTERFACE_MODE_GMII:
581 mii_if = AR71XX_MII0_CTRL_IF_GMII;
582 break;
583 case PHY_INTERFACE_MODE_RGMII:
584 case PHY_INTERFACE_MODE_RGMII_ID:
585 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
586 break;
587 case PHY_INTERFACE_MODE_RMII:
588 mii_if = AR71XX_MII0_CTRL_IF_RMII;
589 break;
590 default:
591 WARN(1, "Impossible PHY mode defined.\n");
592 return;
593 }
594
595 ath79_mii_ctrl_set_if(ag, mii_if);
596 }
597
598 static void ath79_mii1_ctrl_set_if(struct ag71xx *ag)
599 {
600 unsigned int mii_if;
601
602 switch (ag->phy_if_mode) {
603 case PHY_INTERFACE_MODE_RMII:
604 mii_if = AR71XX_MII1_CTRL_IF_RMII;
605 break;
606 case PHY_INTERFACE_MODE_RGMII:
607 case PHY_INTERFACE_MODE_RGMII_ID:
608 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
609 break;
610 default:
611 WARN(1, "Impossible PHY mode defined.\n");
612 return;
613 }
614
615 ath79_mii_ctrl_set_if(ag, mii_if);
616 }
617
618 static void ath79_mii_ctrl_set_speed(struct ag71xx *ag)
619 {
620 unsigned int mii_speed;
621 u32 t;
622
623 if (!ag->mii_base)
624 return;
625
626 switch (ag->speed) {
627 case SPEED_10:
628 mii_speed = AR71XX_MII_CTRL_SPEED_10;
629 break;
630 case SPEED_100:
631 mii_speed = AR71XX_MII_CTRL_SPEED_100;
632 break;
633 case SPEED_1000:
634 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
635 break;
636 default:
637 BUG();
638 }
639
640 t = __raw_readl(ag->mii_base);
641 t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
642 t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
643 __raw_writel(t, ag->mii_base);
644 }
645
646 static void
647 __ag71xx_link_adjust(struct ag71xx *ag, bool update)
648 {
649 struct device_node *np = ag->pdev->dev.of_node;
650 u32 cfg2;
651 u32 ifctl;
652 u32 fifo5;
653
654 if (!ag->link && update) {
655 ag71xx_hw_stop(ag);
656 netif_carrier_off(ag->dev);
657 if (netif_msg_link(ag))
658 pr_info("%s: link down\n", ag->dev->name);
659 return;
660 }
661
662 if (!of_device_is_compatible(np, "qca,ar9130-eth") &&
663 !of_device_is_compatible(np, "qca,ar7100-eth"))
664 ag71xx_fast_reset(ag);
665
666 cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
667 cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
668 cfg2 |= (ag->duplex) ? MAC_CFG2_FDX : 0;
669
670 ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
671 ifctl &= ~(MAC_IFCTL_SPEED);
672
673 fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
674 fifo5 &= ~FIFO_CFG5_BM;
675
676 switch (ag->speed) {
677 case SPEED_1000:
678 cfg2 |= MAC_CFG2_IF_1000;
679 fifo5 |= FIFO_CFG5_BM;
680 break;
681 case SPEED_100:
682 cfg2 |= MAC_CFG2_IF_10_100;
683 ifctl |= MAC_IFCTL_SPEED;
684 break;
685 case SPEED_10:
686 cfg2 |= MAC_CFG2_IF_10_100;
687 break;
688 default:
689 BUG();
690 return;
691 }
692
693 if (ag->tx_ring.desc_split) {
694 ag->fifodata[2] &= 0xffff;
695 ag->fifodata[2] |= ((2048 - ag->tx_ring.desc_split) / 4) << 16;
696 }
697
698 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, ag->fifodata[2]);
699
700 if (update) {
701 if (of_device_is_compatible(np, "qca,ar7100-eth") ||
702 of_device_is_compatible(np, "qca,ar9130-eth")) {
703 ath79_set_pll(ag);
704 ath79_mii_ctrl_set_speed(ag);
705 } else if (of_device_is_compatible(np, "qca,ar7242-eth") ||
706 of_device_is_compatible(np, "qca,ar9340-eth") ||
707 of_device_is_compatible(np, "qca,qca9550-eth") ||
708 of_device_is_compatible(np, "qca,qca9560-eth")) {
709 ath79_set_pllval(ag);
710 }
711 }
712
713 ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
714 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
715 ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
716
717 if (of_device_is_compatible(np, "qca,qca9530-eth") ||
718 of_device_is_compatible(np, "qca,qca9560-eth")) {
719 /*
720 * The rx ring buffer can stall on small packets on QCA953x and
721 * QCA956x. Disabling the inline checksum engine fixes the stall.
722 * The wr, rr functions cannot be used since this hidden register
723 * is outside of the normal ag71xx register block.
724 */
725 void __iomem *dam = ioremap_nocache(0xb90001bc, 0x4);
726 if (dam) {
727 __raw_writel(__raw_readl(dam) & ~BIT(27), dam);
728 (void)__raw_readl(dam);
729 iounmap(dam);
730 }
731 }
732
733 ag71xx_hw_start(ag);
734
735 netif_carrier_on(ag->dev);
736 if (update && netif_msg_link(ag))
737 pr_info("%s: link up (%sMbps/%s duplex)\n",
738 ag->dev->name,
739 ag71xx_speed_str(ag),
740 (DUPLEX_FULL == ag->duplex) ? "Full" : "Half");
741
742 ag71xx_dump_regs(ag);
743 }
744
745 void ag71xx_link_adjust(struct ag71xx *ag)
746 {
747 __ag71xx_link_adjust(ag, true);
748 }
749
750 static int ag71xx_hw_enable(struct ag71xx *ag)
751 {
752 int ret;
753
754 ret = ag71xx_rings_init(ag);
755 if (ret)
756 return ret;
757
758 napi_enable(&ag->napi);
759 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
760 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
761 netif_start_queue(ag->dev);
762
763 return 0;
764 }
765
766 static void ag71xx_hw_disable(struct ag71xx *ag)
767 {
768 netif_stop_queue(ag->dev);
769
770 ag71xx_hw_stop(ag);
771 ag71xx_dma_reset(ag);
772
773 napi_disable(&ag->napi);
774 del_timer_sync(&ag->oom_timer);
775
776 ag71xx_rings_cleanup(ag);
777 }
778
779 static int ag71xx_open(struct net_device *dev)
780 {
781 struct ag71xx *ag = netdev_priv(dev);
782 unsigned int max_frame_len;
783 int ret;
784
785 netif_carrier_off(dev);
786 max_frame_len = ag71xx_max_frame_len(dev->mtu);
787 ag->rx_buf_size = SKB_DATA_ALIGN(max_frame_len + NET_SKB_PAD + NET_IP_ALIGN);
788
789 /* setup max frame length */
790 ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);
791 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
792
793 ret = ag71xx_hw_enable(ag);
794 if (ret)
795 goto err;
796
797 phy_start(ag->phy_dev);
798
799 return 0;
800
801 err:
802 ag71xx_rings_cleanup(ag);
803 return ret;
804 }
805
806 static int ag71xx_stop(struct net_device *dev)
807 {
808 unsigned long flags;
809 struct ag71xx *ag = netdev_priv(dev);
810
811 netif_carrier_off(dev);
812 phy_stop(ag->phy_dev);
813
814 spin_lock_irqsave(&ag->lock, flags);
815 if (ag->link) {
816 ag->link = 0;
817 ag71xx_link_adjust(ag);
818 }
819 spin_unlock_irqrestore(&ag->lock, flags);
820
821 ag71xx_hw_disable(ag);
822
823 return 0;
824 }
825
826 static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len)
827 {
828 int i;
829 struct ag71xx_desc *desc;
830 int ring_mask = BIT(ring->order) - 1;
831 int ndesc = 0;
832 int split = ring->desc_split;
833
834 if (!split)
835 split = len;
836
837 while (len > 0) {
838 unsigned int cur_len = len;
839
840 i = (ring->curr + ndesc) & ring_mask;
841 desc = ag71xx_ring_desc(ring, i);
842
843 if (!ag71xx_desc_empty(desc))
844 return -1;
845
846 if (cur_len > split) {
847 cur_len = split;
848
849 /*
850 * TX will hang if DMA transfers <= 4 bytes,
851 * make sure next segment is more than 4 bytes long.
852 */
853 if (len <= split + 4)
854 cur_len -= 4;
855 }
856
857 desc->data = addr;
858 addr += cur_len;
859 len -= cur_len;
860
861 if (len > 0)
862 cur_len |= DESC_MORE;
863
864 /* prevent early tx attempt of this descriptor */
865 if (!ndesc)
866 cur_len |= DESC_EMPTY;
867
868 desc->ctrl = cur_len;
869 ndesc++;
870 }
871
872 return ndesc;
873 }
874
875 static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
876 struct net_device *dev)
877 {
878 struct ag71xx *ag = netdev_priv(dev);
879 struct ag71xx_ring *ring = &ag->tx_ring;
880 int ring_mask = BIT(ring->order) - 1;
881 int ring_size = BIT(ring->order);
882 struct ag71xx_desc *desc;
883 dma_addr_t dma_addr;
884 int i, n, ring_min;
885
886 if (skb->len <= 4) {
887 DBG("%s: packet len is too small\n", ag->dev->name);
888 goto err_drop;
889 }
890
891 dma_addr = dma_map_single(&ag->pdev->dev, skb->data, skb->len,
892 DMA_TO_DEVICE);
893
894 i = ring->curr & ring_mask;
895 desc = ag71xx_ring_desc(ring, i);
896
897 /* setup descriptor fields */
898 n = ag71xx_fill_dma_desc(ring, (u32) dma_addr, skb->len & ag->desc_pktlen_mask);
899 if (n < 0)
900 goto err_drop_unmap;
901
902 i = (ring->curr + n - 1) & ring_mask;
903 ring->buf[i].len = skb->len;
904 ring->buf[i].skb = skb;
905
906 netdev_sent_queue(dev, skb->len);
907
908 skb_tx_timestamp(skb);
909
910 desc->ctrl &= ~DESC_EMPTY;
911 ring->curr += n;
912
913 /* flush descriptor */
914 wmb();
915
916 ring_min = 2;
917 if (ring->desc_split)
918 ring_min *= AG71XX_TX_RING_DS_PER_PKT;
919
920 if (ring->curr - ring->dirty >= ring_size - ring_min) {
921 DBG("%s: tx queue full\n", dev->name);
922 netif_stop_queue(dev);
923 }
924
925 DBG("%s: packet injected into TX queue\n", ag->dev->name);
926
927 /* enable TX engine */
928 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
929
930 return NETDEV_TX_OK;
931
932 err_drop_unmap:
933 dma_unmap_single(&ag->pdev->dev, dma_addr, skb->len, DMA_TO_DEVICE);
934
935 err_drop:
936 dev->stats.tx_dropped++;
937
938 dev_kfree_skb(skb);
939 return NETDEV_TX_OK;
940 }
941
942 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
943 {
944 struct ag71xx *ag = netdev_priv(dev);
945
946
947 switch (cmd) {
948 case SIOCSIFHWADDR:
949 if (copy_from_user
950 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
951 return -EFAULT;
952 return 0;
953
954 case SIOCGIFHWADDR:
955 if (copy_to_user
956 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
957 return -EFAULT;
958 return 0;
959
960 case SIOCGMIIPHY:
961 case SIOCGMIIREG:
962 case SIOCSMIIREG:
963 if (ag->phy_dev == NULL)
964 break;
965
966 return phy_mii_ioctl(ag->phy_dev, ifr, cmd);
967
968 default:
969 break;
970 }
971
972 return -EOPNOTSUPP;
973 }
974
975 #if (LINUX_VERSION_CODE < KERNEL_VERSION(4,15,0))
976 static void ag71xx_oom_timer_handler(unsigned long data)
977 {
978 struct net_device *dev = (struct net_device *) data;
979 struct ag71xx *ag = netdev_priv(dev);
980 #else
981 static void ag71xx_oom_timer_handler(struct timer_list *t)
982 {
983 struct ag71xx *ag = from_timer(ag, t, oom_timer);
984 #endif
985
986 napi_schedule(&ag->napi);
987 }
988
989 static void ag71xx_tx_timeout(struct net_device *dev)
990 {
991 struct ag71xx *ag = netdev_priv(dev);
992
993 if (netif_msg_tx_err(ag))
994 pr_info("%s: tx timeout\n", ag->dev->name);
995
996 schedule_delayed_work(&ag->restart_work, 1);
997 }
998
999 static void ag71xx_restart_work_func(struct work_struct *work)
1000 {
1001 struct ag71xx *ag = container_of(work, struct ag71xx, restart_work.work);
1002
1003 rtnl_lock();
1004 ag71xx_hw_disable(ag);
1005 ag71xx_hw_enable(ag);
1006 if (ag->link)
1007 __ag71xx_link_adjust(ag, false);
1008 rtnl_unlock();
1009 }
1010
1011 static bool ag71xx_check_dma_stuck(struct ag71xx *ag)
1012 {
1013 unsigned long timestamp;
1014 u32 rx_sm, tx_sm, rx_fd;
1015
1016 timestamp = netdev_get_tx_queue(ag->dev, 0)->trans_start;
1017 if (likely(time_before(jiffies, timestamp + HZ/10)))
1018 return false;
1019
1020 if (!netif_carrier_ok(ag->dev))
1021 return false;
1022
1023 rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
1024 if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
1025 return true;
1026
1027 tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
1028 rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
1029 if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
1030 ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
1031 return true;
1032
1033 return false;
1034 }
1035
1036 static int ag71xx_tx_packets(struct ag71xx *ag, bool flush)
1037 {
1038 struct ag71xx_ring *ring = &ag->tx_ring;
1039 bool dma_stuck = false;
1040 int ring_mask = BIT(ring->order) - 1;
1041 int ring_size = BIT(ring->order);
1042 int sent = 0;
1043 int bytes_compl = 0;
1044 int n = 0;
1045
1046 DBG("%s: processing TX ring\n", ag->dev->name);
1047
1048 while (ring->dirty + n != ring->curr) {
1049 unsigned int i = (ring->dirty + n) & ring_mask;
1050 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1051 struct sk_buff *skb = ring->buf[i].skb;
1052
1053 if (!flush && !ag71xx_desc_empty(desc)) {
1054 if (ag->tx_hang_workaround &&
1055 ag71xx_check_dma_stuck(ag)) {
1056 schedule_delayed_work(&ag->restart_work, HZ / 2);
1057 dma_stuck = true;
1058 }
1059 break;
1060 }
1061
1062 if (flush)
1063 desc->ctrl |= DESC_EMPTY;
1064
1065 n++;
1066 if (!skb)
1067 continue;
1068
1069 dev_kfree_skb_any(skb);
1070 ring->buf[i].skb = NULL;
1071
1072 bytes_compl += ring->buf[i].len;
1073
1074 sent++;
1075 ring->dirty += n;
1076
1077 while (n > 0) {
1078 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
1079 n--;
1080 }
1081 }
1082
1083 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
1084
1085 if (!sent)
1086 return 0;
1087
1088 ag->dev->stats.tx_bytes += bytes_compl;
1089 ag->dev->stats.tx_packets += sent;
1090
1091 netdev_completed_queue(ag->dev, sent, bytes_compl);
1092 if ((ring->curr - ring->dirty) < (ring_size * 3) / 4)
1093 netif_wake_queue(ag->dev);
1094
1095 if (!dma_stuck)
1096 cancel_delayed_work(&ag->restart_work);
1097
1098 return sent;
1099 }
1100
1101 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
1102 {
1103 struct net_device *dev = ag->dev;
1104 struct ag71xx_ring *ring = &ag->rx_ring;
1105 unsigned int pktlen_mask = ag->desc_pktlen_mask;
1106 unsigned int offset = ag->rx_buf_offset;
1107 int ring_mask = BIT(ring->order) - 1;
1108 int ring_size = BIT(ring->order);
1109 struct sk_buff_head queue;
1110 struct sk_buff *skb;
1111 int done = 0;
1112
1113 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
1114 dev->name, limit, ring->curr, ring->dirty);
1115
1116 skb_queue_head_init(&queue);
1117
1118 while (done < limit) {
1119 unsigned int i = ring->curr & ring_mask;
1120 struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
1121 int pktlen;
1122 int err = 0;
1123
1124 if (ag71xx_desc_empty(desc))
1125 break;
1126
1127 if ((ring->dirty + ring_size) == ring->curr) {
1128 ag71xx_assert(0);
1129 break;
1130 }
1131
1132 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
1133
1134 pktlen = desc->ctrl & pktlen_mask;
1135 pktlen -= ETH_FCS_LEN;
1136
1137 dma_unmap_single(&ag->pdev->dev, ring->buf[i].dma_addr,
1138 ag->rx_buf_size, DMA_FROM_DEVICE);
1139
1140 dev->stats.rx_packets++;
1141 dev->stats.rx_bytes += pktlen;
1142
1143 skb = build_skb(ring->buf[i].rx_buf, ag71xx_buffer_size(ag));
1144 if (!skb) {
1145 skb_free_frag(ring->buf[i].rx_buf);
1146 goto next;
1147 }
1148
1149 skb_reserve(skb, offset);
1150 skb_put(skb, pktlen);
1151
1152 if (err) {
1153 dev->stats.rx_dropped++;
1154 kfree_skb(skb);
1155 } else {
1156 skb->dev = dev;
1157 skb->ip_summed = CHECKSUM_NONE;
1158 __skb_queue_tail(&queue, skb);
1159 }
1160
1161 next:
1162 ring->buf[i].rx_buf = NULL;
1163 done++;
1164
1165 ring->curr++;
1166 }
1167
1168 ag71xx_ring_rx_refill(ag);
1169
1170 while ((skb = __skb_dequeue(&queue)) != NULL) {
1171 skb->protocol = eth_type_trans(skb, dev);
1172 netif_receive_skb(skb);
1173 }
1174
1175 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
1176 dev->name, ring->curr, ring->dirty, done);
1177
1178 return done;
1179 }
1180
1181 static int ag71xx_poll(struct napi_struct *napi, int limit)
1182 {
1183 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
1184 struct net_device *dev = ag->dev;
1185 struct ag71xx_ring *rx_ring = &ag->rx_ring;
1186 int rx_ring_size = BIT(rx_ring->order);
1187 unsigned long flags;
1188 u32 status;
1189 int tx_done;
1190 int rx_done;
1191
1192 tx_done = ag71xx_tx_packets(ag, false);
1193
1194 DBG("%s: processing RX ring\n", dev->name);
1195 rx_done = ag71xx_rx_packets(ag, limit);
1196
1197 ag71xx_debugfs_update_napi_stats(ag, rx_done, tx_done);
1198
1199 if (rx_ring->buf[rx_ring->dirty % rx_ring_size].rx_buf == NULL)
1200 goto oom;
1201
1202 status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
1203 if (unlikely(status & RX_STATUS_OF)) {
1204 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
1205 dev->stats.rx_fifo_errors++;
1206
1207 /* restart RX */
1208 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
1209 }
1210
1211 if (rx_done < limit) {
1212 if (status & RX_STATUS_PR)
1213 goto more;
1214
1215 status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
1216 if (status & TX_STATUS_PS)
1217 goto more;
1218
1219 DBG("%s: disable polling mode, rx=%d, tx=%d,limit=%d\n",
1220 dev->name, rx_done, tx_done, limit);
1221
1222 napi_complete(napi);
1223
1224 /* enable interrupts */
1225 spin_lock_irqsave(&ag->lock, flags);
1226 ag71xx_int_enable(ag, AG71XX_INT_POLL);
1227 spin_unlock_irqrestore(&ag->lock, flags);
1228 return rx_done;
1229 }
1230
1231 more:
1232 DBG("%s: stay in polling mode, rx=%d, tx=%d, limit=%d\n",
1233 dev->name, rx_done, tx_done, limit);
1234 return limit;
1235
1236 oom:
1237 if (netif_msg_rx_err(ag))
1238 pr_info("%s: out of memory\n", dev->name);
1239
1240 mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
1241 napi_complete(napi);
1242 return 0;
1243 }
1244
1245 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
1246 {
1247 struct net_device *dev = dev_id;
1248 struct ag71xx *ag = netdev_priv(dev);
1249 u32 status;
1250
1251 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
1252 ag71xx_dump_intr(ag, "raw", status);
1253
1254 if (unlikely(!status))
1255 return IRQ_NONE;
1256
1257 if (unlikely(status & AG71XX_INT_ERR)) {
1258 if (status & AG71XX_INT_TX_BE) {
1259 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
1260 dev_err(&dev->dev, "TX BUS error\n");
1261 }
1262 if (status & AG71XX_INT_RX_BE) {
1263 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
1264 dev_err(&dev->dev, "RX BUS error\n");
1265 }
1266 }
1267
1268 if (likely(status & AG71XX_INT_POLL)) {
1269 ag71xx_int_disable(ag, AG71XX_INT_POLL);
1270 DBG("%s: enable polling mode\n", dev->name);
1271 napi_schedule(&ag->napi);
1272 }
1273
1274 ag71xx_debugfs_update_int_stats(ag, status);
1275
1276 return IRQ_HANDLED;
1277 }
1278
1279 static int ag71xx_change_mtu(struct net_device *dev, int new_mtu)
1280 {
1281 struct ag71xx *ag = netdev_priv(dev);
1282
1283 dev->mtu = new_mtu;
1284 ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
1285 ag71xx_max_frame_len(dev->mtu));
1286
1287 return 0;
1288 }
1289
1290 static const struct net_device_ops ag71xx_netdev_ops = {
1291 .ndo_open = ag71xx_open,
1292 .ndo_stop = ag71xx_stop,
1293 .ndo_start_xmit = ag71xx_hard_start_xmit,
1294 .ndo_do_ioctl = ag71xx_do_ioctl,
1295 .ndo_tx_timeout = ag71xx_tx_timeout,
1296 .ndo_change_mtu = ag71xx_change_mtu,
1297 .ndo_set_mac_address = eth_mac_addr,
1298 .ndo_validate_addr = eth_validate_addr,
1299 };
1300
1301 static int ag71xx_probe(struct platform_device *pdev)
1302 {
1303 struct device_node *np = pdev->dev.of_node;
1304 struct net_device *dev;
1305 struct resource *res;
1306 struct ag71xx *ag;
1307 const void *mac_addr;
1308 u32 max_frame_len;
1309 int tx_size, err;
1310
1311 if (!np)
1312 return -ENODEV;
1313
1314 dev = devm_alloc_etherdev(&pdev->dev, sizeof(*ag));
1315 if (!dev)
1316 return -ENOMEM;
1317
1318 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1319 if (!res)
1320 return -EINVAL;
1321
1322 err = ag71xx_setup_gmac(np);
1323 if (err)
1324 return err;
1325
1326 SET_NETDEV_DEV(dev, &pdev->dev);
1327
1328 ag = netdev_priv(dev);
1329 ag->pdev = pdev;
1330 ag->dev = dev;
1331 ag->msg_enable = netif_msg_init(ag71xx_msg_level,
1332 AG71XX_DEFAULT_MSG_ENABLE);
1333 spin_lock_init(&ag->lock);
1334
1335 ag->mac_reset = devm_reset_control_get_exclusive(&pdev->dev, "mac");
1336 if (IS_ERR(ag->mac_reset)) {
1337 dev_err(&pdev->dev, "missing mac reset\n");
1338 return PTR_ERR(ag->mac_reset);
1339 }
1340
1341 ag->mdio_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "mdio");
1342
1343 if (of_property_read_u32_array(np, "fifo-data", ag->fifodata, 3)) {
1344 if (of_device_is_compatible(np, "qca,ar9130-eth") ||
1345 of_device_is_compatible(np, "qca,ar7100-eth")) {
1346 ag->fifodata[0] = 0x0fff0000;
1347 ag->fifodata[1] = 0x00001fff;
1348 } else {
1349 ag->fifodata[0] = 0x0010ffff;
1350 ag->fifodata[1] = 0x015500aa;
1351 ag->fifodata[2] = 0x01f00140;
1352 }
1353 if (of_device_is_compatible(np, "qca,ar9130-eth"))
1354 ag->fifodata[2] = 0x00780fff;
1355 else if (of_device_is_compatible(np, "qca,ar7100-eth"))
1356 ag->fifodata[2] = 0x008001ff;
1357 }
1358
1359 if (of_property_read_u32_array(np, "pll-data", ag->plldata, 3))
1360 dev_dbg(&pdev->dev, "failed to read pll-data property\n");
1361
1362 if (of_property_read_u32_array(np, "pll-reg", ag->pllreg, 3))
1363 dev_dbg(&pdev->dev, "failed to read pll-reg property\n");
1364
1365 ag->pllregmap = syscon_regmap_lookup_by_phandle(np, "pll-handle");
1366 if (IS_ERR(ag->pllregmap)) {
1367 dev_dbg(&pdev->dev, "failed to read pll-handle property\n");
1368 ag->pllregmap = NULL;
1369 }
1370
1371 ag->mac_base = devm_ioremap_nocache(&pdev->dev, res->start,
1372 res->end - res->start + 1);
1373 if (!ag->mac_base)
1374 return -ENOMEM;
1375
1376 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1377 if (res) {
1378 ag->mii_base = devm_ioremap_nocache(&pdev->dev, res->start,
1379 res->end - res->start + 1);
1380 if (!ag->mii_base)
1381 return -ENOMEM;
1382 }
1383
1384 dev->irq = platform_get_irq(pdev, 0);
1385 err = devm_request_irq(&pdev->dev, dev->irq, ag71xx_interrupt,
1386 0x0, dev_name(&pdev->dev), dev);
1387 if (err) {
1388 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
1389 return err;
1390 }
1391
1392 dev->netdev_ops = &ag71xx_netdev_ops;
1393 dev->ethtool_ops = &ag71xx_ethtool_ops;
1394
1395 INIT_DELAYED_WORK(&ag->restart_work, ag71xx_restart_work_func);
1396
1397 #if (LINUX_VERSION_CODE < KERNEL_VERSION(4,15,0))
1398 init_timer(&ag->oom_timer);
1399 ag->oom_timer.data = (unsigned long) dev;
1400 ag->oom_timer.function = ag71xx_oom_timer_handler;
1401 #else
1402 timer_setup(&ag->oom_timer, ag71xx_oom_timer_handler, 0);
1403 #endif
1404
1405 tx_size = AG71XX_TX_RING_SIZE_DEFAULT;
1406 ag->rx_ring.order = ag71xx_ring_size_order(AG71XX_RX_RING_SIZE_DEFAULT);
1407
1408 if (of_device_is_compatible(np, "qca,ar9340-eth") ||
1409 of_device_is_compatible(np, "qca,qca9530-eth") ||
1410 of_device_is_compatible(np, "qca,qca9550-eth") ||
1411 of_device_is_compatible(np, "qca,qca9560-eth"))
1412 ag->desc_pktlen_mask = SZ_16K - 1;
1413 else
1414 ag->desc_pktlen_mask = SZ_4K - 1;
1415
1416 if (ag->desc_pktlen_mask == SZ_16K - 1 &&
1417 !of_device_is_compatible(np, "qca,qca9550-eth") &&
1418 !of_device_is_compatible(np, "qca,qca9560-eth"))
1419 max_frame_len = ag->desc_pktlen_mask;
1420 else
1421 max_frame_len = 1540;
1422
1423 dev->min_mtu = 68;
1424 dev->max_mtu = max_frame_len - ag71xx_max_frame_len(0);
1425
1426 if (of_device_is_compatible(np, "qca,ar7240-eth") ||
1427 of_device_is_compatible(np, "qca,ar7241-eth") ||
1428 of_device_is_compatible(np, "qca,ar7242-eth") ||
1429 of_device_is_compatible(np, "qca,ar9330-eth") ||
1430 of_device_is_compatible(np, "qca,ar9340-eth") ||
1431 of_device_is_compatible(np, "qca,qca9530-eth") ||
1432 of_device_is_compatible(np, "qca,qca9550-eth") ||
1433 of_device_is_compatible(np, "qca,qca9560-eth"))
1434 ag->tx_hang_workaround = 1;
1435
1436 ag->rx_buf_offset = NET_SKB_PAD;
1437 if (!of_device_is_compatible(np, "qca,ar7100-eth") &&
1438 !of_device_is_compatible(np, "qca,ar9130-eth"))
1439 ag->rx_buf_offset += NET_IP_ALIGN;
1440
1441 if (of_device_is_compatible(np, "qca,ar7100-eth")) {
1442 ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT;
1443 tx_size *= AG71XX_TX_RING_DS_PER_PKT;
1444 }
1445 ag->tx_ring.order = ag71xx_ring_size_order(tx_size);
1446
1447 ag->stop_desc = dmam_alloc_coherent(&pdev->dev,
1448 sizeof(struct ag71xx_desc),
1449 &ag->stop_desc_dma, GFP_KERNEL);
1450 if (!ag->stop_desc)
1451 return -ENOMEM;
1452
1453 ag->stop_desc->data = 0;
1454 ag->stop_desc->ctrl = 0;
1455 ag->stop_desc->next = (u32) ag->stop_desc_dma;
1456
1457 mac_addr = of_get_mac_address(np);
1458 if (mac_addr)
1459 memcpy(dev->dev_addr, mac_addr, ETH_ALEN);
1460 if (!mac_addr || !is_valid_ether_addr(dev->dev_addr)) {
1461 dev_err(&pdev->dev, "invalid MAC address, using random address\n");
1462 eth_random_addr(dev->dev_addr);
1463 }
1464
1465 ag->phy_if_mode = of_get_phy_mode(np);
1466 if (ag->phy_if_mode < 0) {
1467 dev_err(&pdev->dev, "missing phy-mode property in DT\n");
1468 return ag->phy_if_mode;
1469 }
1470
1471 if (of_property_read_u32(np, "qca,mac-idx", &ag->mac_idx))
1472 ag->mac_idx = -1;
1473 if (ag->mii_base)
1474 switch (ag->mac_idx) {
1475 case 0:
1476 ath79_mii0_ctrl_set_if(ag);
1477 break;
1478 case 1:
1479 ath79_mii1_ctrl_set_if(ag);
1480 break;
1481 default:
1482 break;
1483 }
1484
1485 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
1486
1487 ag71xx_dump_regs(ag);
1488
1489 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, 0);
1490
1491 ag71xx_hw_init(ag);
1492
1493 ag71xx_dump_regs(ag);
1494
1495 /*
1496 * populate current node to register mdio-bus as a subdevice.
1497 * the mdio bus works independently on ar7241 and later chips
1498 * and we need to load mdio1 before gmac0, which can be done
1499 * by adding a "simple-mfd" compatible to gmac node. The
1500 * following code checks OF_POPULATED_BUS flag before populating
1501 * to avoid duplicated population.
1502 */
1503 if (!of_node_check_flag(np, OF_POPULATED_BUS)) {
1504 err = of_platform_populate(np, NULL, NULL, &pdev->dev);
1505 if (err)
1506 return err;
1507 }
1508
1509 err = ag71xx_phy_connect(ag);
1510 if (err)
1511 return err;
1512
1513 err = ag71xx_debugfs_init(ag);
1514 if (err)
1515 goto err_phy_disconnect;
1516
1517 platform_set_drvdata(pdev, dev);
1518
1519 err = register_netdev(dev);
1520 if (err) {
1521 dev_err(&pdev->dev, "unable to register net device\n");
1522 platform_set_drvdata(pdev, NULL);
1523 ag71xx_debugfs_exit(ag);
1524 goto err_phy_disconnect;
1525 }
1526
1527 pr_info("%s: Atheros AG71xx at 0x%08lx, irq %d, mode: %s\n",
1528 dev->name, (unsigned long) ag->mac_base, dev->irq,
1529 phy_modes(ag->phy_if_mode));
1530
1531 return 0;
1532
1533 err_phy_disconnect:
1534 ag71xx_phy_disconnect(ag);
1535 return err;
1536 }
1537
1538 static int ag71xx_remove(struct platform_device *pdev)
1539 {
1540 struct net_device *dev = platform_get_drvdata(pdev);
1541 struct ag71xx *ag;
1542
1543 if (!dev)
1544 return 0;
1545
1546 ag = netdev_priv(dev);
1547 ag71xx_debugfs_exit(ag);
1548 ag71xx_phy_disconnect(ag);
1549 unregister_netdev(dev);
1550 platform_set_drvdata(pdev, NULL);
1551 return 0;
1552 }
1553
1554 static const struct of_device_id ag71xx_match[] = {
1555 { .compatible = "qca,ar7100-eth" },
1556 { .compatible = "qca,ar7240-eth" },
1557 { .compatible = "qca,ar7241-eth" },
1558 { .compatible = "qca,ar7242-eth" },
1559 { .compatible = "qca,ar9130-eth" },
1560 { .compatible = "qca,ar9330-eth" },
1561 { .compatible = "qca,ar9340-eth" },
1562 { .compatible = "qca,qca9530-eth" },
1563 { .compatible = "qca,qca9550-eth" },
1564 { .compatible = "qca,qca9560-eth" },
1565 {}
1566 };
1567
1568 static struct platform_driver ag71xx_driver = {
1569 .probe = ag71xx_probe,
1570 .remove = ag71xx_remove,
1571 .driver = {
1572 .name = AG71XX_DRV_NAME,
1573 .of_match_table = ag71xx_match,
1574 }
1575 };
1576
1577 static int __init ag71xx_module_init(void)
1578 {
1579 int ret;
1580
1581 ret = ag71xx_debugfs_root_init();
1582 if (ret)
1583 goto err_out;
1584
1585 ret = platform_driver_register(&ag71xx_driver);
1586 if (ret)
1587 goto err_debugfs_exit;
1588
1589 return 0;
1590
1591 err_debugfs_exit:
1592 ag71xx_debugfs_root_exit();
1593 err_out:
1594 return ret;
1595 }
1596
1597 static void __exit ag71xx_module_exit(void)
1598 {
1599 platform_driver_unregister(&ag71xx_driver);
1600 ag71xx_debugfs_root_exit();
1601 }
1602
1603 module_init(ag71xx_module_init);
1604 module_exit(ag71xx_module_exit);
1605
1606 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1607 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
1608 MODULE_AUTHOR("Felix Fietkau <nbd@nbd.name>");
1609 MODULE_LICENSE("GPL v2");
1610 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);
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