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[openwrt/openwrt.git] / target / linux / atheros / patches-3.14 / 100-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -144,6 +144,19 @@ config BCM63XX
4 help
5 Support for BCM63XX based boards
6
7 +config ATHEROS_AR231X
8 + bool "Atheros 231x/531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_BIG_ENDIAN
15 + select SYS_SUPPORTS_32BIT_KERNEL
16 + select ARCH_REQUIRE_GPIOLIB
17 + help
18 + Support for AR231x and AR531x based boards
19 +
20 config MIPS_COBALT
21 bool "Cobalt Server"
22 select CEVT_R4K
23 @@ -795,6 +808,7 @@ config NLM_XLP_BOARD
24
25 endchoice
26
27 +source "arch/mips/ar231x/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/ath79/Kconfig"
30 source "arch/mips/bcm47xx/Kconfig"
31 --- a/arch/mips/Kbuild.platforms
32 +++ b/arch/mips/Kbuild.platforms
33 @@ -6,6 +6,7 @@ platforms += ath79
34 platforms += bcm47xx
35 platforms += bcm63xx
36 platforms += cavium-octeon
37 +platforms += ar231x
38 platforms += cobalt
39 platforms += dec
40 platforms += emma
41 --- /dev/null
42 +++ b/arch/mips/ar231x/Platform
43 @@ -0,0 +1,6 @@
44 +#
45 +# Atheros AR531X/AR231X WiSoC
46 +#
47 +platform-$(CONFIG_ATHEROS_AR231X) += ar231x/
48 +cflags-$(CONFIG_ATHEROS_AR231X) += -I$(srctree)/arch/mips/include/asm/mach-ar231x
49 +load-$(CONFIG_ATHEROS_AR231X) += 0xffffffff80041000
50 --- /dev/null
51 +++ b/arch/mips/ar231x/Kconfig
52 @@ -0,0 +1,16 @@
53 +config ATHEROS_AR5312
54 + bool "Atheros 5312/2312+ support"
55 + depends on ATHEROS_AR231X
56 + default y
57 +
58 +config ATHEROS_AR2315
59 + bool "Atheros 2315+ support"
60 + depends on ATHEROS_AR231X
61 + select DMA_NONCOHERENT
62 + select CEVT_R4K
63 + select CSRC_R4K
64 + select IRQ_CPU
65 + select SYS_HAS_CPU_MIPS32_R1
66 + select SYS_SUPPORTS_32BIT_KERNEL
67 + select SYS_SUPPORTS_BIG_ENDIAN
68 + default y
69 --- /dev/null
70 +++ b/arch/mips/ar231x/Makefile
71 @@ -0,0 +1,13 @@
72 +#
73 +# This file is subject to the terms and conditions of the GNU General Public
74 +# License. See the file "COPYING" in the main directory of this archive
75 +# for more details.
76 +#
77 +# Copyright (C) 2006 FON Technology, SL.
78 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
79 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
80 +#
81 +
82 +obj-y += board.o prom.o devices.o
83 +obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
84 +obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
85 --- /dev/null
86 +++ b/arch/mips/ar231x/board.c
87 @@ -0,0 +1,263 @@
88 +/*
89 + * This file is subject to the terms and conditions of the GNU General Public
90 + * License. See the file "COPYING" in the main directory of this archive
91 + * for more details.
92 + *
93 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
94 + * Copyright (C) 2006 FON Technology, SL.
95 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
96 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
97 + */
98 +
99 +#include <generated/autoconf.h>
100 +#include <linux/init.h>
101 +#include <linux/module.h>
102 +#include <linux/types.h>
103 +#include <linux/string.h>
104 +#include <linux/platform_device.h>
105 +#include <linux/kernel.h>
106 +#include <linux/random.h>
107 +#include <linux/etherdevice.h>
108 +#include <linux/irq.h>
109 +#include <linux/io.h>
110 +#include <asm/irq_cpu.h>
111 +#include <asm/reboot.h>
112 +#include <asm/bootinfo.h>
113 +#include <asm/time.h>
114 +
115 +#include <ar231x_platform.h>
116 +#include "devices.h"
117 +#include "ar5312.h"
118 +#include "ar2315.h"
119 +
120 +void (*ar231x_irq_dispatch)(void);
121 +
122 +static inline bool
123 +check_radio_magic(u8 *addr)
124 +{
125 + addr += 0x7a; /* offset for flash magic */
126 + if ((addr[0] == 0x5a) && (addr[1] == 0xa5))
127 + return 1;
128 +
129 + return 0;
130 +}
131 +
132 +static inline bool
133 +check_board_data(u8 *flash_limit, u8 *addr, bool broken)
134 +{
135 + /* config magic found */
136 + if (*((u32 *)addr) == AR231X_BD_MAGIC)
137 + return 1;
138 +
139 + if (!broken)
140 + return 0;
141 +
142 + if (check_radio_magic(addr + 0xf8))
143 + ar231x_board.radio = addr + 0xf8;
144 + if ((addr < flash_limit + 0x10000) &&
145 + check_radio_magic(addr + 0x10000))
146 + ar231x_board.radio = addr + 0x10000;
147 +
148 + if (ar231x_board.radio) {
149 + /* broken board data detected, use radio data to find the
150 + * offset, user will fix this */
151 + return 1;
152 + }
153 + return 0;
154 +}
155 +
156 +static u8 *
157 +find_board_config(u8 *flash_limit, bool broken)
158 +{
159 + u8 *addr;
160 + int found = 0;
161 +
162 + for (addr = flash_limit - 0x1000;
163 + addr >= flash_limit - 0x30000;
164 + addr -= 0x1000) {
165 +
166 + if (check_board_data(flash_limit, addr, broken)) {
167 + found = 1;
168 + break;
169 + }
170 + }
171 +
172 + if (!found)
173 + addr = NULL;
174 +
175 + return addr;
176 +}
177 +
178 +static u8 *
179 +find_radio_config(u8 *flash_limit, u8 *board_config)
180 +{
181 + int found;
182 + u8 *radio_config;
183 +
184 + /*
185 + * Now find the start of Radio Configuration data, using heuristics:
186 + * Search forward from Board Configuration data by 0x1000 bytes
187 + * at a time until we find non-0xffffffff.
188 + */
189 + found = 0;
190 + for (radio_config = board_config + 0x1000;
191 + (radio_config < flash_limit);
192 + radio_config += 0x1000) {
193 + if ((*(u32 *)radio_config != 0xffffffff) &&
194 + check_radio_magic(radio_config)) {
195 + found = 1;
196 + break;
197 + }
198 + }
199 +
200 + /* AR2316 relocates radio config to new location */
201 + if (!found) {
202 + for (radio_config = board_config + 0xf8;
203 + (radio_config < flash_limit - 0x1000 + 0xf8);
204 + radio_config += 0x1000) {
205 + if ((*(u32 *)radio_config != 0xffffffff) &&
206 + check_radio_magic(radio_config)) {
207 + found = 1;
208 + break;
209 + }
210 + }
211 + }
212 +
213 + if (!found) {
214 + pr_warn("WARNING: Could not find Radio Configuration data\n");
215 + radio_config = NULL;
216 + }
217 +
218 + return radio_config;
219 +}
220 +
221 +int __init
222 +ar231x_find_config(u8 *flash_limit)
223 +{
224 + struct ar231x_boarddata *config;
225 + unsigned int rcfg_size;
226 + int broken_boarddata = 0;
227 + u8 *bcfg, *rcfg;
228 + u8 *board_data;
229 + u8 *radio_data;
230 + u8 *mac_addr;
231 + u32 offset;
232 +
233 + ar231x_board.config = NULL;
234 + ar231x_board.radio = NULL;
235 + /* Copy the board and radio data to RAM, because accessing the mapped
236 + * memory of the flash directly after booting is not safe */
237 +
238 + /* Try to find valid board and radio data */
239 + bcfg = find_board_config(flash_limit, false);
240 +
241 + /* If that fails, try to at least find valid radio data */
242 + if (!bcfg) {
243 + bcfg = find_board_config(flash_limit, true);
244 + broken_boarddata = 1;
245 + }
246 +
247 + if (!bcfg) {
248 + pr_warn("WARNING: No board configuration data found!\n");
249 + return -ENODEV;
250 + }
251 +
252 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
253 + ar231x_board.config = (struct ar231x_boarddata *)board_data;
254 + memcpy(board_data, bcfg, 0x100);
255 + if (broken_boarddata) {
256 + pr_warn("WARNING: broken board data detected\n");
257 + config = ar231x_board.config;
258 + if (!memcmp(config->enet0_mac, "\x00\x00\x00\x00\x00\x00", 6)) {
259 + pr_info("Fixing up empty mac addresses\n");
260 + config->reset_config_gpio = 0xffff;
261 + config->sys_led_gpio = 0xffff;
262 + random_ether_addr(config->wlan0_mac);
263 + config->wlan0_mac[0] &= ~0x06;
264 + random_ether_addr(config->enet0_mac);
265 + random_ether_addr(config->enet1_mac);
266 + }
267 + }
268 +
269 +
270 + /* Radio config starts 0x100 bytes after board config, regardless
271 + * of what the physical layout on the flash chip looks like */
272 +
273 + if (ar231x_board.radio)
274 + rcfg = (u8 *)ar231x_board.radio;
275 + else
276 + rcfg = find_radio_config(flash_limit, bcfg);
277 +
278 + if (!rcfg)
279 + return -ENODEV;
280 +
281 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
282 + ar231x_board.radio = radio_data;
283 + offset = radio_data - board_data;
284 + pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
285 + offset);
286 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
287 + memcpy(radio_data, rcfg, rcfg_size);
288 +
289 + mac_addr = &radio_data[0x1d * 2];
290 + if (is_broadcast_ether_addr(mac_addr)) {
291 + pr_info("Radio MAC is blank; using board-data\n");
292 + memcpy(mac_addr, ar231x_board.config->wlan0_mac, ETH_ALEN);
293 + }
294 +
295 + return 0;
296 +}
297 +
298 +static void
299 +ar231x_halt(void)
300 +{
301 + local_irq_disable();
302 + while (1)
303 + ;
304 +}
305 +
306 +void __init
307 +plat_mem_setup(void)
308 +{
309 + _machine_halt = ar231x_halt;
310 + pm_power_off = ar231x_halt;
311 +
312 + ar5312_plat_setup();
313 + ar2315_plat_setup();
314 +
315 + /* Disable data watchpoints */
316 + write_c0_watchlo0(0);
317 +}
318 +
319 +
320 +asmlinkage void
321 +plat_irq_dispatch(void)
322 +{
323 + ar231x_irq_dispatch();
324 +}
325 +
326 +void __init
327 +plat_time_init(void)
328 +{
329 + ar5312_time_init();
330 + ar2315_time_init();
331 +}
332 +
333 +unsigned int __cpuinit
334 +get_c0_compare_int(void)
335 +{
336 + return CP0_LEGACY_COMPARE_IRQ;
337 +}
338 +
339 +void __init
340 +arch_init_irq(void)
341 +{
342 + clear_c0_status(ST0_IM);
343 + mips_cpu_irq_init();
344 +
345 + /* Initialize interrupt controllers */
346 + ar5312_irq_init();
347 + ar2315_irq_init();
348 +}
349 +
350 +
351 --- /dev/null
352 +++ b/arch/mips/ar231x/prom.c
353 @@ -0,0 +1,37 @@
354 +/*
355 + * This file is subject to the terms and conditions of the GNU General Public
356 + * License. See the file "COPYING" in the main directory of this archive
357 + * for more details.
358 + *
359 + * Copyright MontaVista Software Inc
360 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
361 + * Copyright (C) 2006 FON Technology, SL.
362 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
363 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
364 + */
365 +
366 +/*
367 + * Prom setup file for ar231x
368 + */
369 +
370 +#include <linux/init.h>
371 +#include <generated/autoconf.h>
372 +#include <linux/kernel.h>
373 +#include <linux/string.h>
374 +#include <linux/mm.h>
375 +#include <linux/bootmem.h>
376 +
377 +#include <asm/bootinfo.h>
378 +#include <asm/addrspace.h>
379 +#include "ar5312.h"
380 +#include "ar2315.h"
381 +
382 +void __init prom_init(void)
383 +{
384 + ar5312_prom_init();
385 + ar2315_prom_init();
386 +}
387 +
388 +void __init prom_free_prom_memory(void)
389 +{
390 +}
391 --- /dev/null
392 +++ b/arch/mips/include/asm/mach-ar231x/ar231x_platform.h
393 @@ -0,0 +1,83 @@
394 +#ifndef __ASM_MACH_AR231X_PLATFORM_H
395 +#define __ASM_MACH_AR231X_PLATFORM_H
396 +
397 +/*
398 + * This is board-specific data that is stored in a "fixed" location in flash.
399 + * It is shared across operating systems, so it should not be changed lightly.
400 + * The main reason we need it is in order to extract the ethernet MAC
401 + * address(es).
402 + */
403 +struct ar231x_boarddata {
404 + u32 magic; /* board data is valid */
405 +#define AR231X_BD_MAGIC 0x35333131 /* "5311", for all 531x/231x platforms */
406 + u16 cksum; /* checksum (starting with BD_REV 2) */
407 + u16 rev; /* revision of this struct */
408 +#define BD_REV 4
409 + char board_name[64]; /* Name of board */
410 + u16 major; /* Board major number */
411 + u16 minor; /* Board minor number */
412 + u32 flags; /* Board configuration */
413 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
414 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
415 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
416 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
417 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
418 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
419 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
420 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
421 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
422 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
423 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
424 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
425 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
426 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
427 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
428 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
429 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
430 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
431 + u16 reset_config_gpio; /* Reset factory GPIO pin */
432 + u16 sys_led_gpio; /* System LED GPIO pin */
433 +
434 + u32 cpu_freq; /* CPU core frequency in Hz */
435 + u32 sys_freq; /* System frequency in Hz */
436 + u32 cnt_freq; /* Calculated C0_COUNT frequency */
437 +
438 + u8 wlan0_mac[6];
439 + u8 enet0_mac[6];
440 + u8 enet1_mac[6];
441 +
442 + u16 pci_id; /* Pseudo PCIID for common code */
443 + u16 mem_cap; /* cap bank1 in MB */
444 +
445 + /* version 3 */
446 + u8 wlan1_mac[6]; /* (ar5212) */
447 +};
448 +
449 +#define BOARD_CONFIG_BUFSZ 0x1000
450 +
451 +/*
452 + * Platform device information for the Wireless MAC
453 + */
454 +struct ar231x_board_config {
455 + u16 devid;
456 +
457 + /* board config data */
458 + struct ar231x_boarddata *config;
459 +
460 + /* radio calibration data */
461 + const char *radio;
462 +};
463 +
464 +/*
465 + * Platform device information for the Ethernet MAC
466 + */
467 +struct ar231x_eth {
468 + void (*reset_set)(u32);
469 + void (*reset_clear)(u32);
470 + u32 reset_mac;
471 + u32 reset_phy;
472 + struct ar231x_board_config *config;
473 + char *macaddr;
474 +};
475 +
476 +#endif /* __ASM_MACH_AR231X_PLATFORM_H */
477 --- /dev/null
478 +++ b/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h
479 @@ -0,0 +1,84 @@
480 +/*
481 + * Atheros AR231x/AR531x SoC specific CPU feature overrides
482 + *
483 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
484 + *
485 + * This file was derived from: include/asm-mips/cpu-features.h
486 + * Copyright (C) 2003, 2004 Ralf Baechle
487 + * Copyright (C) 2004 Maciej W. Rozycki
488 + *
489 + * This program is free software; you can redistribute it and/or modify it
490 + * under the terms of the GNU General Public License version 2 as published
491 + * by the Free Software Foundation.
492 + *
493 + */
494 +#ifndef __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H
495 +#define __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H
496 +
497 +/*
498 + * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core.
499 + */
500 +#define cpu_has_tlb 1
501 +#define cpu_has_4kex 1
502 +#define cpu_has_3k_cache 0
503 +#define cpu_has_4k_cache 1
504 +#define cpu_has_tx39_cache 0
505 +#define cpu_has_sb1_cache 0
506 +#define cpu_has_fpu 0
507 +#define cpu_has_32fpr 0
508 +#define cpu_has_counter 1
509 +/* #define cpu_has_watch ? */
510 +/* #define cpu_has_divec ? */
511 +/* #define cpu_has_vce ? */
512 +/* #define cpu_has_cache_cdex_p ? */
513 +/* #define cpu_has_cache_cdex_s ? */
514 +/* #define cpu_has_prefetch ? */
515 +/* #define cpu_has_mcheck ? */
516 +#define cpu_has_ejtag 1
517 +
518 +#if !defined(CONFIG_ATHEROS_AR5312)
519 +# define cpu_has_llsc 1
520 +#else
521 +/*
522 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
523 + * ll/sc instructions.
524 + */
525 +# define cpu_has_llsc 0
526 +#endif
527 +
528 +#define cpu_has_mips16 0
529 +#define cpu_has_mdmx 0
530 +#define cpu_has_mips3d 0
531 +#define cpu_has_smartmips 0
532 +
533 +/* #define cpu_has_vtag_icache ? */
534 +/* #define cpu_has_dc_aliases ? */
535 +/* #define cpu_has_ic_fills_f_dc ? */
536 +/* #define cpu_has_pindexed_dcache ? */
537 +
538 +/* #define cpu_icache_snoops_remote_store ? */
539 +
540 +#define cpu_has_mips32r1 1
541 +
542 +#if !defined(CONFIG_ATHEROS_AR5312)
543 +# define cpu_has_mips32r2 1
544 +#endif
545 +
546 +#define cpu_has_mips64r1 0
547 +#define cpu_has_mips64r2 0
548 +
549 +#define cpu_has_dsp 0
550 +#define cpu_has_mipsmt 0
551 +
552 +/* #define cpu_has_nofpuex ? */
553 +#define cpu_has_64bits 0
554 +#define cpu_has_64bit_zero_reg 0
555 +#define cpu_has_64bit_gp_regs 0
556 +#define cpu_has_64bit_addresses 0
557 +
558 +/* #define cpu_has_inclusive_pcaches ? */
559 +
560 +/* #define cpu_dcache_line_size() ? */
561 +/* #define cpu_icache_line_size() ? */
562 +
563 +#endif /* __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H */
564 --- /dev/null
565 +++ b/arch/mips/include/asm/mach-ar231x/dma-coherence.h
566 @@ -0,0 +1,78 @@
567 +/*
568 + * This file is subject to the terms and conditions of the GNU General Public
569 + * License. See the file "COPYING" in the main directory of this archive
570 + * for more details.
571 + *
572 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
573 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
574 + *
575 + */
576 +#ifndef __ASM_MACH_AR231X_DMA_COHERENCE_H
577 +#define __ASM_MACH_AR231X_DMA_COHERENCE_H
578 +
579 +#define PCI_DMA_OFFSET 0x20000000
580 +
581 +#include <linux/device.h>
582 +
583 +static inline dma_addr_t ar231x_dev_offset(struct device *dev)
584 +{
585 +#ifdef CONFIG_PCI
586 + extern struct bus_type pci_bus_type;
587 +
588 + if (dev && dev->bus == &pci_bus_type)
589 + return PCI_DMA_OFFSET;
590 + else
591 +#endif
592 + return 0;
593 +}
594 +
595 +static inline dma_addr_t
596 +plat_map_dma_mem(struct device *dev, void *addr, size_t size)
597 +{
598 + return virt_to_phys(addr) + ar231x_dev_offset(dev);
599 +}
600 +
601 +static inline dma_addr_t
602 +plat_map_dma_mem_page(struct device *dev, struct page *page)
603 +{
604 + return page_to_phys(page) + ar231x_dev_offset(dev);
605 +}
606 +
607 +static inline unsigned long
608 +plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
609 +{
610 + return dma_addr - ar231x_dev_offset(dev);
611 +}
612 +
613 +static inline void
614 +plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
615 + enum dma_data_direction direction)
616 +{
617 +}
618 +
619 +static inline int plat_dma_supported(struct device *dev, u64 mask)
620 +{
621 + return 1;
622 +}
623 +
624 +static inline void plat_extra_sync_for_device(struct device *dev)
625 +{
626 +}
627 +
628 +static inline int plat_dma_mapping_error(struct device *dev,
629 + dma_addr_t dma_addr)
630 +{
631 + return 0;
632 +}
633 +
634 +static inline int plat_device_is_coherent(struct device *dev)
635 +{
636 +#ifdef CONFIG_DMA_COHERENT
637 + return 1;
638 +#endif
639 +#ifdef CONFIG_DMA_NONCOHERENT
640 + return 0;
641 +#endif
642 +}
643 +
644 +#endif /* __ASM_MACH_AR231X_DMA_COHERENCE_H */
645 --- /dev/null
646 +++ b/arch/mips/include/asm/mach-ar231x/gpio.h
647 @@ -0,0 +1,30 @@
648 +#ifndef __ASM_MACH_AR231X_GPIO_H
649 +#define __ASM_MACH_AR231X_GPIO_H
650 +
651 +#include <ar231x.h>
652 +
653 +#define gpio_get_value __gpio_get_value
654 +#define gpio_set_value __gpio_set_value
655 +#define gpio_cansleep __gpio_cansleep
656 +
657 +/*
658 + * Wrappers for the generic GPIO layer
659 + */
660 +
661 +/* not sure if these are used? */
662 +
663 +/* Returns IRQ to attach for gpio. Unchecked function */
664 +static inline int gpio_to_irq(unsigned gpio)
665 +{
666 + return AR231X_GPIO_IRQ(gpio);
667 +}
668 +
669 +/* Returns gpio for IRQ attached. Unchecked function */
670 +static inline int irq_to_gpio(unsigned irq)
671 +{
672 + return irq - AR231X_GPIO_IRQ(0);
673 +}
674 +
675 +#include <asm-generic/gpio.h> /* cansleep wrappers */
676 +
677 +#endif /* __ASM_MACH_AR231X_GPIO_H */
678 --- /dev/null
679 +++ b/arch/mips/include/asm/mach-ar231x/reset.h
680 @@ -0,0 +1,6 @@
681 +#ifndef __ASM_MACH_AR231X_RESET_H
682 +#define __ASM_MACH_AR231X_RESET_H
683 +
684 +void ar231x_disable_reset_button(void);
685 +
686 +#endif /* __ASM_MACH_AR231X_RESET_H */
687 --- /dev/null
688 +++ b/arch/mips/include/asm/mach-ar231x/war.h
689 @@ -0,0 +1,25 @@
690 +/*
691 + * This file is subject to the terms and conditions of the GNU General Public
692 + * License. See the file "COPYING" in the main directory of this archive
693 + * for more details.
694 + *
695 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
696 + */
697 +#ifndef __ASM_MACH_AR231X_WAR_H
698 +#define __ASM_MACH_AR231X_WAR_H
699 +
700 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
701 +#define R4600_V1_HIT_CACHEOP_WAR 0
702 +#define R4600_V2_HIT_CACHEOP_WAR 0
703 +#define R5432_CP0_INTERRUPT_WAR 0
704 +#define BCM1250_M3_WAR 0
705 +#define SIBYTE_1956_WAR 0
706 +#define MIPS4K_ICACHE_REFILL_WAR 0
707 +#define MIPS_CACHE_SYNC_WAR 0
708 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
709 +#define RM9000_CDEX_SMP_WAR 0
710 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
711 +#define R10000_LLSC_WAR 0
712 +#define MIPS34K_MISSED_ITLB_WAR 0
713 +
714 +#endif /* __ASM_MACH_AR231X_WAR_H */
715 --- /dev/null
716 +++ b/arch/mips/include/asm/mach-ar231x/ar2315_regs.h
717 @@ -0,0 +1,617 @@
718 +/*
719 + * Register definitions for AR2315+
720 + *
721 + * This file is subject to the terms and conditions of the GNU General Public
722 + * License. See the file "COPYING" in the main directory of this archive
723 + * for more details.
724 + *
725 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
726 + * Copyright (C) 2006 FON Technology, SL.
727 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
728 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
729 + */
730 +
731 +#ifndef __ASM_MACH_AR231X_AR2315_REGS_H
732 +#define __ASM_MACH_AR231X_AR2315_REGS_H
733 +
734 +/*
735 + * IRQs
736 + */
737 +#define AR2315_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
738 +#define AR2315_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
739 +#define AR2315_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
740 +#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
741 +#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
742 +
743 +
744 +/*
745 + * Miscellaneous interrupts, which share IP2.
746 + */
747 +#define AR2315_MISC_IRQ_NONE (AR231X_MISC_IRQ_BASE+0)
748 +#define AR2315_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+1)
749 +#define AR2315_MISC_IRQ_I2C_RSVD (AR231X_MISC_IRQ_BASE+2)
750 +#define AR2315_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+3)
751 +#define AR2315_MISC_IRQ_AHB (AR231X_MISC_IRQ_BASE+4)
752 +#define AR2315_MISC_IRQ_APB (AR231X_MISC_IRQ_BASE+5)
753 +#define AR2315_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+6)
754 +#define AR2315_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+7)
755 +#define AR2315_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+8)
756 +#define AR2315_MISC_IRQ_IR_RSVD (AR231X_MISC_IRQ_BASE+9)
757 +#define AR2315_MISC_IRQ_COUNT 10
758 +
759 +
760 +/*
761 + * Address map
762 + */
763 +#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
764 +#define AR2315_WLAN0 0x10000000 /* Wireless MMR */
765 +#define AR2315_PCI 0x10100000 /* PCI MMR */
766 +#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */
767 +#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */
768 +#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */
769 +#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */
770 +#define AR2315_UART0 0x11100000 /* UART MMR */
771 +#define AR2315_SPI_MMR 0x11300000 /* SPI FLASH MMR */
772 +#define AR2315_PCIEXT 0x80000000 /* pci external */
773 +
774 +/* MII registers offset inside Ethernet MMR region */
775 +#define AR2315_ENET0_MII (AR2315_ENET0 + 0x14)
776 +
777 +/*
778 + * Reset Register
779 + */
780 +#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
781 +
782 +#define AR2315_RESET_COLD_AHB 0x00000001
783 +#define AR2315_RESET_COLD_APB 0x00000002
784 +#define AR2315_RESET_COLD_CPU 0x00000004
785 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
786 +#define AR2315_RESET_SYSTEM \
787 + (RESET_COLD_CPU |\
788 + RESET_COLD_APB |\
789 + RESET_COLD_AHB) /* full system */
790 +#define AR2317_RESET_SYSTEM 0x00000010
791 +
792 +
793 +#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
794 +
795 +/* warm reset WLAN0 MAC */
796 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001
797 +/* warm reset WLAN0 BaseBand */
798 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002
799 +/* warm reset MPEG-TS */
800 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004
801 +/* warm reset PCI ahb/dma */
802 +#define AR2315_RESET_PCIDMA 0x00000008
803 +/* warm reset memory controller */
804 +#define AR2315_RESET_MEMCTL 0x00000010
805 +/* warm reset local bus */
806 +#define AR2315_RESET_LOCAL 0x00000020
807 +/* warm reset I2C bus */
808 +#define AR2315_RESET_I2C_RSVD 0x00000040
809 +/* warm reset SPI interface */
810 +#define AR2315_RESET_SPI 0x00000080
811 +/* warm reset UART0 */
812 +#define AR2315_RESET_UART0 0x00000100
813 +/* warm reset IR interface */
814 +#define AR2315_RESET_IR_RSVD 0x00000200
815 +/* cold reset ENET0 phy */
816 +#define AR2315_RESET_EPHY0 0x00000400
817 +/* cold reset ENET0 mac */
818 +#define AR2315_RESET_ENET0 0x00000800
819 +
820 +/*
821 + * AHB master arbitration control
822 + */
823 +#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
824 +
825 +/* CPU, default */
826 +#define AR2315_ARB_CPU 0x00000001
827 +/* WLAN */
828 +#define AR2315_ARB_WLAN 0x00000002
829 +/* MPEG-TS */
830 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004
831 +/* LOCAL */
832 +#define AR2315_ARB_LOCAL 0x00000008
833 +/* PCI */
834 +#define AR2315_ARB_PCI 0x00000010
835 +/* Ethernet */
836 +#define AR2315_ARB_ETHERNET 0x00000020
837 +/* retry policy, debug only */
838 +#define AR2315_ARB_RETRY 0x00000100
839 +
840 +/*
841 + * Config Register
842 + */
843 +#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
844 +
845 +/* EC - AHB bridge endianess */
846 +#define AR2315_CONFIG_AHB 0x00000001
847 +/* WLAN byteswap */
848 +#define AR2315_CONFIG_WLAN 0x00000002
849 +/* MPEG-TS byteswap */
850 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004
851 +/* PCI byteswap */
852 +#define AR2315_CONFIG_PCI 0x00000008
853 +/* Memory controller endianess */
854 +#define AR2315_CONFIG_MEMCTL 0x00000010
855 +/* Local bus byteswap */
856 +#define AR2315_CONFIG_LOCAL 0x00000020
857 +/* Ethernet byteswap */
858 +#define AR2315_CONFIG_ETHERNET 0x00000040
859 +
860 +/* CPU write buffer merge */
861 +#define AR2315_CONFIG_MERGE 0x00000200
862 +/* CPU big endian */
863 +#define AR2315_CONFIG_CPU 0x00000400
864 +#define AR2315_CONFIG_PCIAHB 0x00000800
865 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
866 +/* SPI byteswap */
867 +#define AR2315_CONFIG_SPI 0x00008000
868 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
869 +#define AR2315_CONFIG_CPU_PCI 0x00020000
870 +#define AR2315_CONFIG_CPU_MMR 0x00040000
871 +#define AR2315_CONFIG_BIG 0x00000400
872 +
873 +
874 +/*
875 + * NMI control
876 + */
877 +#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
878 +
879 +#define AR2315_NMI_EN 1
880 +
881 +/*
882 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0).
883 + */
884 +#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
885 +
886 +#define AR2315_REV_MAJ 0x00f0
887 +#define AR2315_REV_MAJ_S 4
888 +#define AR2315_REV_MIN 0x000f
889 +#define AR2315_REV_MIN_S 0
890 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
891 +
892 +/*
893 + * Interface Enable
894 + */
895 +#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
896 +
897 +#define AR2315_IF_MASK 0x00000007
898 +#define AR2315_IF_DISABLED 0
899 +#define AR2315_IF_PCI 1
900 +#define AR2315_IF_TS_LOCAL 2
901 +/* only for emulation with separate pins */
902 +#define AR2315_IF_ALL 3
903 +#define AR2315_IF_LOCAL_HOST 0x00000008
904 +#define AR2315_IF_PCI_HOST 0x00000010
905 +#define AR2315_IF_PCI_INTR 0x00000020
906 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
907 +#define AR2315_IF_PCI_CLK_INPUT 0
908 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
909 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
910 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
911 +#define AR2315_IF_PCI_CLK_SHIFT 16
912 +
913 +/*
914 + * APB Interrupt control
915 + */
916 +
917 +#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
918 +#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
919 +#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
920 +
921 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
922 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
923 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
924 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
925 +#define AR2315_ISR_APB 0x0010 /* APB error */
926 +#define AR2315_ISR_TIMER 0x0020 /* timer */
927 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
928 +#define AR2315_ISR_WD 0x0080 /* watchdog */
929 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
930 +
931 +#define AR2315_GISR_MISC 0x0001
932 +#define AR2315_GISR_WLAN0 0x0002
933 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
934 +#define AR2315_GISR_LOCALPCI 0x0008
935 +#define AR2315_GISR_WMACPOLL 0x0010
936 +#define AR2315_GISR_TIMER 0x0020
937 +#define AR2315_GISR_ETHERNET 0x0040
938 +
939 +/*
940 + * Interrupt routing from IO to the processor IP bits
941 + * Define our inter mask and level
942 + */
943 +#define AR2315_INTR_MISCIO SR_IBIT3
944 +#define AR2315_INTR_WLAN0 SR_IBIT4
945 +#define AR2315_INTR_ENET0 SR_IBIT5
946 +#define AR2315_INTR_LOCALPCI SR_IBIT6
947 +#define AR2315_INTR_WMACPOLL SR_IBIT7
948 +#define AR2315_INTR_COMPARE SR_IBIT8
949 +
950 +/*
951 + * Timers
952 + */
953 +#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
954 +#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
955 +#define AR2315_WD (AR2315_DSLBASE + 0x0038)
956 +#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
957 +
958 +#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
959 +#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
960 +#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
961 +
962 +/*
963 + * CPU Performance Counters
964 + */
965 +#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
966 +#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
967 +
968 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
969 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
970 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
971 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
972 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
973 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
974 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
975 +
976 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
977 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
978 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
979 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
980 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
981 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
982 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
983 +
984 +/*
985 + * AHB Error Reporting.
986 + */
987 +#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
988 +#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
989 +#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
990 +#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
991 +#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
992 +
993 +#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
994 + /* write 1 to clear all bits in ERR0 */
995 +#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
996 +#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
997 +
998 +#define AR2315_PROCERR_HMAST 0x0000000f
999 +#define AR2315_PROCERR_HMAST_DFLT 0
1000 +#define AR2315_PROCERR_HMAST_WMAC 1
1001 +#define AR2315_PROCERR_HMAST_ENET 2
1002 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
1003 +#define AR2315_PROCERR_HMAST_LOCAL 4
1004 +#define AR2315_PROCERR_HMAST_CPU 5
1005 +#define AR2315_PROCERR_HMAST_PCITGT 6
1006 +
1007 +#define AR2315_PROCERR_HMAST_S 0
1008 +#define AR2315_PROCERR_HWRITE 0x00000010
1009 +#define AR2315_PROCERR_HSIZE 0x00000060
1010 +#define AR2315_PROCERR_HSIZE_S 5
1011 +#define AR2315_PROCERR_HTRANS 0x00000180
1012 +#define AR2315_PROCERR_HTRANS_S 7
1013 +#define AR2315_PROCERR_HBURST 0x00000e00
1014 +#define AR2315_PROCERR_HBURST_S 9
1015 +
1016 +/*
1017 + * Clock Control
1018 + */
1019 +#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
1020 +#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
1021 +#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
1022 +#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
1023 +#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
1024 +#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
1025 +#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
1026 +
1027 +/* PLLc Control fields */
1028 +#define PLLC_REF_DIV_M 0x00000003
1029 +#define PLLC_REF_DIV_S 0
1030 +#define PLLC_FDBACK_DIV_M 0x0000007C
1031 +#define PLLC_FDBACK_DIV_S 2
1032 +#define PLLC_ADD_FDBACK_DIV_M 0x00000080
1033 +#define PLLC_ADD_FDBACK_DIV_S 7
1034 +#define PLLC_CLKC_DIV_M 0x0001c000
1035 +#define PLLC_CLKC_DIV_S 14
1036 +#define PLLC_CLKM_DIV_M 0x00700000
1037 +#define PLLC_CLKM_DIV_S 20
1038 +
1039 +/* CPU CLK Control fields */
1040 +#define CPUCLK_CLK_SEL_M 0x00000003
1041 +#define CPUCLK_CLK_SEL_S 0
1042 +#define CPUCLK_CLK_DIV_M 0x0000000c
1043 +#define CPUCLK_CLK_DIV_S 2
1044 +
1045 +/* AMBA CLK Control fields */
1046 +#define AMBACLK_CLK_SEL_M 0x00000003
1047 +#define AMBACLK_CLK_SEL_S 0
1048 +#define AMBACLK_CLK_DIV_M 0x0000000c
1049 +#define AMBACLK_CLK_DIV_S 2
1050 +
1051 +/*
1052 + * GPIO
1053 + */
1054 +#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088)
1055 +#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090)
1056 +#define AR2315_GPIO_DIR (AR2315_DSLBASE + 0x0098)
1057 +#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0)
1058 +
1059 +#define AR2315_GPIO_DIR_M(x) (1 << (x)) /* mask for i/o */
1060 +#define AR2315_GPIO_DIR_O(x) (1 << (x)) /* output */
1061 +#define AR2315_GPIO_DIR_I(x) (0) /* input */
1062 +
1063 +#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */
1064 +#define AR2315_GPIO_INT_M (0x3F) /* mask for int */
1065 +#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */
1066 +#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */
1067 +
1068 +#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for
1069 + * AR2315_GPIO_INT_* macros */
1070 +#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */
1071 +#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */
1072 +#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */
1073 +#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */
1074 +
1075 +#define AR2315_RESET_GPIO 5
1076 +#define AR2315_NUM_GPIO 22
1077 +
1078 +/*
1079 + * PCI Clock Control
1080 + */
1081 +#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
1082 +
1083 +#define AR2315_PCICLK_INPUT_M 0x3
1084 +#define AR2315_PCICLK_INPUT_S 0
1085 +
1086 +#define AR2315_PCICLK_PLLC_CLKM 0
1087 +#define AR2315_PCICLK_PLLC_CLKM1 1
1088 +#define AR2315_PCICLK_PLLC_CLKC 2
1089 +#define AR2315_PCICLK_REF_CLK 3
1090 +
1091 +#define AR2315_PCICLK_DIV_M 0xc
1092 +#define AR2315_PCICLK_DIV_S 2
1093 +
1094 +#define AR2315_PCICLK_IN_FREQ 0
1095 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
1096 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
1097 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
1098 +
1099 +/*
1100 + * Observation Control Register
1101 + */
1102 +#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
1103 +#define OCR_GPIO0_IRIN 0x0040
1104 +#define OCR_GPIO1_IROUT 0x0080
1105 +#define OCR_GPIO3_RXCLR 0x0200
1106 +
1107 +/*
1108 + * General Clock Control
1109 + */
1110 +
1111 +#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
1112 +#define MISCCLK_PLLBYPASS_EN 0x00000001
1113 +#define MISCCLK_PROCREFCLK 0x00000002
1114 +
1115 +/*
1116 + * SDRAM Controller
1117 + * - No read or write buffers are included.
1118 + */
1119 +#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
1120 +#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
1121 +#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
1122 +
1123 +#define SDRAM_DATA_WIDTH_M 0x00006000
1124 +#define SDRAM_DATA_WIDTH_S 13
1125 +
1126 +#define SDRAM_COL_WIDTH_M 0x00001E00
1127 +#define SDRAM_COL_WIDTH_S 9
1128 +
1129 +#define SDRAM_ROW_WIDTH_M 0x000001E0
1130 +#define SDRAM_ROW_WIDTH_S 5
1131 +
1132 +#define SDRAM_BANKADDR_BITS_M 0x00000018
1133 +#define SDRAM_BANKADDR_BITS_S 3
1134 +
1135 +/*
1136 + * PCI Bus Interface Registers
1137 + */
1138 +#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
1139 +#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1140 +
1141 +#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
1142 +#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
1143 +#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */
1144 +#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
1145 +#define AR2315_PCIMISC_RST_MODE 0x00000030
1146 +#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
1147 +#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
1148 +#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
1149 +#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
1150 +#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
1151 +#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
1152 +#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
1153 +#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
1154 + * disable */
1155 +
1156 +#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
1157 +
1158 +#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014)
1159 +
1160 +#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100)
1161 +#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
1162 +#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
1163 +#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
1164 +#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
1165 +
1166 +#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104)
1167 +#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
1168 +#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
1169 +#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
1170 +#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
1171 +
1172 +#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200)
1173 +
1174 +#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400)
1175 +#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
1176 +
1177 +#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404)
1178 +#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
1179 +
1180 +#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408)
1181 +
1182 +#define AR2315_PCI_INT_STATUS (AR2315_PCI + 0x0500) /* write one to clr */
1183 +#define AR2315_PCI_TXINT 0x00000001 /* Desc In Completed */
1184 +#define AR2315_PCI_TXOK 0x00000002 /* Desc In OK */
1185 +#define AR2315_PCI_TXERR 0x00000004 /* Desc In ERR */
1186 +#define AR2315_PCI_TXEOL 0x00000008 /* Desc In End-of-List */
1187 +#define AR2315_PCI_RXINT 0x00000010 /* Desc Out Completed */
1188 +#define AR2315_PCI_RXOK 0x00000020 /* Desc Out OK */
1189 +#define AR2315_PCI_RXERR 0x00000040 /* Desc Out ERR */
1190 +#define AR2315_PCI_RXEOL 0x00000080 /* Desc Out EOL */
1191 +#define AR2315_PCI_TXOOD 0x00000200 /* Desc In Out-of-Desc */
1192 +#define AR2315_PCI_MASK 0x0000FFFF /* Desc Mask */
1193 +#define AR2315_PCI_EXT_INT 0x02000000
1194 +#define AR2315_PCI_ABORT_INT 0x04000000
1195 +
1196 +#define AR2315_PCI_INT_MASK (AR2315_PCI + 0x0504) /* same as INT_STATUS */
1197 +
1198 +#define AR2315_PCI_INTEN_REG (AR2315_PCI + 0x0508)
1199 +#define AR2315_PCI_INT_DISABLE 0x00 /* disable pci interrupts */
1200 +#define AR2315_PCI_INT_ENABLE 0x01 /* enable pci interrupts */
1201 +
1202 +#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800)
1203 +#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804)
1204 +#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810)
1205 +#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900)
1206 +#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
1207 +#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
1208 +
1209 +
1210 +/*
1211 + * Local Bus Interface Registers
1212 + */
1213 +#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
1214 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1215 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1216 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1217 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1218 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1219 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1220 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1221 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1222 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1223 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1224 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1225 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1226 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1227 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1228 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1229 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1230 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1231 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1232 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1233 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1234 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1235 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1236 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1237 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1238 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1239 +
1240 +#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
1241 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1242 +
1243 +#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
1244 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1245 +
1246 +#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
1247 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1248 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1249 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1250 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1251 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1252 +#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1253 +#define AR2315_LBM_TIMEOUT_SHFT 7
1254 +#define AR2315_LBM_PORTMUX 0x07000000
1255 +
1256 +
1257 +#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
1258 +
1259 +#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
1260 +#define AR2315_LB_TXEN_0 0x01
1261 +#define AR2315_LB_TXEN_1 0x02
1262 +#define AR2315_LB_TXEN_2 0x04
1263 +#define AR2315_LB_TXEN_3 0x08
1264 +
1265 +#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
1266 +#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
1267 +
1268 +#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
1269 +#define AR2315_LB_RXEN 0x01
1270 +
1271 +#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
1272 +#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
1273 +
1274 +#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
1275 +#define AR2315_INT_TX_DESC 0x0001
1276 +#define AR2315_INT_TX_OK 0x0002
1277 +#define AR2315_INT_TX_ERR 0x0004
1278 +#define AR2315_INT_TX_EOF 0x0008
1279 +#define AR2315_INT_RX_DESC 0x0010
1280 +#define AR2315_INT_RX_OK 0x0020
1281 +#define AR2315_INT_RX_ERR 0x0040
1282 +#define AR2315_INT_RX_EOF 0x0080
1283 +#define AR2315_INT_TX_TRUNC 0x0100
1284 +#define AR2315_INT_TX_STARVE 0x0200
1285 +#define AR2315_INT_LB_TIMEOUT 0x0400
1286 +#define AR2315_INT_LB_ERR 0x0800
1287 +#define AR2315_INT_MBOX_WR 0x1000
1288 +#define AR2315_INT_MBOX_RD 0x2000
1289 +
1290 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1291 +#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
1292 +
1293 +#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
1294 +#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
1295 +
1296 +/*
1297 + * IR Interface Registers
1298 + */
1299 +#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
1300 +
1301 +#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
1302 +
1303 +#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
1304 +#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
1305 +#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
1306 +#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor */
1307 +#define AR2315_IRCTL_SAMPLECLK_SHFT 1
1308 +#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk div */
1309 +#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
1310 +
1311 +#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
1312 +#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
1313 +#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
1314 +
1315 +#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
1316 +#define AR2315_IRCFG_INVIN 0x00000001 /* invert in polarity */
1317 +#define AR2315_IRCFG_INVOUT 0x00000002 /* invert out polarity */
1318 +#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
1319 +#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0
1320 +#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100
1321 +#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00
1322 +#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000
1323 +#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000
1324 +#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000
1325 +
1326 +#define HOST_PCI_DEV_ID 3
1327 +#define HOST_PCI_MBAR0 0x10000000
1328 +#define HOST_PCI_MBAR1 0x20000000
1329 +#define HOST_PCI_MBAR2 0x30000000
1330 +
1331 +#define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1
1332 +#define PCI_DEVICE_MEM_SPACE 0x800000
1333 +
1334 +#endif /* __ASM_MACH_AR231X_AR2315_REGS_H */
1335 --- /dev/null
1336 +++ b/arch/mips/include/asm/mach-ar231x/ar5312_regs.h
1337 @@ -0,0 +1,253 @@
1338 +/*
1339 + * This file is subject to the terms and conditions of the GNU General Public
1340 + * License. See the file "COPYING" in the main directory of this archive
1341 + * for more details.
1342 + *
1343 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1344 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1345 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1346 + */
1347 +
1348 +#ifndef __ASM_MACH_AR231X_AR5312_REGS_H
1349 +#define __ASM_MACH_AR231X_AR5312_REGS_H
1350 +
1351 +#include <asm/addrspace.h>
1352 +
1353 +/*
1354 + * IRQs
1355 + */
1356 +
1357 +#define AR5312_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
1358 +#define AR5312_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
1359 +#define AR5312_IRQ_ENET1_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
1360 +#define AR5312_IRQ_WLAN1_INTRS (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
1361 +#define AR5312_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
1362 +
1363 +
1364 +/*
1365 + * Miscellaneous interrupts, which share IP6.
1366 + */
1367 +#define AR5312_MISC_IRQ_NONE (AR231X_MISC_IRQ_BASE+0)
1368 +#define AR5312_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+1)
1369 +#define AR5312_MISC_IRQ_AHB_PROC (AR231X_MISC_IRQ_BASE+2)
1370 +#define AR5312_MISC_IRQ_AHB_DMA (AR231X_MISC_IRQ_BASE+3)
1371 +#define AR5312_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+4)
1372 +#define AR5312_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+5)
1373 +#define AR5312_MISC_IRQ_UART0_DMA (AR231X_MISC_IRQ_BASE+6)
1374 +#define AR5312_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+7)
1375 +#define AR5312_MISC_IRQ_LOCAL (AR231X_MISC_IRQ_BASE+8)
1376 +#define AR5312_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+9)
1377 +#define AR5312_MISC_IRQ_COUNT 10
1378 +
1379 +
1380 +/* Address Map */
1381 +#define AR5312_WLAN0 0x18000000
1382 +#define AR5312_WLAN1 0x18500000
1383 +#define AR5312_ENET0 0x18100000
1384 +#define AR5312_ENET1 0x18200000
1385 +#define AR5312_SDRAMCTL 0x18300000
1386 +#define AR5312_FLASHCTL 0x18400000
1387 +#define AR5312_APBBASE 0x1c000000
1388 +#define AR5312_UART0 0x1c000000 /* UART MMR */
1389 +#define AR5312_FLASH 0x1e000000
1390 +
1391 +/*
1392 + * AR5312_NUM_ENET_MAC defines the number of ethernet MACs that
1393 + * should be considered available. The AR5312 supports 2 enet MACS,
1394 + * even though many reference boards only actually use 1 of them
1395 + * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
1396 + * The AR2312 supports 1 enet MAC.
1397 + */
1398 +#define AR5312_NUM_ENET_MAC 2
1399 +
1400 +/*
1401 + * Need these defines to determine true number of ethernet MACs
1402 + */
1403 +#define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1404 +#define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1405 +#define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1406 +
1407 +/* MII registers offset inside Ethernet MMR region */
1408 +#define AR5312_ENET0_MII (AR5312_ENET0 + 0x14)
1409 +#define AR5312_ENET1_MII (AR5312_ENET1 + 0x14)
1410 +
1411 +/*
1412 + * AR5312_NUM_WMAC defines the number of Wireless MACs that\
1413 + * should be considered available.
1414 + */
1415 +#define AR5312_NUM_WMAC 2
1416 +
1417 +/* Reset/Timer Block Address Map */
1418 +#define AR5312_RESETTMR (AR5312_APBBASE + 0x3000)
1419 +#define AR5312_TIMER (AR5312_RESETTMR + 0x0000) /* countdown timer */
1420 +#define AR5312_WD_CTRL (AR5312_RESETTMR + 0x0008) /* watchdog cntrl */
1421 +#define AR5312_WD_TIMER (AR5312_RESETTMR + 0x000c) /* watchdog timer */
1422 +#define AR5312_ISR (AR5312_RESETTMR + 0x0010) /* Intr Status Reg */
1423 +#define AR5312_IMR (AR5312_RESETTMR + 0x0014) /* Intr Mask Reg */
1424 +#define AR5312_RESET (AR5312_RESETTMR + 0x0020)
1425 +#define AR5312_CLOCKCTL1 (AR5312_RESETTMR + 0x0064)
1426 +#define AR5312_SCRATCH (AR5312_RESETTMR + 0x006c)
1427 +#define AR5312_PROCADDR (AR5312_RESETTMR + 0x0070)
1428 +#define AR5312_PROC1 (AR5312_RESETTMR + 0x0074)
1429 +#define AR5312_DMAADDR (AR5312_RESETTMR + 0x0078)
1430 +#define AR5312_DMA1 (AR5312_RESETTMR + 0x007c)
1431 +#define AR5312_ENABLE (AR5312_RESETTMR + 0x0080) /* interface enb */
1432 +#define AR5312_REV (AR5312_RESETTMR + 0x0090) /* revision */
1433 +
1434 +/* AR5312_WD_CTRL register bit field definitions */
1435 +#define AR5312_WD_CTRL_IGNORE_EXPIRATION 0x0000
1436 +#define AR5312_WD_CTRL_NMI 0x0001
1437 +#define AR5312_WD_CTRL_RESET 0x0002
1438 +
1439 +/* AR5312_ISR register bit field definitions */
1440 +#define AR5312_ISR_NONE 0x0000
1441 +#define AR5312_ISR_TIMER 0x0001
1442 +#define AR5312_ISR_AHBPROC 0x0002
1443 +#define AR5312_ISR_AHBDMA 0x0004
1444 +#define AR5312_ISR_GPIO 0x0008
1445 +#define AR5312_ISR_UART0 0x0010
1446 +#define AR5312_ISR_UART0DMA 0x0020
1447 +#define AR5312_ISR_WD 0x0040
1448 +#define AR5312_ISR_LOCAL 0x0080
1449 +
1450 +/* AR5312_RESET register bit field definitions */
1451 +#define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */
1452 +#define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */
1453 +#define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1454 +#define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1455 +#define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1456 +#define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1457 +#define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1458 +#define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1459 +#define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1460 +#define AR5312_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1461 +#define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1462 +#define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1463 +#define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1464 +#define AR5312_RESET_NMI 0x00010000 /* send an NMI to the processor */
1465 +#define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1466 +#define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1467 +#define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1468 +#define AR5312_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1469 +
1470 +#define AR5312_RESET_WMAC0_BITS \
1471 + (AR5312_RESET_WLAN0 |\
1472 + AR5312_RESET_WARM_WLAN0_MAC |\
1473 + AR5312_RESET_WARM_WLAN0_BB)
1474 +
1475 +#define AR5312_RESET_WMAC1_BITS \
1476 + (AR5312_RESET_WLAN1 |\
1477 + AR5312_RESET_WARM_WLAN1_MAC |\
1478 + AR5312_RESET_WARM_WLAN1_BB)
1479 +
1480 +/* AR5312_CLOCKCTL1 register bit field definitions */
1481 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1482 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1483 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1484 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1485 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1486 +
1487 +/* Valid for AR5312 and AR2312 */
1488 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1489 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1490 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1491 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1492 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1493 +
1494 +/* Valid for AR2313 */
1495 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1496 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1497 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1498 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1499 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1500 +
1501 +
1502 +/* AR5312_ENABLE register bit field definitions */
1503 +#define AR5312_ENABLE_WLAN0 0x0001
1504 +#define AR5312_ENABLE_ENET0 0x0002
1505 +#define AR5312_ENABLE_ENET1 0x0004
1506 +#define AR5312_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1507 +#define AR5312_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1508 +#define AR5312_ENABLE_WLAN1 \
1509 + (AR5312_ENABLE_UART_AND_WLAN1_PIO |\
1510 + AR5312_ENABLE_WLAN1_DMA)
1511 +
1512 +/* AR5312_REV register bit field definitions */
1513 +#define AR5312_REV_WMAC_MAJ 0xf000
1514 +#define AR5312_REV_WMAC_MAJ_S 12
1515 +#define AR5312_REV_WMAC_MIN 0x0f00
1516 +#define AR5312_REV_WMAC_MIN_S 8
1517 +#define AR5312_REV_MAJ 0x00f0
1518 +#define AR5312_REV_MAJ_S 4
1519 +#define AR5312_REV_MIN 0x000f
1520 +#define AR5312_REV_MIN_S 0
1521 +#define AR5312_REV_CHIP (AR5312_REV_MAJ|AR5312_REV_MIN)
1522 +
1523 +/* Major revision numbers, bits 7..4 of Revision ID register */
1524 +#define AR5312_REV_MAJ_AR5312 0x4
1525 +#define AR5312_REV_MAJ_AR2313 0x5
1526 +
1527 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1528 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1529 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1530 +
1531 +/* AR5312_FLASHCTL register bit field definitions */
1532 +#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1533 +#define FLASHCTL_IDCY_S 0
1534 +#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1535 +#define FLASHCTL_WST1_S 5
1536 +#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1537 +#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1538 +#define FLASHCTL_WST2_S 11
1539 +#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1540 +#define FLASHCTL_AC_S 16
1541 +#define FLASHCTL_AC_128K 0x00000000
1542 +#define FLASHCTL_AC_256K 0x00010000
1543 +#define FLASHCTL_AC_512K 0x00020000
1544 +#define FLASHCTL_AC_1M 0x00030000
1545 +#define FLASHCTL_AC_2M 0x00040000
1546 +#define FLASHCTL_AC_4M 0x00050000
1547 +#define FLASHCTL_AC_8M 0x00060000
1548 +#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1549 +#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1550 +#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1551 +#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1552 +#define FLASHCTL_WP 0x04000000 /* Write protect */
1553 +#define FLASHCTL_BM 0x08000000 /* Burst mode */
1554 +#define FLASHCTL_MW 0x30000000 /* Memory width */
1555 +#define FLASHCTL_MWx8 0x00000000 /* Memory width x8 */
1556 +#define FLASHCTL_MWx16 0x10000000 /* Memory width x16 */
1557 +#define FLASHCTL_MWx32 0x20000000 /* Memory width x32 (not supported) */
1558 +#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1559 +#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1560 +#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1561 +
1562 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1563 +#define AR5312_FLASHCTL0 (AR5312_FLASHCTL + 0x00)
1564 +#define AR5312_FLASHCTL1 (AR5312_FLASHCTL + 0x04)
1565 +#define AR5312_FLASHCTL2 (AR5312_FLASHCTL + 0x08)
1566 +
1567 +/* ARM SDRAM Controller -- just enough to determine memory size */
1568 +#define AR5312_MEM_CFG1 (AR5312_SDRAMCTL + 0x04)
1569 +#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1570 +#define MEM_CFG1_AC0_S 8
1571 +#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1572 +#define MEM_CFG1_AC1_S 12
1573 +
1574 +/* GPIO Address Map */
1575 +#define AR5312_GPIO (AR5312_APBBASE + 0x2000)
1576 +#define AR5312_GPIO_DO (AR5312_GPIO + 0x00) /* output register */
1577 +#define AR5312_GPIO_DI (AR5312_GPIO + 0x04) /* intput register */
1578 +#define AR5312_GPIO_CR (AR5312_GPIO + 0x08) /* control register */
1579 +
1580 +/* GPIO Control Register bit field definitions */
1581 +#define AR5312_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1582 +#define AR5312_GPIO_CR_O(x) (0 << (x)) /* mask for output */
1583 +#define AR5312_GPIO_CR_I(x) (1 << (x)) /* mask for input */
1584 +#define AR5312_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt*/
1585 +#define AR5312_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
1586 +#define AR5312_NUM_GPIO 8
1587 +
1588 +
1589 +#endif /* __ASM_MACH_AR231X_AR5312_REGS_H */
1590 +
1591 --- /dev/null
1592 +++ b/arch/mips/ar231x/ar5312.c
1593 @@ -0,0 +1,542 @@
1594 +/*
1595 + * This file is subject to the terms and conditions of the GNU General Public
1596 + * License. See the file "COPYING" in the main directory of this archive
1597 + * for more details.
1598 + *
1599 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1600 + * Copyright (C) 2006 FON Technology, SL.
1601 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1602 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1603 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1604 + */
1605 +
1606 +/*
1607 + * Platform devices for Atheros SoCs
1608 + */
1609 +
1610 +#include <generated/autoconf.h>
1611 +#include <linux/init.h>
1612 +#include <linux/module.h>
1613 +#include <linux/types.h>
1614 +#include <linux/string.h>
1615 +#include <linux/mtd/physmap.h>
1616 +#include <linux/platform_device.h>
1617 +#include <linux/kernel.h>
1618 +#include <linux/reboot.h>
1619 +#include <linux/leds.h>
1620 +#include <linux/gpio.h>
1621 +#include <asm/bootinfo.h>
1622 +#include <asm/reboot.h>
1623 +#include <asm/time.h>
1624 +#include <linux/irq.h>
1625 +#include <linux/io.h>
1626 +
1627 +#include <ar231x_platform.h>
1628 +#include <ar5312_regs.h>
1629 +#include <ar231x.h>
1630 +#include "devices.h"
1631 +#include "ar5312.h"
1632 +
1633 +static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1634 +{
1635 + unsigned int ar231x_misc_intrs = ar231x_read_reg(AR5312_ISR) &
1636 + ar231x_read_reg(AR5312_IMR);
1637 +
1638 + if (ar231x_misc_intrs & AR5312_ISR_TIMER) {
1639 + do_IRQ(AR5312_MISC_IRQ_TIMER);
1640 + (void)ar231x_read_reg(AR5312_TIMER);
1641 + } else if (ar231x_misc_intrs & AR5312_ISR_AHBPROC)
1642 + do_IRQ(AR5312_MISC_IRQ_AHB_PROC);
1643 + else if ((ar231x_misc_intrs & AR5312_ISR_UART0))
1644 + do_IRQ(AR5312_MISC_IRQ_UART0);
1645 + else if (ar231x_misc_intrs & AR5312_ISR_WD)
1646 + do_IRQ(AR5312_MISC_IRQ_WATCHDOG);
1647 + else
1648 + do_IRQ(AR5312_MISC_IRQ_NONE);
1649 +}
1650 +
1651 +static asmlinkage void
1652 +ar5312_irq_dispatch(void)
1653 +{
1654 + int pending = read_c0_status() & read_c0_cause();
1655 +
1656 + if (pending & CAUSEF_IP2)
1657 + do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1658 + else if (pending & CAUSEF_IP3)
1659 + do_IRQ(AR5312_IRQ_ENET0_INTRS);
1660 + else if (pending & CAUSEF_IP4)
1661 + do_IRQ(AR5312_IRQ_ENET1_INTRS);
1662 + else if (pending & CAUSEF_IP5)
1663 + do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1664 + else if (pending & CAUSEF_IP6)
1665 + do_IRQ(AR5312_IRQ_MISC_INTRS);
1666 + else if (pending & CAUSEF_IP7)
1667 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
1668 +}
1669 +
1670 +
1671 +/* Enable the specified AR5312_MISC_IRQ interrupt */
1672 +static void
1673 +ar5312_misc_irq_unmask(struct irq_data *d)
1674 +{
1675 + unsigned int imr;
1676 +
1677 + imr = ar231x_read_reg(AR5312_IMR);
1678 + imr |= (1 << (d->irq - AR231X_MISC_IRQ_BASE - 1));
1679 + ar231x_write_reg(AR5312_IMR, imr);
1680 +}
1681 +
1682 +/* Disable the specified AR5312_MISC_IRQ interrupt */
1683 +static void
1684 +ar5312_misc_irq_mask(struct irq_data *d)
1685 +{
1686 + unsigned int imr;
1687 +
1688 + imr = ar231x_read_reg(AR5312_IMR);
1689 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE - 1));
1690 + ar231x_write_reg(AR5312_IMR, imr);
1691 + ar231x_read_reg(AR5312_IMR); /* flush write buffer */
1692 +}
1693 +
1694 +static struct irq_chip ar5312_misc_irq_chip = {
1695 + .name = "AR5312-MISC",
1696 + .irq_unmask = ar5312_misc_irq_unmask,
1697 + .irq_mask = ar5312_misc_irq_mask,
1698 +};
1699 +
1700 +
1701 +static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
1702 +{
1703 + u32 proc1 = ar231x_read_reg(AR5312_PROC1);
1704 + u32 proc_addr = ar231x_read_reg(AR5312_PROCADDR); /* clears error */
1705 + u32 dma1 = ar231x_read_reg(AR5312_DMA1);
1706 + u32 dma_addr = ar231x_read_reg(AR5312_DMAADDR); /* clears error */
1707 +
1708 + pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x "
1709 + "DMAADDR=0x%8.8x DMA1=0x%8.8x\n", proc_addr, proc1, dma_addr,
1710 + dma1);
1711 +
1712 + machine_restart("AHB error"); /* Catastrophic failure */
1713 + return IRQ_HANDLED;
1714 +}
1715 +
1716 +
1717 +static struct irqaction ar5312_ahb_proc_interrupt = {
1718 + .handler = ar5312_ahb_proc_handler,
1719 + .name = "ar5312_ahb_proc_interrupt",
1720 +};
1721 +
1722 +
1723 +void __init ar5312_irq_init(void)
1724 +{
1725 + int i;
1726 +
1727 + if (!is_5312())
1728 + return;
1729 +
1730 + ar231x_irq_dispatch = ar5312_irq_dispatch;
1731 + for (i = 0; i < AR5312_MISC_IRQ_COUNT; i++) {
1732 + int irq = AR231X_MISC_IRQ_BASE + i;
1733 +
1734 + irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip,
1735 + handle_level_irq);
1736 + }
1737 + setup_irq(AR5312_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
1738 + irq_set_chained_handler(AR5312_IRQ_MISC_INTRS, ar5312_misc_irq_handler);
1739 +}
1740 +
1741 +/*
1742 + * gpiolib implementations
1743 + */
1744 +static int
1745 +ar5312_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
1746 +{
1747 + return (ar231x_read_reg(AR5312_GPIO_DI) >> gpio) & 1;
1748 +}
1749 +
1750 +static void
1751 +ar5312_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
1752 +{
1753 + u32 reg = ar231x_read_reg(AR5312_GPIO_DO);
1754 +
1755 + reg = value ? reg | (1 << gpio) : reg & ~(1 << gpio);
1756 + ar231x_write_reg(AR5312_GPIO_DO, reg);
1757 +}
1758 +
1759 +static int
1760 +ar5312_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
1761 +{
1762 + ar231x_mask_reg(AR5312_GPIO_CR, 0, 1 << gpio);
1763 + return 0;
1764 +}
1765 +
1766 +static int
1767 +ar5312_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
1768 +{
1769 + ar231x_mask_reg(AR5312_GPIO_CR, 1 << gpio, 0);
1770 + ar5312_gpio_set_value(chip, gpio, value);
1771 + return 0;
1772 +}
1773 +
1774 +static struct gpio_chip ar5312_gpio_chip = {
1775 + .label = "ar5312-gpio",
1776 + .direction_input = ar5312_gpio_direction_input,
1777 + .direction_output = ar5312_gpio_direction_output,
1778 + .set = ar5312_gpio_set_value,
1779 + .get = ar5312_gpio_get_value,
1780 + .base = 0,
1781 + .ngpio = AR5312_NUM_GPIO, /* 8 */
1782 +};
1783 +
1784 +/* end of gpiolib */
1785 +
1786 +static void ar5312_device_reset_set(u32 mask)
1787 +{
1788 + u32 val;
1789 +
1790 + val = ar231x_read_reg(AR5312_RESET);
1791 + ar231x_write_reg(AR5312_RESET, val | mask);
1792 +}
1793 +
1794 +static void ar5312_device_reset_clear(u32 mask)
1795 +{
1796 + u32 val;
1797 +
1798 + val = ar231x_read_reg(AR5312_RESET);
1799 + ar231x_write_reg(AR5312_RESET, val & ~mask);
1800 +}
1801 +
1802 +static struct physmap_flash_data ar5312_flash_data = {
1803 + .width = 2,
1804 +};
1805 +
1806 +static struct resource ar5312_flash_resource = {
1807 + .start = AR5312_FLASH,
1808 + .end = AR5312_FLASH + 0x800000 - 1,
1809 + .flags = IORESOURCE_MEM,
1810 +};
1811 +
1812 +static struct ar231x_eth ar5312_eth0_data = {
1813 + .reset_set = ar5312_device_reset_set,
1814 + .reset_clear = ar5312_device_reset_clear,
1815 + .reset_mac = AR5312_RESET_ENET0,
1816 + .reset_phy = AR5312_RESET_EPHY0,
1817 + .config = &ar231x_board,
1818 +};
1819 +
1820 +static struct ar231x_eth ar5312_eth1_data = {
1821 + .reset_set = ar5312_device_reset_set,
1822 + .reset_clear = ar5312_device_reset_clear,
1823 + .reset_mac = AR5312_RESET_ENET1,
1824 + .reset_phy = AR5312_RESET_EPHY1,
1825 + .config = &ar231x_board,
1826 +};
1827 +
1828 +static struct platform_device ar5312_physmap_flash = {
1829 + .name = "physmap-flash",
1830 + .id = 0,
1831 + .dev.platform_data = &ar5312_flash_data,
1832 + .resource = &ar5312_flash_resource,
1833 + .num_resources = 1,
1834 +};
1835 +
1836 +#ifdef CONFIG_LEDS_GPIO
1837 +static struct gpio_led ar5312_leds[] = {
1838 + { .name = "wlan", .gpio = 0, .active_low = 1, },
1839 +};
1840 +
1841 +static const struct gpio_led_platform_data ar5312_led_data = {
1842 + .num_leds = ARRAY_SIZE(ar5312_leds),
1843 + .leds = (void *)ar5312_leds,
1844 +};
1845 +
1846 +static struct platform_device ar5312_gpio_leds = {
1847 + .name = "leds-gpio",
1848 + .id = -1,
1849 + .dev.platform_data = (void *)&ar5312_led_data,
1850 +};
1851 +#endif
1852 +
1853 +/*
1854 + * NB: This mapping size is larger than the actual flash size,
1855 + * but this shouldn't be a problem here, because the flash
1856 + * will simply be mapped multiple times.
1857 + */
1858 +static char __init *ar5312_flash_limit(void)
1859 +{
1860 + u32 ctl;
1861 + /*
1862 + * Configure flash bank 0.
1863 + * Assume 8M window size. Flash will be aliased if it's smaller
1864 + */
1865 + ctl = FLASHCTL_E |
1866 + FLASHCTL_AC_8M |
1867 + FLASHCTL_RBLE |
1868 + (0x01 << FLASHCTL_IDCY_S) |
1869 + (0x07 << FLASHCTL_WST1_S) |
1870 + (0x07 << FLASHCTL_WST2_S) |
1871 + (ar231x_read_reg(AR5312_FLASHCTL0) & FLASHCTL_MW);
1872 +
1873 + ar231x_write_reg(AR5312_FLASHCTL0, ctl);
1874 +
1875 + /* Disable other flash banks */
1876 + ar231x_write_reg(AR5312_FLASHCTL1,
1877 + ar231x_read_reg(AR5312_FLASHCTL1) &
1878 + ~(FLASHCTL_E | FLASHCTL_AC));
1879 +
1880 + ar231x_write_reg(AR5312_FLASHCTL2,
1881 + ar231x_read_reg(AR5312_FLASHCTL2) &
1882 + ~(FLASHCTL_E | FLASHCTL_AC));
1883 +
1884 + return (char *)KSEG1ADDR(AR5312_FLASH + 0x800000);
1885 +}
1886 +
1887 +int __init ar5312_init_devices(void)
1888 +{
1889 + struct ar231x_boarddata *config;
1890 + u32 fctl = 0;
1891 + u8 *c;
1892 +
1893 + if (!is_5312())
1894 + return 0;
1895 +
1896 + /* Locate board/radio config data */
1897 + ar231x_find_config(ar5312_flash_limit());
1898 + config = ar231x_board.config;
1899 +
1900 + /* AR2313 has CPU minor rev. 10 */
1901 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1902 + ar231x_devtype = DEV_TYPE_AR2313;
1903 +
1904 + /* AR2312 shares the same Silicon ID as AR5312 */
1905 + else if (config->flags & BD_ISCASPER)
1906 + ar231x_devtype = DEV_TYPE_AR2312;
1907 +
1908 + /* Everything else is probably AR5312 or compatible */
1909 + else
1910 + ar231x_devtype = DEV_TYPE_AR5312;
1911 +
1912 + /* fixup flash width */
1913 + fctl = ar231x_read_reg(AR5312_FLASHCTL) & FLASHCTL_MW;
1914 + switch (fctl) {
1915 + case FLASHCTL_MWx16:
1916 + ar5312_flash_data.width = 2;
1917 + break;
1918 + case FLASHCTL_MWx8:
1919 + default:
1920 + ar5312_flash_data.width = 1;
1921 + break;
1922 + }
1923 +
1924 + platform_device_register(&ar5312_physmap_flash);
1925 +
1926 +#ifdef CONFIG_LEDS_GPIO
1927 + ar5312_leds[0].gpio = config->sys_led_gpio;
1928 + platform_device_register(&ar5312_gpio_leds);
1929 +#endif
1930 +
1931 + /* Fix up MAC addresses if necessary */
1932 + if (!memcmp(config->enet0_mac, "\xff\xff\xff\xff\xff\xff", 6))
1933 + memcpy(config->enet0_mac, config->enet1_mac, 6);
1934 +
1935 + /* If ENET0 and ENET1 have the same mac address,
1936 + * increment the one from ENET1 */
1937 + if (memcmp(config->enet0_mac, config->enet1_mac, 6) == 0) {
1938 + c = config->enet1_mac + 5;
1939 + while ((c >= config->enet1_mac) && !(++(*c)))
1940 + c--;
1941 + }
1942 +
1943 + switch (ar231x_devtype) {
1944 + case DEV_TYPE_AR5312:
1945 + ar5312_eth0_data.macaddr = config->enet0_mac;
1946 + ar231x_add_ethernet(0, AR5312_ENET0, "eth0_mii",
1947 + AR5312_ENET0_MII, AR5312_IRQ_ENET0_INTRS,
1948 + &ar5312_eth0_data);
1949 +
1950 + ar5312_eth1_data.macaddr = config->enet1_mac;
1951 + ar231x_add_ethernet(1, AR5312_ENET1, "eth1_mii",
1952 + AR5312_ENET1_MII, AR5312_IRQ_ENET1_INTRS,
1953 + &ar5312_eth1_data);
1954 +
1955 + if (!ar231x_board.radio)
1956 + return 0;
1957 +
1958 + if (!(config->flags & BD_WLAN0))
1959 + break;
1960 +
1961 + ar231x_add_wmac(0, AR5312_WLAN0, AR5312_IRQ_WLAN0_INTRS);
1962 + break;
1963 + /*
1964 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1965 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1966 + */
1967 + case DEV_TYPE_AR2312:
1968 + case DEV_TYPE_AR2313:
1969 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1970 + ar5312_eth1_data.macaddr = config->enet0_mac;
1971 + ar231x_add_ethernet(1, AR5312_ENET1, "eth0_mii",
1972 + AR5312_ENET0_MII, AR5312_IRQ_ENET1_INTRS,
1973 + &ar5312_eth1_data);
1974 +
1975 + if (!ar231x_board.radio)
1976 + return 0;
1977 + break;
1978 + default:
1979 + break;
1980 + }
1981 +
1982 + if (config->flags & BD_WLAN1)
1983 + ar231x_add_wmac(1, AR5312_WLAN1, AR5312_IRQ_WLAN1_INTRS);
1984 +
1985 + return 0;
1986 +}
1987 +
1988 +
1989 +static void ar5312_restart(char *command)
1990 +{
1991 + /* reset the system */
1992 + local_irq_disable();
1993 + while (1)
1994 + ar231x_write_reg(AR5312_RESET, AR5312_RESET_SYSTEM);
1995 +}
1996 +
1997 +
1998 +/*
1999 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2000 + * to determine the predevisor value.
2001 + */
2002 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2003 +
2004 +
2005 +static int __init
2006 +ar5312_cpu_frequency(void)
2007 +{
2008 + unsigned int scratch;
2009 + unsigned int predivide_mask, predivide_shift;
2010 + unsigned int multiplier_mask, multiplier_shift;
2011 + unsigned int clock_ctl1, predivide_select, predivisor, multiplier;
2012 + unsigned int doubler_mask;
2013 + u16 devid;
2014 +
2015 + /* Trust the bootrom's idea of cpu frequency. */
2016 + scratch = ar231x_read_reg(AR5312_SCRATCH);
2017 + if (scratch)
2018 + return scratch;
2019 +
2020 + devid = ar231x_read_reg(AR5312_REV);
2021 + devid &= AR5312_REV_MAJ;
2022 + devid >>= AR5312_REV_MAJ_S;
2023 + if (devid == AR5312_REV_MAJ_AR2313) {
2024 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
2025 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
2026 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
2027 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
2028 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
2029 + } else { /* AR5312 and AR2312 */
2030 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
2031 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
2032 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
2033 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
2034 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
2035 + }
2036 +
2037 + /*
2038 + * Clocking is derived from a fixed 40MHz input clock.
2039 + *
2040 + * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
2041 + * sys_freq = cpu_freq / 4 (used for APB clock, serial,
2042 + * flash, Timer, Watchdog Timer)
2043 + *
2044 + * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
2045 + *
2046 + * So, for example, with a PLL multiplier of 5, we have
2047 + *
2048 + * cpu_freq = 200MHz
2049 + * sys_freq = 50MHz
2050 + * cnt_freq = 100MHz
2051 + *
2052 + * We compute the CPU frequency, based on PLL settings.
2053 + */
2054 +
2055 + clock_ctl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
2056 + predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
2057 + predivisor = clockctl1_predivide_table[predivide_select];
2058 + multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
2059 +
2060 + if (clock_ctl1 & doubler_mask)
2061 + multiplier = multiplier << 1;
2062 +
2063 + return (40000000 / predivisor) * multiplier;
2064 +}
2065 +
2066 +static inline int
2067 +ar5312_sys_frequency(void)
2068 +{
2069 + return ar5312_cpu_frequency() / 4;
2070 +}
2071 +
2072 +void __init
2073 +ar5312_time_init(void)
2074 +{
2075 + if (!is_5312())
2076 + return;
2077 +
2078 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
2079 +}
2080 +
2081 +static int __init
2082 +ar5312_gpio_init(void)
2083 +{
2084 + int ret = gpiochip_add(&ar5312_gpio_chip);
2085 +
2086 + if (ret) {
2087 + pr_err("%s: failed to add gpiochip\n", ar5312_gpio_chip.label);
2088 + return ret;
2089 + }
2090 + pr_info("%s: registered %d GPIOs\n", ar5312_gpio_chip.label,
2091 + ar5312_gpio_chip.ngpio);
2092 + return ret;
2093 +}
2094 +
2095 +void __init
2096 +ar5312_prom_init(void)
2097 +{
2098 + u32 memsize, memcfg, bank0AC, bank1AC;
2099 + u32 devid;
2100 +
2101 + if (!is_5312())
2102 + return;
2103 +
2104 + /* Detect memory size */
2105 + memcfg = ar231x_read_reg(AR5312_MEM_CFG1);
2106 + bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
2107 + bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
2108 + memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) +
2109 + (bank1AC ? (1 << (bank1AC+1)) : 0);
2110 + memsize <<= 20;
2111 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2112 +
2113 + devid = ar231x_read_reg(AR5312_REV);
2114 + devid >>= AR5312_REV_WMAC_MIN_S;
2115 + devid &= AR5312_REV_CHIP;
2116 + ar231x_board.devid = (u16) devid;
2117 + ar5312_gpio_init();
2118 +}
2119 +
2120 +void __init
2121 +ar5312_plat_setup(void)
2122 +{
2123 + if (!is_5312())
2124 + return;
2125 +
2126 + /* Clear any lingering AHB errors */
2127 + ar231x_read_reg(AR5312_PROCADDR);
2128 + ar231x_read_reg(AR5312_DMAADDR);
2129 + ar231x_write_reg(AR5312_WD_CTRL, AR5312_WD_CTRL_IGNORE_EXPIRATION);
2130 +
2131 + _machine_restart = ar5312_restart;
2132 + ar231x_serial_setup(AR5312_UART0, AR5312_MISC_IRQ_UART0,
2133 + ar5312_sys_frequency());
2134 +}
2135 +
2136 --- /dev/null
2137 +++ b/arch/mips/ar231x/ar2315.c
2138 @@ -0,0 +1,559 @@
2139 +/*
2140 + * This file is subject to the terms and conditions of the GNU General Public
2141 + * License. See the file "COPYING" in the main directory of this archive
2142 + * for more details.
2143 + *
2144 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
2145 + * Copyright (C) 2006 FON Technology, SL.
2146 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
2147 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
2148 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
2149 + */
2150 +
2151 +/*
2152 + * Platform devices for Atheros SoCs
2153 + */
2154 +
2155 +#include <generated/autoconf.h>
2156 +#include <linux/init.h>
2157 +#include <linux/module.h>
2158 +#include <linux/types.h>
2159 +#include <linux/string.h>
2160 +#include <linux/platform_device.h>
2161 +#include <linux/kernel.h>
2162 +#include <linux/reboot.h>
2163 +#include <linux/delay.h>
2164 +#include <linux/leds.h>
2165 +#include <linux/gpio.h>
2166 +#include <asm/bootinfo.h>
2167 +#include <asm/reboot.h>
2168 +#include <asm/time.h>
2169 +#include <linux/irq.h>
2170 +#include <linux/io.h>
2171 +
2172 +#include <ar231x_platform.h>
2173 +#include <ar2315_regs.h>
2174 +#include <ar231x.h>
2175 +#include "devices.h"
2176 +#include "ar2315.h"
2177 +
2178 +static u32 gpiointmask, gpiointval;
2179 +
2180 +static void ar2315_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
2181 +{
2182 + u32 pend;
2183 + int bit = -1;
2184 +
2185 + /* only do one gpio interrupt at a time */
2186 + pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask;
2187 +
2188 + if (pend) {
2189 + bit = fls(pend) - 1;
2190 + pend &= ~(1 << bit);
2191 + gpiointval ^= (1 << bit);
2192 + }
2193 +
2194 + if (!pend)
2195 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
2196 +
2197 + /* Enable interrupt with edge detection */
2198 + if ((ar231x_read_reg(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(bit)) !=
2199 + AR2315_GPIO_DIR_I(bit))
2200 + return;
2201 +
2202 + if (bit >= 0)
2203 + do_IRQ(AR231X_GPIO_IRQ_BASE + bit);
2204 +}
2205 +
2206 +static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
2207 +{
2208 + unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) &
2209 + ar231x_read_reg(AR2315_IMR);
2210 +
2211 + if (misc_intr & AR2315_ISR_SPI)
2212 + do_IRQ(AR2315_MISC_IRQ_SPI);
2213 + else if (misc_intr & AR2315_ISR_TIMER)
2214 + do_IRQ(AR2315_MISC_IRQ_TIMER);
2215 + else if (misc_intr & AR2315_ISR_AHB)
2216 + do_IRQ(AR2315_MISC_IRQ_AHB);
2217 + else if (misc_intr & AR2315_ISR_GPIO)
2218 + do_IRQ(AR2315_MISC_IRQ_GPIO);
2219 + else if (misc_intr & AR2315_ISR_UART0)
2220 + do_IRQ(AR2315_MISC_IRQ_UART0);
2221 + else if (misc_intr & AR2315_ISR_WD) {
2222 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_WD);
2223 + do_IRQ(AR2315_MISC_IRQ_WATCHDOG);
2224 + } else
2225 + do_IRQ(AR2315_MISC_IRQ_NONE);
2226 +}
2227 +
2228 +/*
2229 + * Called when an interrupt is received, this function
2230 + * determines exactly which interrupt it was, and it
2231 + * invokes the appropriate handler.
2232 + *
2233 + * Implicitly, we also define interrupt priority by
2234 + * choosing which to dispatch first.
2235 + */
2236 +static asmlinkage void
2237 +ar2315_irq_dispatch(void)
2238 +{
2239 + int pending = read_c0_status() & read_c0_cause();
2240 +
2241 + if (pending & CAUSEF_IP3)
2242 + do_IRQ(AR2315_IRQ_WLAN0_INTRS);
2243 + else if (pending & CAUSEF_IP4)
2244 + do_IRQ(AR2315_IRQ_ENET0_INTRS);
2245 + else if (pending & CAUSEF_IP2)
2246 + do_IRQ(AR2315_IRQ_MISC_INTRS);
2247 + else if (pending & CAUSEF_IP7)
2248 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
2249 +}
2250 +
2251 +static void ar2315_set_gpiointmask(int gpio, int level)
2252 +{
2253 + u32 reg;
2254 +
2255 + reg = ar231x_read_reg(AR2315_GPIO_INT);
2256 + reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M);
2257 + reg |= gpio | AR2315_GPIO_INT_LVL(level);
2258 + ar231x_write_reg(AR2315_GPIO_INT, reg);
2259 +}
2260 +
2261 +static void ar2315_gpio_irq_unmask(struct irq_data *d)
2262 +{
2263 + unsigned int gpio = d->irq - AR231X_GPIO_IRQ_BASE;
2264 +
2265 + /* Enable interrupt with edge detection */
2266 + if ((ar231x_read_reg(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(gpio)) !=
2267 + AR2315_GPIO_DIR_I(gpio))
2268 + return;
2269 +
2270 + gpiointmask |= (1 << gpio);
2271 + ar2315_set_gpiointmask(gpio, 3);
2272 +}
2273 +
2274 +static void ar2315_gpio_irq_mask(struct irq_data *d)
2275 +{
2276 + unsigned int gpio = d->irq - AR231X_GPIO_IRQ_BASE;
2277 +
2278 + /* Disable interrupt */
2279 + gpiointmask &= ~(1 << gpio);
2280 + ar2315_set_gpiointmask(gpio, 0);
2281 +}
2282 +
2283 +static struct irq_chip ar2315_gpio_irq_chip = {
2284 + .name = "AR2315-GPIO",
2285 + .irq_unmask = ar2315_gpio_irq_unmask,
2286 + .irq_mask = ar2315_gpio_irq_mask,
2287 +};
2288 +
2289 +static void
2290 +ar2315_misc_irq_unmask(struct irq_data *d)
2291 +{
2292 + unsigned int imr;
2293 +
2294 + imr = ar231x_read_reg(AR2315_IMR);
2295 + imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE - 1);
2296 + ar231x_write_reg(AR2315_IMR, imr);
2297 +}
2298 +
2299 +static void
2300 +ar2315_misc_irq_mask(struct irq_data *d)
2301 +{
2302 + unsigned int imr;
2303 +
2304 + imr = ar231x_read_reg(AR2315_IMR);
2305 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE - 1));
2306 + ar231x_write_reg(AR2315_IMR, imr);
2307 +}
2308 +
2309 +static struct irq_chip ar2315_misc_irq_chip = {
2310 + .name = "AR2315-MISC",
2311 + .irq_unmask = ar2315_misc_irq_unmask,
2312 + .irq_mask = ar2315_misc_irq_mask,
2313 +};
2314 +
2315 +static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id)
2316 +{
2317 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2318 + ar231x_read_reg(AR2315_AHB_ERR1);
2319 +
2320 + pr_emerg("AHB fatal error\n");
2321 + machine_restart("AHB error"); /* Catastrophic failure */
2322 +
2323 + return IRQ_HANDLED;
2324 +}
2325 +
2326 +static struct irqaction ar2315_ahb_proc_interrupt = {
2327 + .handler = ar2315_ahb_proc_handler,
2328 + .name = "ar2315_ahb_proc_interrupt",
2329 +};
2330 +
2331 +void
2332 +ar2315_irq_init(void)
2333 +{
2334 + int i;
2335 +
2336 + if (!is_2315())
2337 + return;
2338 +
2339 + ar231x_irq_dispatch = ar2315_irq_dispatch;
2340 + gpiointval = ar231x_read_reg(AR2315_GPIO_DI);
2341 + for (i = 0; i < AR2315_MISC_IRQ_COUNT; i++) {
2342 + int irq = AR231X_MISC_IRQ_BASE + i;
2343 +
2344 + irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip,
2345 + handle_level_irq);
2346 + }
2347 + for (i = 0; i < AR2315_NUM_GPIO; i++) {
2348 + int irq = AR231X_GPIO_IRQ_BASE + i;
2349 +
2350 + irq_set_chip_and_handler(irq, &ar2315_gpio_irq_chip,
2351 + handle_level_irq);
2352 + }
2353 + irq_set_chained_handler(AR2315_MISC_IRQ_GPIO, ar2315_gpio_irq_handler);
2354 + setup_irq(AR2315_MISC_IRQ_AHB, &ar2315_ahb_proc_interrupt);
2355 + irq_set_chained_handler(AR2315_IRQ_MISC_INTRS, ar2315_misc_irq_handler);
2356 +}
2357 +
2358 +/*
2359 + * gpiolib implementation
2360 + */
2361 +static int
2362 +ar2315_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
2363 +{
2364 + return (ar231x_read_reg(AR2315_GPIO_DI) >> gpio) & 1;
2365 +}
2366 +
2367 +static void
2368 +ar2315_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
2369 +{
2370 + u32 reg = ar231x_read_reg(AR2315_GPIO_DO);
2371 +
2372 + reg = value ? reg | (1 << gpio) : reg & ~(1 << gpio);
2373 + ar231x_write_reg(AR2315_GPIO_DO, reg);
2374 +}
2375 +
2376 +static int
2377 +ar2315_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
2378 +{
2379 + ar231x_mask_reg(AR2315_GPIO_DIR, 1 << gpio, 0);
2380 + return 0;
2381 +}
2382 +
2383 +static int
2384 +ar2315_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
2385 +{
2386 + ar231x_mask_reg(AR2315_GPIO_DIR, 0, 1 << gpio);
2387 + ar2315_gpio_set_value(chip, gpio, value);
2388 + return 0;
2389 +}
2390 +
2391 +static struct gpio_chip ar2315_gpio_chip = {
2392 + .label = "ar2315-gpio",
2393 + .direction_input = ar2315_gpio_direction_input,
2394 + .direction_output = ar2315_gpio_direction_output,
2395 + .set = ar2315_gpio_set_value,
2396 + .get = ar2315_gpio_get_value,
2397 + .base = 0,
2398 + .ngpio = AR2315_NUM_GPIO, /* 22 */
2399 +};
2400 +
2401 +/* end of gpiolib */
2402 +
2403 +static void ar2315_device_reset_set(u32 mask)
2404 +{
2405 + u32 val;
2406 +
2407 + val = ar231x_read_reg(AR2315_RESET);
2408 + ar231x_write_reg(AR2315_RESET, val | mask);
2409 +}
2410 +
2411 +static void ar2315_device_reset_clear(u32 mask)
2412 +{
2413 + u32 val;
2414 +
2415 + val = ar231x_read_reg(AR2315_RESET);
2416 + ar231x_write_reg(AR2315_RESET, val & ~mask);
2417 +}
2418 +
2419 +static struct ar231x_eth ar2315_eth_data = {
2420 + .reset_set = ar2315_device_reset_set,
2421 + .reset_clear = ar2315_device_reset_clear,
2422 + .reset_mac = AR2315_RESET_ENET0,
2423 + .reset_phy = AR2315_RESET_EPHY0,
2424 + .config = &ar231x_board,
2425 +};
2426 +
2427 +static struct resource ar2315_spiflash_res[] = {
2428 + {
2429 + .name = "spiflash_read",
2430 + .flags = IORESOURCE_MEM,
2431 + .start = AR2315_SPI_READ,
2432 + .end = AR2315_SPI_READ + 0x1000000 - 1,
2433 + },
2434 + {
2435 + .name = "spiflash_mmr",
2436 + .flags = IORESOURCE_MEM,
2437 + .start = AR2315_SPI_MMR,
2438 + .end = AR2315_SPI_MMR + 12 - 1,
2439 + },
2440 +};
2441 +
2442 +static struct platform_device ar2315_spiflash = {
2443 + .id = 0,
2444 + .name = "ar2315-spiflash",
2445 + .resource = ar2315_spiflash_res,
2446 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2447 +};
2448 +
2449 +static struct resource ar2315_wdt_res[] = {
2450 + {
2451 + .flags = IORESOURCE_MEM,
2452 + .start = AR2315_WD,
2453 + .end = AR2315_WD + 8 - 1,
2454 + },
2455 + {
2456 + .flags = IORESOURCE_IRQ,
2457 + .start = AR2315_MISC_IRQ_WATCHDOG,
2458 + .end = AR2315_MISC_IRQ_WATCHDOG,
2459 + }
2460 +};
2461 +
2462 +static struct platform_device ar2315_wdt = {
2463 + .id = 0,
2464 + .name = "ar2315-wdt",
2465 + .resource = ar2315_wdt_res,
2466 + .num_resources = ARRAY_SIZE(ar2315_wdt_res)
2467 +};
2468 +
2469 +/*
2470 + * NB: We use mapping size that is larger than the actual flash size,
2471 + * but this shouldn't be a problem here, because the flash will simply
2472 + * be mapped multiple times.
2473 + */
2474 +static u8 __init *ar2315_flash_limit(void)
2475 +{
2476 + return (u8 *)KSEG1ADDR(ar2315_spiflash_res[0].end + 1);
2477 +}
2478 +
2479 +#ifdef CONFIG_LEDS_GPIO
2480 +static struct gpio_led ar2315_leds[6];
2481 +static struct gpio_led_platform_data ar2315_led_data = {
2482 + .leds = (void *)ar2315_leds,
2483 +};
2484 +
2485 +static struct platform_device ar2315_gpio_leds = {
2486 + .name = "leds-gpio",
2487 + .id = -1,
2488 + .dev = {
2489 + .platform_data = (void *)&ar2315_led_data,
2490 + }
2491 +};
2492 +
2493 +static void __init
2494 +ar2315_init_gpio_leds(void)
2495 +{
2496 + static char led_names[6][6];
2497 + int i, led = 0;
2498 +
2499 + ar2315_led_data.num_leds = 0;
2500 + for (i = 1; i < 8; i++) {
2501 + if ((i == AR2315_RESET_GPIO) ||
2502 + (i == ar231x_board.config->reset_config_gpio))
2503 + continue;
2504 +
2505 + if (i == ar231x_board.config->sys_led_gpio)
2506 + strcpy(led_names[led], "wlan");
2507 + else
2508 + sprintf(led_names[led], "gpio%d", i);
2509 +
2510 + ar2315_leds[led].name = led_names[led];
2511 + ar2315_leds[led].gpio = i;
2512 + ar2315_leds[led].active_low = 0;
2513 + led++;
2514 + }
2515 + ar2315_led_data.num_leds = led;
2516 + platform_device_register(&ar2315_gpio_leds);
2517 +}
2518 +#else
2519 +static inline void ar2315_init_gpio_leds(void)
2520 +{
2521 +}
2522 +#endif
2523 +
2524 +int __init
2525 +ar2315_init_devices(void)
2526 +{
2527 + if (!is_2315())
2528 + return 0;
2529 +
2530 + /* Find board configuration */
2531 + ar231x_find_config(ar2315_flash_limit());
2532 + ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac;
2533 +
2534 + ar2315_init_gpio_leds();
2535 + platform_device_register(&ar2315_wdt);
2536 + platform_device_register(&ar2315_spiflash);
2537 + ar231x_add_ethernet(0, AR2315_ENET0, "eth0_mii", AR2315_ENET0_MII,
2538 + AR2315_IRQ_ENET0_INTRS, &ar2315_eth_data);
2539 + ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
2540 +
2541 + return 0;
2542 +}
2543 +
2544 +static void
2545 +ar2315_restart(char *command)
2546 +{
2547 + void (*mips_reset_vec)(void) = (void *)0xbfc00000;
2548 +
2549 + local_irq_disable();
2550 +
2551 + /* try reset the system via reset control */
2552 + ar231x_write_reg(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
2553 +
2554 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
2555 + * a workaround. Give it some time to attempt a gpio based hardware
2556 + * reset (atheros reference design workaround) */
2557 + gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
2558 + mdelay(100);
2559 +
2560 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2561 + * workaround. Attempt to jump to the mips reset location -
2562 + * the boot loader itself might be able to recover the system */
2563 + mips_reset_vec();
2564 +}
2565 +
2566 +
2567 +/*
2568 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2569 + * to determine the predevisor value.
2570 + */
2571 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2572 +static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
2573 +
2574 +static unsigned int __init
2575 +ar2315_sys_clk(unsigned int clock_ctl)
2576 +{
2577 + unsigned int pllc_ctrl, cpu_div;
2578 + unsigned int pllc_out, refdiv, fdiv, divby2;
2579 + unsigned int clk_div;
2580 +
2581 + pllc_ctrl = ar231x_read_reg(AR2315_PLLC_CTL);
2582 + refdiv = (pllc_ctrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
2583 + refdiv = clockctl1_predivide_table[refdiv];
2584 + fdiv = (pllc_ctrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
2585 + divby2 = (pllc_ctrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
2586 + divby2 += 1;
2587 + pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
2588 +
2589 + /* clkm input selected */
2590 + switch (clock_ctl & CPUCLK_CLK_SEL_M) {
2591 + case 0:
2592 + case 1:
2593 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKM_DIV_M) >>
2594 + PLLC_CLKM_DIV_S];
2595 + break;
2596 + case 2:
2597 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKC_DIV_M) >>
2598 + PLLC_CLKC_DIV_S];
2599 + break;
2600 + default:
2601 + pllc_out = 40000000;
2602 + clk_div = 1;
2603 + break;
2604 + }
2605 +
2606 + cpu_div = (clock_ctl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
2607 + cpu_div = cpu_div * 2 ?: 1;
2608 +
2609 + return pllc_out / (clk_div * cpu_div);
2610 +}
2611 +
2612 +static inline unsigned int
2613 +ar2315_cpu_frequency(void)
2614 +{
2615 + return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
2616 +}
2617 +
2618 +static inline unsigned int
2619 +ar2315_apb_frequency(void)
2620 +{
2621 + return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
2622 +}
2623 +
2624 +void __init
2625 +ar2315_time_init(void)
2626 +{
2627 + if (!is_2315())
2628 + return;
2629 +
2630 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2631 +}
2632 +
2633 +static int __init
2634 +ar2315_gpio_init(void)
2635 +{
2636 + int ret = gpiochip_add(&ar2315_gpio_chip);
2637 +
2638 + if (ret) {
2639 + pr_err("%s: failed to add gpiochip\n", ar2315_gpio_chip.label);
2640 + return ret;
2641 + }
2642 + pr_info("%s: registered %d GPIOs\n", ar2315_gpio_chip.label,
2643 + ar2315_gpio_chip.ngpio);
2644 + return ret;
2645 +}
2646 +
2647 +
2648 +
2649 +void __init
2650 +ar2315_prom_init(void)
2651 +{
2652 + u32 memsize, memcfg, devid;
2653 +
2654 + if (!is_2315())
2655 + return;
2656 +
2657 + memcfg = ar231x_read_reg(AR2315_MEM_CFG);
2658 + memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
2659 + memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
2660 + memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
2661 + memsize <<= 3;
2662 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2663 +
2664 + /* Detect the hardware based on the device ID */
2665 + devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
2666 + switch (devid) {
2667 + case 0x90:
2668 + case 0x91:
2669 + ar231x_devtype = DEV_TYPE_AR2317;
2670 + break;
2671 + default:
2672 + ar231x_devtype = DEV_TYPE_AR2315;
2673 + break;
2674 + }
2675 + ar2315_gpio_init();
2676 + ar231x_board.devid = devid;
2677 +}
2678 +
2679 +void __init
2680 +ar2315_plat_setup(void)
2681 +{
2682 + u32 config;
2683 +
2684 + if (!is_2315())
2685 + return;
2686 +
2687 + /* Clear any lingering AHB errors */
2688 + config = read_c0_config();
2689 + write_c0_config(config & ~0x3);
2690 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2691 + ar231x_read_reg(AR2315_AHB_ERR1);
2692 + ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
2693 +
2694 + _machine_restart = ar2315_restart;
2695 + ar231x_serial_setup(AR2315_UART0, AR2315_MISC_IRQ_UART0,
2696 + ar2315_apb_frequency());
2697 +}
2698 --- /dev/null
2699 +++ b/arch/mips/ar231x/ar2315.h
2700 @@ -0,0 +1,37 @@
2701 +#ifndef __AR2315_H
2702 +#define __AR2315_H
2703 +
2704 +#ifdef CONFIG_ATHEROS_AR2315
2705 +
2706 +void ar2315_irq_init(void);
2707 +int ar2315_init_devices(void);
2708 +void ar2315_prom_init(void);
2709 +void ar2315_plat_setup(void);
2710 +void ar2315_time_init(void);
2711 +
2712 +#else
2713 +
2714 +static inline void ar2315_irq_init(void)
2715 +{
2716 +}
2717 +
2718 +static inline int ar2315_init_devices(void)
2719 +{
2720 + return 0;
2721 +}
2722 +
2723 +static inline void ar2315_prom_init(void)
2724 +{
2725 +}
2726 +
2727 +static inline void ar2315_plat_setup(void)
2728 +{
2729 +}
2730 +
2731 +static inline void ar2315_time_init(void)
2732 +{
2733 +}
2734 +
2735 +#endif
2736 +
2737 +#endif
2738 --- /dev/null
2739 +++ b/arch/mips/ar231x/ar5312.h
2740 @@ -0,0 +1,37 @@
2741 +#ifndef __AR5312_H
2742 +#define __AR5312_H
2743 +
2744 +#ifdef CONFIG_ATHEROS_AR5312
2745 +
2746 +void ar5312_irq_init(void);
2747 +int ar5312_init_devices(void);
2748 +void ar5312_prom_init(void);
2749 +void ar5312_plat_setup(void);
2750 +void ar5312_time_init(void);
2751 +
2752 +#else
2753 +
2754 +static inline void ar5312_irq_init(void)
2755 +{
2756 +}
2757 +
2758 +static inline int ar5312_init_devices(void)
2759 +{
2760 + return 0;
2761 +}
2762 +
2763 +static inline void ar5312_prom_init(void)
2764 +{
2765 +}
2766 +
2767 +static inline void ar5312_plat_setup(void)
2768 +{
2769 +}
2770 +
2771 +static inline void ar5312_time_init(void)
2772 +{
2773 +}
2774 +
2775 +#endif
2776 +
2777 +#endif
2778 --- /dev/null
2779 +++ b/arch/mips/include/asm/mach-ar231x/ar231x.h
2780 @@ -0,0 +1,43 @@
2781 +#ifndef __ASM_MACH_AR231X_H
2782 +#define __ASM_MACH_AR231X_H
2783 +
2784 +#include <linux/types.h>
2785 +#include <linux/io.h>
2786 +
2787 +#define AR231X_MISC_IRQ_BASE 0x20
2788 +#define AR231X_GPIO_IRQ_BASE 0x30
2789 +
2790 +/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
2791 +#define AR231X_IRQ_NONE (MIPS_CPU_IRQ_BASE+0)
2792 +#define AR231X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
2793 +
2794 +/* GPIO Interrupts, share ARXXXX_MISC_IRQ_GPIO */
2795 +#define AR231X_GPIO_IRQ_NONE (AR231X_GPIO_IRQ_BASE+0)
2796 +#define AR231X_GPIO_IRQ(n) (AR231X_GPIO_IRQ_BASE+n)
2797 +
2798 +static inline u32
2799 +ar231x_read_reg(u32 reg)
2800 +{
2801 + return __raw_readl((void __iomem *)KSEG1ADDR(reg));
2802 +}
2803 +
2804 +static inline void
2805 +ar231x_write_reg(u32 reg, u32 val)
2806 +{
2807 + __raw_writel(val, (void __iomem *)KSEG1ADDR(reg));
2808 +}
2809 +
2810 +static inline u32
2811 +ar231x_mask_reg(u32 reg, u32 mask, u32 val)
2812 +{
2813 + u32 ret;
2814 +
2815 + ret = ar231x_read_reg(reg);
2816 + ret &= ~mask;
2817 + ret |= val;
2818 + ar231x_write_reg(reg, ret);
2819 +
2820 + return ret;
2821 +}
2822 +
2823 +#endif /* __ASM_MACH_AR231X_H */
2824 --- /dev/null
2825 +++ b/arch/mips/ar231x/devices.h
2826 @@ -0,0 +1,38 @@
2827 +#ifndef __AR231X_DEVICES_H
2828 +#define __AR231X_DEVICES_H
2829 +
2830 +enum {
2831 + /* handled by ar5312.c */
2832 + DEV_TYPE_AR2312,
2833 + DEV_TYPE_AR2313,
2834 + DEV_TYPE_AR5312,
2835 +
2836 + /* handled by ar2315.c */
2837 + DEV_TYPE_AR2315,
2838 + DEV_TYPE_AR2316,
2839 + DEV_TYPE_AR2317,
2840 +
2841 + DEV_TYPE_UNKNOWN
2842 +};
2843 +
2844 +extern int ar231x_devtype;
2845 +extern struct ar231x_board_config ar231x_board;
2846 +extern asmlinkage void (*ar231x_irq_dispatch)(void);
2847 +
2848 +int ar231x_find_config(u8 *flash_limit);
2849 +void ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
2850 +int ar231x_add_wmac(int nr, u32 base, int irq);
2851 +int ar231x_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
2852 + int irq, void *pdata);
2853 +
2854 +static inline bool is_2315(void)
2855 +{
2856 + return (current_cpu_data.cputype == CPU_4KEC);
2857 +}
2858 +
2859 +static inline bool is_5312(void)
2860 +{
2861 + return !is_2315();
2862 +}
2863 +
2864 +#endif
2865 --- /dev/null
2866 +++ b/arch/mips/ar231x/devices.c
2867 @@ -0,0 +1,182 @@
2868 +#include <linux/kernel.h>
2869 +#include <linux/init.h>
2870 +#include <linux/serial.h>
2871 +#include <linux/serial_core.h>
2872 +#include <linux/serial_8250.h>
2873 +#include <linux/platform_device.h>
2874 +#include <asm/bootinfo.h>
2875 +
2876 +#include <ar231x_platform.h>
2877 +#include <ar231x.h>
2878 +#include "devices.h"
2879 +#include "ar5312.h"
2880 +#include "ar2315.h"
2881 +
2882 +struct ar231x_board_config ar231x_board;
2883 +int ar231x_devtype = DEV_TYPE_UNKNOWN;
2884 +
2885 +static struct resource ar231x_eth0_res[] = {
2886 + {
2887 + .name = "eth0_membase",
2888 + .flags = IORESOURCE_MEM,
2889 + },
2890 + {
2891 + .name = "eth0_mii",
2892 + .flags = IORESOURCE_MEM,
2893 + },
2894 + {
2895 + .name = "eth0_irq",
2896 + .flags = IORESOURCE_IRQ,
2897 + }
2898 +};
2899 +
2900 +static struct resource ar231x_eth1_res[] = {
2901 + {
2902 + .name = "eth1_membase",
2903 + .flags = IORESOURCE_MEM,
2904 + },
2905 + {
2906 + .name = "eth1_mii",
2907 + .flags = IORESOURCE_MEM,
2908 + },
2909 + {
2910 + .name = "eth1_irq",
2911 + .flags = IORESOURCE_IRQ,
2912 + }
2913 +};
2914 +
2915 +static struct platform_device ar231x_eth[] = {
2916 + {
2917 + .id = 0,
2918 + .name = "ar231x-eth",
2919 + .resource = ar231x_eth0_res,
2920 + .num_resources = ARRAY_SIZE(ar231x_eth0_res)
2921 + },
2922 + {
2923 + .id = 1,
2924 + .name = "ar231x-eth",
2925 + .resource = ar231x_eth1_res,
2926 + .num_resources = ARRAY_SIZE(ar231x_eth1_res)
2927 + }
2928 +};
2929 +
2930 +static struct resource ar231x_wmac0_res[] = {
2931 + {
2932 + .name = "wmac0_membase",
2933 + .flags = IORESOURCE_MEM,
2934 + },
2935 + {
2936 + .name = "wmac0_irq",
2937 + .flags = IORESOURCE_IRQ,
2938 + }
2939 +};
2940 +
2941 +static struct resource ar231x_wmac1_res[] = {
2942 + {
2943 + .name = "wmac1_membase",
2944 + .flags = IORESOURCE_MEM,
2945 + },
2946 + {
2947 + .name = "wmac1_irq",
2948 + .flags = IORESOURCE_IRQ,
2949 + }
2950 +};
2951 +
2952 +
2953 +static struct platform_device ar231x_wmac[] = {
2954 + {
2955 + .id = 0,
2956 + .name = "ar231x-wmac",
2957 + .resource = ar231x_wmac0_res,
2958 + .num_resources = ARRAY_SIZE(ar231x_wmac0_res),
2959 + .dev.platform_data = &ar231x_board,
2960 + },
2961 + {
2962 + .id = 1,
2963 + .name = "ar231x-wmac",
2964 + .resource = ar231x_wmac1_res,
2965 + .num_resources = ARRAY_SIZE(ar231x_wmac1_res),
2966 + .dev.platform_data = &ar231x_board,
2967 + },
2968 +};
2969 +
2970 +static const char * const devtype_strings[] = {
2971 + [DEV_TYPE_AR5312] = "Atheros AR5312",
2972 + [DEV_TYPE_AR2312] = "Atheros AR2312",
2973 + [DEV_TYPE_AR2313] = "Atheros AR2313",
2974 + [DEV_TYPE_AR2315] = "Atheros AR2315",
2975 + [DEV_TYPE_AR2316] = "Atheros AR2316",
2976 + [DEV_TYPE_AR2317] = "Atheros AR2317",
2977 + [DEV_TYPE_UNKNOWN] = "Atheros (unknown)",
2978 +};
2979 +
2980 +const char *get_system_type(void)
2981 +{
2982 + if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) ||
2983 + !devtype_strings[ar231x_devtype])
2984 + return devtype_strings[DEV_TYPE_UNKNOWN];
2985 + return devtype_strings[ar231x_devtype];
2986 +}
2987 +
2988 +
2989 +int __init
2990 +ar231x_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
2991 + int irq, void *pdata)
2992 +{
2993 + struct resource *res;
2994 +
2995 + ar231x_eth[nr].dev.platform_data = pdata;
2996 + res = &ar231x_eth[nr].resource[0];
2997 + res->start = base;
2998 + res->end = base + 0x2000 - 1;
2999 + res++;
3000 + res->name = mii_name;
3001 + res->start = mii_base;
3002 + res->end = mii_base + 8 - 1;
3003 + res++;
3004 + res->start = irq;
3005 + res->end = irq;
3006 + return platform_device_register(&ar231x_eth[nr]);
3007 +}
3008 +
3009 +void __init
3010 +ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
3011 +{
3012 + struct uart_port s;
3013 +
3014 + memset(&s, 0, sizeof(s));
3015 +
3016 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
3017 + s.iotype = UPIO_MEM32;
3018 + s.irq = irq;
3019 + s.regshift = 2;
3020 + s.mapbase = mapbase;
3021 + s.uartclk = uartclk;
3022 +
3023 + early_serial_setup(&s);
3024 +}
3025 +
3026 +int __init
3027 +ar231x_add_wmac(int nr, u32 base, int irq)
3028 +{
3029 + struct resource *res;
3030 +
3031 + ar231x_wmac[nr].dev.platform_data = &ar231x_board;
3032 + res = &ar231x_wmac[nr].resource[0];
3033 + res->start = base;
3034 + res->end = base + 0x10000 - 1;
3035 + res++;
3036 + res->start = irq;
3037 + res->end = irq;
3038 + return platform_device_register(&ar231x_wmac[nr]);
3039 +}
3040 +
3041 +static int __init ar231x_register_devices(void)
3042 +{
3043 + ar5312_init_devices();
3044 + ar2315_init_devices();
3045 +
3046 + return 0;
3047 +}
3048 +
3049 +device_initcall(ar231x_register_devices);
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