target/linux/brcm63xx/files/arch/mips/bcm63xx/cpu.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   7  *               2009 Florian Fainelli <florian@openwrt.org>
   8  */
   9
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/cpu.h>
  13 #include <bcm63xx_cpu.h>
  14 #include <bcm63xx_regs.h>
  15 #include <bcm63xx_io.h>
  16 #include <bcm63xx_irq.h>
  17
  18 const unsigned long *bcm63xx_regs_base;
  19 EXPORT_SYMBOL(bcm63xx_regs_base);
  20
  21 const int *bcm63xx_irqs;
  22 EXPORT_SYMBOL(bcm63xx_irqs);
  23
  24 const unsigned long *bcm63xx_regs_spi;
  25 EXPORT_SYMBOL(bcm63xx_regs_spi);
  26
  27 static u16 bcm63xx_cpu_id;
  28 static u16 bcm63xx_cpu_rev;
  29 static unsigned int bcm63xx_cpu_freq;
  30 static unsigned int bcm63xx_memory_size;
  31
  32 /*
  33  * 6338 register sets and irqs
  34  */
  35
  36 static const unsigned long bcm96338_regs_base[] = {
  37         [RSET_DSL_LMEM]         = BCM_6338_DSL_LMEM_BASE,
  38         [RSET_PERF]             = BCM_6338_PERF_BASE,
  39         [RSET_TIMER]            = BCM_6338_TIMER_BASE,
  40         [RSET_WDT]              = BCM_6338_WDT_BASE,
  41         [RSET_UART0]            = BCM_6338_UART0_BASE,
  42         [RSET_GPIO]             = BCM_6338_GPIO_BASE,
  43         [RSET_SPI]              = BCM_6338_SPI_BASE,
  44         [RSET_OHCI0]            = BCM_6338_OHCI0_BASE,
  45         [RSET_OHCI_PRIV]        = BCM_6338_OHCI_PRIV_BASE,
  46         [RSET_USBH_PRIV]        = BCM_6338_USBH_PRIV_BASE,
  47         [RSET_UDC0]             = BCM_6338_UDC0_BASE,
  48         [RSET_MPI]              = BCM_6338_MPI_BASE,
  49         [RSET_PCMCIA]           = BCM_6338_PCMCIA_BASE,
  50         [RSET_SDRAM]            = BCM_6338_SDRAM_BASE,
  51         [RSET_DSL]              = BCM_6338_DSL_BASE,
  52         [RSET_ENET0]            = BCM_6338_ENET0_BASE,
  53         [RSET_ENET1]            = BCM_6338_ENET1_BASE,
  54         [RSET_ENETDMA]          = BCM_6338_ENETDMA_BASE,
  55         [RSET_MEMC]             = BCM_6338_MEMC_BASE,
  56         [RSET_DDR]              = BCM_6338_DDR_BASE,
  57 };
  58
  59 static const int bcm96338_irqs[] = {
  60         [IRQ_TIMER]             = BCM_6338_TIMER_IRQ,
  61         [IRQ_SPI]               = BCM_6338_SPI_IRQ,
  62         [IRQ_UART0]             = BCM_6338_UART0_IRQ,
  63         [IRQ_DSL]               = BCM_6338_DSL_IRQ,
  64         [IRQ_UDC0]              = BCM_6338_UDC0_IRQ,
  65         [IRQ_ENET0]             = BCM_6338_ENET0_IRQ,
  66         [IRQ_ENET_PHY]          = BCM_6338_ENET_PHY_IRQ,
  67         [IRQ_ENET0_RXDMA]       = BCM_6338_ENET0_RXDMA_IRQ,
  68         [IRQ_ENET0_TXDMA]       = BCM_6338_ENET0_TXDMA_IRQ,
  69 };
  70
  71 static const unsigned long bcm96338_regs_spi[] = {
  72         [SPI_CMD]               = SPI_BCM_6338_SPI_CMD,
  73         [SPI_INT_STATUS]        = SPI_BCM_6338_SPI_INT_STATUS,
  74         [SPI_INT_MASK_ST]       = SPI_BCM_6338_SPI_MASK_INT_ST,
  75         [SPI_INT_MASK]          = SPI_BCM_6338_SPI_INT_MASK,
  76         [SPI_ST]                = SPI_BCM_6338_SPI_ST,
  77         [SPI_CLK_CFG]           = SPI_BCM_6338_SPI_CLK_CFG,
  78         [SPI_FILL_BYTE]         = SPI_BCM_6338_SPI_FILL_BYTE,
  79         [SPI_MSG_TAIL]          = SPI_BCM_6338_SPI_MSG_TAIL,
  80         [SPI_RX_TAIL]           = SPI_BCM_6338_SPI_RX_TAIL,
  81         [SPI_MSG_CTL]           = SPI_BCM_6338_SPI_MSG_CTL,
  82         [SPI_MSG_DATA]          = SPI_BCM_6338_SPI_MSG_DATA,
  83         [SPI_RX_DATA]           = SPI_BCM_6338_SPI_RX_DATA,
  84 };
  85
  86 /*
  87  * 6345 register sets and irqs
  88  */
  89
  90 static const unsigned long bcm96345_regs_base[] = {
  91         [RSET_PERF]             = BCM_6345_PERF_BASE,
  92         [RSET_TIMER]            = BCM_6345_TIMER_BASE,
  93         [RSET_WDT]              = BCM_6345_WDT_BASE,
  94         [RSET_UART0]            = BCM_6345_UART0_BASE,
  95         [RSET_GPIO]             = BCM_6345_GPIO_BASE,
  96 };
  97
  98 static const int bcm96345_irqs[] = {
  99         [IRQ_TIMER]             = BCM_6345_TIMER_IRQ,
 100         [IRQ_UART0]             = BCM_6345_UART0_IRQ,
 101         [IRQ_DSL]               = BCM_6345_DSL_IRQ,
 102         [IRQ_ENET0]             = BCM_6345_ENET0_IRQ,
 103         [IRQ_ENET_PHY]          = BCM_6345_ENET_PHY_IRQ,
 104 };
 105
 106 /*
 107  * 6348 register sets and irqs
 108  */
 109 static const unsigned long bcm96348_regs_base[] = {
 110         [RSET_DSL_LMEM]         = BCM_6348_DSL_LMEM_BASE,
 111         [RSET_PERF]             = BCM_6348_PERF_BASE,
 112         [RSET_TIMER]            = BCM_6348_TIMER_BASE,
 113         [RSET_WDT]              = BCM_6348_WDT_BASE,
 114         [RSET_UART0]            = BCM_6348_UART0_BASE,
 115         [RSET_GPIO]             = BCM_6348_GPIO_BASE,
 116         [RSET_SPI]              = BCM_6348_SPI_BASE,
 117         [RSET_OHCI0]            = BCM_6348_OHCI0_BASE,
 118         [RSET_OHCI_PRIV]        = BCM_6348_OHCI_PRIV_BASE,
 119         [RSET_USBH_PRIV]        = BCM_6348_USBH_PRIV_BASE,
 120         [RSET_UDC0]             = BCM_6348_UDC0_BASE,
 121         [RSET_MPI]              = BCM_6348_MPI_BASE,
 122         [RSET_PCMCIA]           = BCM_6348_PCMCIA_BASE,
 123         [RSET_SDRAM]            = BCM_6348_SDRAM_BASE,
 124         [RSET_DSL]              = BCM_6348_DSL_BASE,
 125         [RSET_ENET0]            = BCM_6348_ENET0_BASE,
 126         [RSET_ENET1]            = BCM_6348_ENET1_BASE,
 127         [RSET_ENETDMA]          = BCM_6348_ENETDMA_BASE,
 128         [RSET_MEMC]             = BCM_6348_MEMC_BASE,
 129         [RSET_DDR]              = BCM_6348_DDR_BASE,
 130 };
 131
 132 static const int bcm96348_irqs[] = {
 133         [IRQ_TIMER]             = BCM_6348_TIMER_IRQ,
 134         [IRQ_SPI]               = BCM_6348_SPI_IRQ,
 135         [IRQ_UART0]             = BCM_6348_UART0_IRQ,
 136         [IRQ_DSL]               = BCM_6348_DSL_IRQ,
 137         [IRQ_UDC0]              = BCM_6348_UDC0_IRQ,
 138         [IRQ_ENET0]             = BCM_6348_ENET0_IRQ,
 139         [IRQ_ENET1]             = BCM_6348_ENET1_IRQ,
 140         [IRQ_ENET_PHY]          = BCM_6348_ENET_PHY_IRQ,
 141         [IRQ_OHCI0]             = BCM_6348_OHCI0_IRQ,
 142         [IRQ_PCMCIA]            = BCM_6348_PCMCIA_IRQ,
 143         [IRQ_ENET0_RXDMA]       = BCM_6348_ENET0_RXDMA_IRQ,
 144         [IRQ_ENET0_TXDMA]       = BCM_6348_ENET0_TXDMA_IRQ,
 145         [IRQ_ENET1_RXDMA]       = BCM_6348_ENET1_RXDMA_IRQ,
 146         [IRQ_ENET1_TXDMA]       = BCM_6348_ENET1_TXDMA_IRQ,
 147         [IRQ_PCI]               = BCM_6348_PCI_IRQ,
 148 };
 149
 150 static const unsigned long bcm96348_regs_spi[] = {
 151         [SPI_CMD]               = SPI_BCM_6348_SPI_CMD,
 152         [SPI_INT_STATUS]        = SPI_BCM_6348_SPI_INT_STATUS,
 153         [SPI_INT_MASK_ST]       = SPI_BCM_6348_SPI_MASK_INT_ST,
 154         [SPI_INT_MASK]          = SPI_BCM_6348_SPI_INT_MASK,
 155         [SPI_ST]                = SPI_BCM_6348_SPI_ST,
 156         [SPI_CLK_CFG]           = SPI_BCM_6348_SPI_CLK_CFG,
 157         [SPI_FILL_BYTE]         = SPI_BCM_6348_SPI_FILL_BYTE,
 158         [SPI_MSG_TAIL]          = SPI_BCM_6348_SPI_MSG_TAIL,
 159         [SPI_RX_TAIL]           = SPI_BCM_6348_SPI_RX_TAIL,
 160         [SPI_MSG_CTL]           = SPI_BCM_6348_SPI_MSG_CTL,
 161         [SPI_MSG_DATA]          = SPI_BCM_6348_SPI_MSG_DATA,
 162         [SPI_RX_DATA]           = SPI_BCM_6348_SPI_RX_DATA,
 163 };
 164
 165 /*
 166  * 6358 register sets and irqs
 167  */
 168 static const unsigned long bcm96358_regs_base[] = {
 169         [RSET_DSL_LMEM]         = BCM_6358_DSL_LMEM_BASE,
 170         [RSET_PERF]             = BCM_6358_PERF_BASE,
 171         [RSET_TIMER]            = BCM_6358_TIMER_BASE,
 172         [RSET_WDT]              = BCM_6358_WDT_BASE,
 173         [RSET_UART0]            = BCM_6358_UART0_BASE,
 174         [RSET_GPIO]             = BCM_6358_GPIO_BASE,
 175         [RSET_SPI]              = BCM_6358_SPI_BASE,
 176         [RSET_OHCI0]            = BCM_6358_OHCI0_BASE,
 177         [RSET_EHCI0]            = BCM_6358_EHCI0_BASE,
 178         [RSET_OHCI_PRIV]        = BCM_6358_OHCI_PRIV_BASE,
 179         [RSET_USBH_PRIV]        = BCM_6358_USBH_PRIV_BASE,
 180         [RSET_MPI]              = BCM_6358_MPI_BASE,
 181         [RSET_PCMCIA]           = BCM_6358_PCMCIA_BASE,
 182         [RSET_SDRAM]            = BCM_6358_SDRAM_BASE,
 183         [RSET_DSL]              = BCM_6358_DSL_BASE,
 184         [RSET_ENET0]            = BCM_6358_ENET0_BASE,
 185         [RSET_ENET1]            = BCM_6358_ENET1_BASE,
 186         [RSET_ENETDMA]          = BCM_6358_ENETDMA_BASE,
 187         [RSET_MEMC]             = BCM_6358_MEMC_BASE,
 188         [RSET_DDR]              = BCM_6358_DDR_BASE,
 189 };
 190
 191 static const int bcm96358_irqs[] = {
 192         [IRQ_TIMER]             = BCM_6358_TIMER_IRQ,
 193         [IRQ_SPI]               = BCM_6358_SPI_IRQ,
 194         [IRQ_UART0]             = BCM_6358_UART0_IRQ,
 195         [IRQ_DSL]               = BCM_6358_DSL_IRQ,
 196         [IRQ_ENET0]             = BCM_6358_ENET0_IRQ,
 197         [IRQ_ENET1]             = BCM_6358_ENET1_IRQ,
 198         [IRQ_ENET_PHY]          = BCM_6358_ENET_PHY_IRQ,
 199         [IRQ_OHCI0]             = BCM_6358_OHCI0_IRQ,
 200         [IRQ_EHCI0]             = BCM_6358_EHCI0_IRQ,
 201         [IRQ_PCMCIA]            = BCM_6358_PCMCIA_IRQ,
 202         [IRQ_ENET0_RXDMA]       = BCM_6358_ENET0_RXDMA_IRQ,
 203         [IRQ_ENET0_TXDMA]       = BCM_6358_ENET0_TXDMA_IRQ,
 204         [IRQ_ENET1_RXDMA]       = BCM_6358_ENET1_RXDMA_IRQ,
 205         [IRQ_ENET1_TXDMA]       = BCM_6358_ENET1_TXDMA_IRQ,
 206         [IRQ_PCI]               = BCM_6358_PCI_IRQ,
 207 };
 208
 209 static const unsigned long bcm96358_regs_spi[] = {
 210         [SPI_CMD]               = SPI_BCM_6358_SPI_CMD,
 211         [SPI_INT_STATUS]        = SPI_BCM_6358_SPI_INT_STATUS,
 212         [SPI_INT_MASK_ST]       = SPI_BCM_6358_SPI_MASK_INT_ST,
 213         [SPI_INT_MASK]          = SPI_BCM_6358_SPI_INT_MASK,
 214         [SPI_ST]                = SPI_BCM_6358_SPI_STATUS,
 215         [SPI_CLK_CFG]           = SPI_BCM_6358_SPI_CLK_CFG,
 216         [SPI_FILL_BYTE]         = SPI_BCM_6358_SPI_FILL_BYTE,
 217         [SPI_MSG_TAIL]          = SPI_BCM_6358_SPI_MSG_TAIL,
 218         [SPI_RX_TAIL]           = SPI_BCM_6358_SPI_RX_TAIL,
 219         [SPI_MSG_CTL]           = SPI_BCM_6358_MSG_CTL,
 220         [SPI_MSG_DATA]          = SPI_BCM_6358_SPI_MSG_DATA,
 221         [SPI_RX_DATA]           = SPI_BCM_6358_SPI_RX_DATA,
 222 };
 223
 224 u16 __bcm63xx_get_cpu_id(void)
 225 {
 226         return bcm63xx_cpu_id;
 227 }
 228
 229 EXPORT_SYMBOL(__bcm63xx_get_cpu_id);
 230
 231 u16 bcm63xx_get_cpu_rev(void)
 232 {
 233         return bcm63xx_cpu_rev;
 234 }
 235
 236 EXPORT_SYMBOL(bcm63xx_get_cpu_rev);
 237
 238 unsigned int bcm63xx_get_cpu_freq(void)
 239 {
 240         return bcm63xx_cpu_freq;
 241 }
 242
 243 unsigned int bcm63xx_get_memory_size(void)
 244 {
 245         return bcm63xx_memory_size;
 246 }
 247
 248 static unsigned int detect_cpu_clock(void)
 249 {
 250         unsigned int tmp, n1 = 0, n2 = 0, m1 = 0;
 251
 252         if (BCMCPU_IS_6338())
 253                 return 240000000;
 254
 255         if (BCMCPU_IS_6345())
 256                 return 140000000;
 257
 258         /*
 259          * frequency depends on PLL configuration:
 260          */
 261         if (BCMCPU_IS_6348()) {
 262                 /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
 263                 tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
 264                 n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
 265                 n2 = (tmp & MIPSPLLCTL_N2_MASK) >> MIPSPLLCTL_N2_SHIFT;
 266                 m1 = (tmp & MIPSPLLCTL_M1CPU_MASK) >> MIPSPLLCTL_M1CPU_SHIFT;
 267                 n1 += 1;
 268                 n2 += 2;
 269                 m1 += 1;
 270         }
 271
 272         if (BCMCPU_IS_6358()) {
 273                 /* 16MHz * N1 * N2 / M1_CPU */
 274                 tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
 275                 n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
 276                 n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
 277                 m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
 278         }
 279
 280         return (16 * 1000000 * n1 * n2) / m1;
 281 }
 282
 283 /*
 284  * attempt to detect the amount of memory installed
 285  */
 286 static unsigned int detect_memory_size(void)
 287 {
 288         unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
 289         u32 val;
 290
 291         if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
 292                 val = bcm_sdram_readl(SDRAM_CFG_REG);
 293                 rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
 294                 cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
 295                 is_32bits = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
 296                 banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
 297         }
 298
 299         if (BCMCPU_IS_6358()) {
 300                 val = bcm_memc_readl(MEMC_CFG_REG);
 301                 rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
 302                 cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
 303                 is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
 304                 banks = 2;
 305         }
 306
 307         /* 0 => 11 address bits ... 2 => 13 address bits */
 308         rows += 11;
 309
 310         /* 0 => 8 address bits ... 2 => 10 address bits */
 311         cols += 8;
 312
 313         return 1 << (cols + rows + (is_32bits + 1) + banks);
 314 }
 315
 316 void __init bcm63xx_cpu_init(void)
 317 {
 318         unsigned int tmp, expected_cpu_id;
 319         struct cpuinfo_mips *c = &current_cpu_data;
 320
 321         /* soc registers location depends on cpu type */
 322         expected_cpu_id = 0;
 323
 324         switch (c->cputype) {
 325         case CPU_BCM3302:
 326                 expected_cpu_id = BCM6338_CPU_ID;
 327                 bcm63xx_regs_base = bcm96338_regs_base;
 328                 bcm63xx_irqs = bcm96338_irqs;
 329                 bcm63xx_regs_spi = bcm96338_regs_spi;
 330                 break;
 331         case CPU_BCM6345:
 332                 expected_cpu_id = BCM6345_CPU_ID;
 333                 bcm63xx_regs_base = bcm96345_regs_base;
 334                 bcm63xx_irqs = bcm96345_irqs;
 335                 break;
 336         case CPU_BCM6348:
 337                 expected_cpu_id = BCM6348_CPU_ID;
 338                 bcm63xx_regs_base = bcm96348_regs_base;
 339                 bcm63xx_irqs = bcm96348_irqs;
 340                 bcm63xx_regs_spi = bcm96348_regs_spi;
 341                 break;
 342         case CPU_BCM6358:
 343                 expected_cpu_id = BCM6358_CPU_ID;
 344                 bcm63xx_regs_base = bcm96358_regs_base;
 345                 bcm63xx_irqs = bcm96358_irqs;
 346                 bcm63xx_regs_spi = bcm96358_regs_spi;
 347                 break;
 348         }
 349
 350         /* really early to panic, but delaying panic would not help
 351          * since we will never get any working console */
 352         if (!expected_cpu_id)
 353                 panic("unsupported Broadcom CPU");
 354
 355         /*
 356          * bcm63xx_regs_base is set, we can access soc registers
 357          */
 358
 359         /* double check CPU type */
 360         tmp = bcm_perf_readl(PERF_REV_REG);
 361         bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
 362         bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
 363
 364         if (bcm63xx_cpu_id != expected_cpu_id)
 365                 panic("bcm63xx CPU id mismatch");
 366
 367         bcm63xx_cpu_freq = detect_cpu_clock();
 368         bcm63xx_memory_size = detect_memory_size();
 369
 370         printk(KERN_INFO "Detected Broadcom 0x%04x CPU revision %02x\n",
 371                bcm63xx_cpu_id, bcm63xx_cpu_rev);
 372         printk(KERN_INFO "CPU frequency is %u Hz\n",
 373                bcm63xx_cpu_freq);
 374         printk(KERN_INFO "%uMB of RAM installed\n",
 375                bcm63xx_memory_size >> 20);
 376 }