2 * Platform driver for the Realtek RTL8366S ethernet switch
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/rtl8366rb.h>
21 #include "rtl8366_smi.h"
23 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
24 #include <linux/debugfs.h>
27 #define RTL8366S_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
28 #define RTL8366S_DRIVER_VER "0.2.2"
30 #define RTL8366S_PHY_NO_MAX 4
31 #define RTL8366S_PHY_PAGE_MAX 7
32 #define RTL8366S_PHY_ADDR_MAX 31
34 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
35 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
36 #define RTL8366_CHIP_CTRL_VLAN_4KTB (1 << 14)
38 #define RTL8366_RESET_CTRL_REG 0x0100
39 #define RTL8366_CHIP_CTRL_RESET_HW 1
40 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
42 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x050A
43 #define RTL8366S_CHIP_VERSION_MASK 0xf
44 #define RTL8366S_CHIP_ID_REG 0x0509
45 #define RTL8366S_CHIP_ID_8366 0x5937
47 /* PHY registers control */
48 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8000
49 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8002
51 #define RTL8366S_PHY_CTRL_READ 1
52 #define RTL8366S_PHY_CTRL_WRITE 0
54 #define RTL8366S_PHY_REG_MASK 0x1f
55 #define RTL8366S_PHY_PAGE_OFFSET 5
56 #define RTL8366S_PHY_PAGE_MASK (0xf << 5)
57 #define RTL8366S_PHY_NO_OFFSET 9
58 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
60 /* LED control registers */
61 #define RTL8366_LED_BLINKRATE_REG 0x0430
62 #define RTL8366_LED_BLINKRATE_BIT 0
63 #define RTL8366_LED_BLINKRATE_MASK 0x0007
65 #define RTL8366_LED_CTRL_REG 0x0431
66 #define RTL8366_LED_0_1_CTRL_REG 0x0432
67 #define RTL8366_LED_2_3_CTRL_REG 0x0433
69 #define RTL8366S_MIB_COUNT 33
70 #define RTL8366S_GLOBAL_MIB_COUNT 1
71 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0050
72 #define RTL8366S_MIB_COUNTER_BASE 0x1000
73 #define RTL8366S_MIB_CTRL_REG 0x13F0
74 #define RTL8366S_MIB_CTRL_USER_MASK 0x0FFC
75 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
76 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0001
78 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
79 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
80 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
83 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0063
84 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
85 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
86 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
87 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
90 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018C
91 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
94 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
95 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
96 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
98 #define RTL8366S_VLAN_MEMCONF_BASE 0x0020
101 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0014
102 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
103 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
104 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
105 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
106 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
107 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
110 #define RTL8366_PORT_NUM_CPU 5
111 #define RTL8366_NUM_PORTS 6
112 #define RTL8366_NUM_VLANS 16
113 #define RTL8366_NUM_LEDGROUPS 4
114 #define RTL8366_NUM_VIDS 4096
115 #define RTL8366S_PRIORITYMAX 7
116 #define RTL8366S_FIDMAX 7
119 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
120 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
121 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
122 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
123 #define RTL8366_PORT_5 (1 << 4) /* In userspace port 4 */
125 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
127 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
134 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
140 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
145 #define RTL8366_PORT_ALL_INTERNAL RTL8366_PORT_CPU
148 struct device
*parent
;
149 struct rtl8366_smi smi
;
150 struct switch_dev dev
;
152 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
153 struct dentry
*debugfs_root
;
157 struct rtl8366rb_vlan_mc
{
169 struct rtl8366rb_vlan_4k
{
178 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
188 static struct mib_counter rtl8366rb_mib_counters
[RTL8366S_MIB_COUNT
] = {
189 { 0, 4, "IfInOctets " },
190 { 4, 4, "EtherStatsOctets " },
191 { 8, 2, "EtherStatsUnderSizePkts " },
192 { 10, 2, "EtherFregament " },
193 { 12, 2, "EtherStatsPkts64Octets " },
194 { 14, 2, "EtherStatsPkts65to127Octets " },
195 { 16, 2, "EtherStatsPkts128to255Octets " },
196 { 18, 2, "EtherStatsPkts256to511Octets " },
197 { 20, 2, "EtherStatsPkts512to1023Octets " },
198 { 22, 2, "EtherStatsPkts1024to1518Octets " },
199 { 24, 2, "EtherOversizeStats " },
200 { 26, 2, "EtherStatsJabbers " },
201 { 28, 2, "IfInUcastPkts " },
202 { 30, 2, "EtherStatsMulticastPkts " },
203 { 32, 2, "EtherStatsBroadcastPkts " },
204 { 34, 2, "EtherStatsDropEvents " },
205 { 36, 2, "Dot3StatsFCSErrors " },
206 { 38, 2, "Dot3StatsSymbolErrors " },
207 { 40, 2, "Dot3InPauseFrames " },
208 { 42, 2, "Dot3ControlInUnknownOpcodes " },
209 { 44, 4, "IfOutOctets " },
210 { 48, 2, "Dot3StatsSingleCollisionFrames " },
211 { 50, 2, "Dot3StatMultipleCollisionFrames " },
212 { 52, 2, "Dot3sDeferredTransmissions " },
213 { 54, 2, "Dot3StatsLateCollisions " },
214 { 56, 2, "EtherStatsCollisions " },
215 { 58, 2, "Dot3StatsExcessiveCollisions " },
216 { 60, 2, "Dot3OutPauseFrames " },
217 { 62, 2, "Dot1dBasePortDelayExceededDiscards" },
218 { 64, 2, "Dot1dTpPortInDiscards " },
219 { 66, 2, "IfOutUcastPkts " },
220 { 68, 2, "IfOutMulticastPkts " },
221 { 70, 2, "IfOutBroadcastPkts " },
224 static inline struct rtl8366rb
*smi_to_rtl8366rb(struct rtl8366_smi
*smi
)
226 return container_of(smi
, struct rtl8366rb
, smi
);
229 static inline struct rtl8366rb
*sw_to_rtl8366rb(struct switch_dev
*sw
)
231 return container_of(sw
, struct rtl8366rb
, dev
);
234 static int rtl8366rb_reset_chip(struct rtl8366rb
*rtl
)
236 struct rtl8366_smi
*smi
= &rtl
->smi
;
240 rtl8366_smi_write_reg(smi
, RTL8366_RESET_CTRL_REG
,
241 RTL8366_CHIP_CTRL_RESET_HW
);
244 if (rtl8366_smi_read_reg(smi
, RTL8366_RESET_CTRL_REG
, &data
))
247 if (!(data
& RTL8366_CHIP_CTRL_RESET_HW
))
252 printk("Timeout waiting for the switch to reset\n");
259 static int rtl8366rb_read_phy_reg(struct rtl8366_smi
*smi
,
260 u32 phy_no
, u32 page
, u32 addr
, u32
*data
)
265 if (phy_no
> RTL8366S_PHY_NO_MAX
)
268 if (page
> RTL8366S_PHY_PAGE_MAX
)
271 if (addr
> RTL8366S_PHY_ADDR_MAX
)
274 ret
= rtl8366_smi_write_reg(smi
, RTL8366S_PHY_ACCESS_CTRL_REG
,
275 RTL8366S_PHY_CTRL_READ
);
279 reg
= 0x8000 | (1 << (phy_no
+ RTL8366S_PHY_NO_OFFSET
)) |
280 ((page
<< RTL8366S_PHY_PAGE_OFFSET
) & RTL8366S_PHY_PAGE_MASK
) |
281 (addr
& RTL8366S_PHY_REG_MASK
);
283 ret
= rtl8366_smi_write_reg(smi
, reg
, 0);
287 ret
= rtl8366_smi_read_reg(smi
, RTL8366S_PHY_ACCESS_DATA_REG
, data
);
294 static int rtl8366rb_write_phy_reg(struct rtl8366_smi
*smi
,
295 u32 phy_no
, u32 page
, u32 addr
, u32 data
)
300 if (phy_no
> RTL8366S_PHY_NO_MAX
)
303 if (page
> RTL8366S_PHY_PAGE_MAX
)
306 if (addr
> RTL8366S_PHY_ADDR_MAX
)
309 ret
= rtl8366_smi_write_reg(smi
, RTL8366S_PHY_ACCESS_CTRL_REG
,
310 RTL8366S_PHY_CTRL_WRITE
);
314 reg
= 0x8000 | (1 << (phy_no
+ RTL8366S_PHY_NO_OFFSET
)) |
315 ((page
<< RTL8366S_PHY_PAGE_OFFSET
) & RTL8366S_PHY_PAGE_MASK
) |
316 (addr
& RTL8366S_PHY_REG_MASK
);
318 ret
= rtl8366_smi_write_reg(smi
, reg
, data
);
325 static int rtl8366_get_mib_counter(struct rtl8366rb
*rtl
, int counter
,
326 int port
, unsigned long long *val
)
328 struct rtl8366_smi
*smi
= &rtl
->smi
;
334 if (port
> RTL8366_NUM_PORTS
|| counter
>= RTL8366S_MIB_COUNT
)
337 addr
= RTL8366S_MIB_COUNTER_BASE
+
338 RTL8366S_MIB_COUNTER_PORT_OFFSET
* (port
) +
339 rtl8366rb_mib_counters
[counter
].offset
;
342 * Writing access counter address first
343 * then ASIC will prepare 64bits counter wait for being retrived
345 data
= 0; /* writing data will be discard by ASIC */
346 err
= rtl8366_smi_write_reg(smi
, addr
, data
);
350 /* read MIB control register */
351 err
= rtl8366_smi_read_reg(smi
, RTL8366S_MIB_CTRL_REG
, &data
);
355 if (data
& RTL8366S_MIB_CTRL_BUSY_MASK
)
358 if (data
& RTL8366S_MIB_CTRL_RESET_MASK
)
362 for (i
= rtl8366rb_mib_counters
[counter
].length
; i
> 0; i
--) {
363 err
= rtl8366_smi_read_reg(smi
, addr
+ (i
- 1), &data
);
367 mibvalue
= (mibvalue
<< 16) | (data
& 0xFFFF);
374 static int rtl8366rb_get_vlan_4k(struct rtl8366rb
*rtl
, u32 vid
,
375 struct rtl8366_vlan_4k
*vlan4k
)
377 struct rtl8366_smi
*smi
= &rtl
->smi
;
378 struct rtl8366rb_vlan_4k vlan4k_priv
;
383 memset(vlan4k
, '\0', sizeof(struct rtl8366_vlan_4k
));
384 vlan4k_priv
.vid
= vid
;
386 if (vid
>= RTL8366_NUM_VIDS
)
389 tableaddr
= (u16
*)&vlan4k_priv
;
393 err
= rtl8366_smi_write_reg(smi
, RTL8366S_VLAN_TABLE_WRITE_BASE
, data
);
397 /* write table access control word */
398 err
= rtl8366_smi_write_reg(smi
, RTL8366S_TABLE_ACCESS_CTRL_REG
,
399 RTL8366S_TABLE_VLAN_READ_CTRL
);
403 err
= rtl8366_smi_read_reg(smi
, RTL8366S_VLAN_TABLE_READ_BASE
, &data
);
410 err
= rtl8366_smi_read_reg(smi
, RTL8366S_VLAN_TABLE_READ_BASE
+ 1,
418 err
= rtl8366_smi_read_reg(smi
, RTL8366S_VLAN_TABLE_READ_BASE
+ 2,
425 vlan4k
->untag
= vlan4k_priv
.untag
;
426 vlan4k
->member
= vlan4k_priv
.member
;
427 vlan4k
->fid
= vlan4k_priv
.fid
;
432 static int rtl8366rb_set_vlan_4k(struct rtl8366rb
*rtl
,
433 const struct rtl8366_vlan_4k
*vlan4k
)
435 struct rtl8366_smi
*smi
= &rtl
->smi
;
436 struct rtl8366rb_vlan_4k vlan4k_priv
;
441 if (vlan4k
->vid
>= RTL8366_NUM_VIDS
||
442 vlan4k
->member
> RTL8366_PORT_ALL
||
443 vlan4k
->untag
> RTL8366_PORT_ALL
||
444 vlan4k
->fid
> RTL8366S_FIDMAX
)
447 vlan4k_priv
.vid
= vlan4k
->vid
;
448 vlan4k_priv
.untag
= vlan4k
->untag
;
449 vlan4k_priv
.member
= vlan4k
->member
;
450 vlan4k_priv
.fid
= vlan4k
->fid
;
452 tableaddr
= (u16
*)&vlan4k_priv
;
456 err
= rtl8366_smi_write_reg(smi
, RTL8366S_VLAN_TABLE_WRITE_BASE
, data
);
464 err
= rtl8366_smi_write_reg(smi
, RTL8366S_VLAN_TABLE_WRITE_BASE
+ 1,
473 err
= rtl8366_smi_write_reg(smi
, RTL8366S_VLAN_TABLE_WRITE_BASE
+ 2,
478 /* write table access control word */
479 err
= rtl8366_smi_write_reg(smi
, RTL8366S_TABLE_ACCESS_CTRL_REG
,
480 RTL8366S_TABLE_VLAN_WRITE_CTRL
);
485 static int rtl8366rb_get_vlan_mc(struct rtl8366rb
*rtl
, u32 index
,
486 struct rtl8366_vlan_mc
*vlanmc
)
488 struct rtl8366_smi
*smi
= &rtl
->smi
;
489 struct rtl8366rb_vlan_mc vlanmc_priv
;
495 memset(vlanmc
, '\0', sizeof(struct rtl8366_vlan_mc
));
497 if (index
>= RTL8366_NUM_VLANS
)
500 tableaddr
= (u16
*)&vlanmc_priv
;
502 addr
= RTL8366S_VLAN_MEMCONF_BASE
+ (index
* 3);
503 err
= rtl8366_smi_read_reg(smi
, addr
, &data
);
510 addr
= RTL8366S_VLAN_MEMCONF_BASE
+ 1 + (index
* 3);
511 err
= rtl8366_smi_read_reg(smi
, addr
, &data
);
518 addr
= RTL8366S_VLAN_MEMCONF_BASE
+ 2 + (index
* 3);
519 err
= rtl8366_smi_read_reg(smi
, addr
, &data
);
525 vlanmc
->vid
= vlanmc_priv
.vid
;
526 vlanmc
->priority
= vlanmc_priv
.priority
;
527 vlanmc
->untag
= vlanmc_priv
.untag
;
528 vlanmc
->member
= vlanmc_priv
.member
;
529 vlanmc
->fid
= vlanmc_priv
.fid
;
534 static int rtl8366rb_set_vlan_mc(struct rtl8366rb
*rtl
, u32 index
,
535 const struct rtl8366_vlan_mc
*vlanmc
)
537 struct rtl8366_smi
*smi
= &rtl
->smi
;
538 struct rtl8366rb_vlan_mc vlanmc_priv
;
544 if (index
>= RTL8366_NUM_VLANS
||
545 vlanmc
->vid
>= RTL8366_NUM_VIDS
||
546 vlanmc
->priority
> RTL8366S_PRIORITYMAX
||
547 vlanmc
->member
> RTL8366_PORT_ALL
||
548 vlanmc
->untag
> RTL8366_PORT_ALL
||
549 vlanmc
->fid
> RTL8366S_FIDMAX
)
552 vlanmc_priv
.vid
= vlanmc
->vid
;
553 vlanmc_priv
.priority
= vlanmc
->priority
;
554 vlanmc_priv
.untag
= vlanmc
->untag
;
555 vlanmc_priv
.member
= vlanmc
->member
;
556 vlanmc_priv
.stag_mbr
= 0;
557 vlanmc_priv
.stag_idx
= 0;
558 vlanmc_priv
.fid
= vlanmc
->fid
;
560 addr
= RTL8366S_VLAN_MEMCONF_BASE
+ (index
* 3);
562 tableaddr
= (u16
*)&vlanmc_priv
;
565 err
= rtl8366_smi_write_reg(smi
, addr
, data
);
569 addr
= RTL8366S_VLAN_MEMCONF_BASE
+ 1 + (index
* 3);
574 err
= rtl8366_smi_write_reg(smi
, addr
, data
);
578 addr
= RTL8366S_VLAN_MEMCONF_BASE
+ 2 + (index
* 3);
583 err
= rtl8366_smi_write_reg(smi
, addr
, data
);
589 static int rtl8366rb_get_port_vlan_index(struct rtl8366rb
*rtl
, int port
,
592 struct rtl8366_smi
*smi
= &rtl
->smi
;
596 if (port
>= RTL8366_NUM_PORTS
)
599 err
= rtl8366_smi_read_reg(smi
, RTL8366S_PORT_VLAN_CTRL_REG(port
),
604 *val
= (data
>> RTL8366S_PORT_VLAN_CTRL_SHIFT(port
)) &
605 RTL8366S_PORT_VLAN_CTRL_MASK
;
611 static int rtl8366rb_get_vlan_port_pvid(struct rtl8366rb
*rtl
, int port
,
614 struct rtl8366_vlan_mc vlanmc
;
618 err
= rtl8366rb_get_port_vlan_index(rtl
, port
, &index
);
622 err
= rtl8366rb_get_vlan_mc(rtl
, index
, &vlanmc
);
630 static int rtl8366rb_set_port_vlan_index(struct rtl8366rb
*rtl
, int port
,
633 struct rtl8366_smi
*smi
= &rtl
->smi
;
637 if (port
>= RTL8366_NUM_PORTS
|| index
>= RTL8366_NUM_VLANS
)
640 err
= rtl8366_smi_read_reg(smi
, RTL8366S_PORT_VLAN_CTRL_REG(port
),
645 data
&= ~(RTL8366S_PORT_VLAN_CTRL_MASK
<<
646 RTL8366S_PORT_VLAN_CTRL_SHIFT(port
));
647 data
|= (index
& RTL8366S_PORT_VLAN_CTRL_MASK
) <<
648 RTL8366S_PORT_VLAN_CTRL_SHIFT(port
);
650 err
= rtl8366_smi_write_reg(smi
, RTL8366S_PORT_VLAN_CTRL_REG(port
),
655 static int rtl8366rb_set_vlan_port_pvid(struct rtl8366rb
*rtl
, int port
, int val
)
658 struct rtl8366_vlan_mc vlanmc
;
659 struct rtl8366_vlan_4k vlan4k
;
661 if (port
>= RTL8366_NUM_PORTS
|| val
>= RTL8366_NUM_VIDS
)
664 /* Updating the 4K entry; lookup it and change the port member set */
665 rtl8366rb_get_vlan_4k(rtl
, val
, &vlan4k
);
666 vlan4k
.member
|= ((1 << port
) | RTL8366_PORT_CPU
);
667 vlan4k
.untag
= RTL8366_PORT_ALL_BUT_CPU
;
668 rtl8366rb_set_vlan_4k(rtl
, &vlan4k
);
671 * For the 16 entries more work needs to be done. First see if such
672 * VID is already there and change it
674 for (i
= 0; i
< RTL8366_NUM_VLANS
; ++i
) {
675 rtl8366rb_get_vlan_mc(rtl
, i
, &vlanmc
);
677 /* Try to find an existing vid and update port member set */
678 if (val
== vlanmc
.vid
) {
679 vlanmc
.member
|= ((1 << port
) | RTL8366_PORT_CPU
);
680 rtl8366rb_set_vlan_mc(rtl
, i
, &vlanmc
);
682 /* Now update PVID register settings */
683 rtl8366rb_set_port_vlan_index(rtl
, port
, i
);
690 * PVID could not be found from vlan table. Replace unused (one that
691 * has no member ports) with new one
693 for (i
= 0; i
< RTL8366_NUM_VLANS
; ++i
) {
694 rtl8366rb_get_vlan_mc(rtl
, i
, &vlanmc
);
697 * See if this vlan member configuration is unused. It is
698 * unused if member set contains no ports or CPU port only
700 if (!vlanmc
.member
|| vlanmc
.member
== RTL8366_PORT_CPU
) {
703 vlanmc
.untag
= RTL8366_PORT_ALL_BUT_CPU
;
704 vlanmc
.member
= ((1 << port
) | RTL8366_PORT_CPU
);
707 rtl8366rb_set_vlan_mc(rtl
, i
, &vlanmc
);
709 /* Now update PVID register settings */
710 rtl8366rb_set_port_vlan_index(rtl
, port
, i
);
717 "All 16 vlan member configurations are in use\n");
723 static int rtl8366rb_vlan_set_vlan(struct rtl8366rb
*rtl
, int enable
)
725 struct rtl8366_smi
*smi
= &rtl
->smi
;
728 rtl8366_smi_read_reg(smi
, RTL8366_CHIP_GLOBAL_CTRL_REG
, &data
);
731 data
|= RTL8366_CHIP_CTRL_VLAN
;
733 data
&= ~RTL8366_CHIP_CTRL_VLAN
;
735 return rtl8366_smi_write_reg(smi
, RTL8366_CHIP_GLOBAL_CTRL_REG
, data
);
738 static int rtl8366rb_vlan_set_4ktable(struct rtl8366rb
*rtl
, int enable
)
740 struct rtl8366_smi
*smi
= &rtl
->smi
;
743 rtl8366_smi_read_reg(smi
, RTL8366_CHIP_GLOBAL_CTRL_REG
, &data
);
746 data
|= RTL8366_CHIP_CTRL_VLAN_4KTB
;
748 data
&= ~RTL8366_CHIP_CTRL_VLAN_4KTB
;
750 return rtl8366_smi_write_reg(smi
, RTL8366_CHIP_GLOBAL_CTRL_REG
, data
);
753 static int rtl8366rb_reset_vlan(struct rtl8366rb
*rtl
)
755 struct rtl8366_vlan_4k vlan4k
;
756 struct rtl8366_vlan_mc vlanmc
;
760 /* clear 16 VLAN member configuration */
766 for (i
= 0; i
< RTL8366_NUM_VLANS
; i
++) {
767 err
= rtl8366rb_set_vlan_mc(rtl
, i
, &vlanmc
);
772 /* Set a default VLAN with vid 1 to 4K table for all ports */
774 vlan4k
.member
= RTL8366_PORT_ALL
;
775 vlan4k
.untag
= RTL8366_PORT_ALL
;
777 err
= rtl8366rb_set_vlan_4k(rtl
, &vlan4k
);
781 /* Set all ports PVID to default VLAN */
782 for (i
= 0; i
< RTL8366_NUM_PORTS
; i
++) {
783 err
= rtl8366rb_set_vlan_port_pvid(rtl
, i
, 0);
791 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
792 static int rtl8366rb_debugfs_open(struct inode
*inode
, struct file
*file
)
794 file
->private_data
= inode
->i_private
;
798 static ssize_t
rtl8366rb_read_debugfs_mibs(struct file
*file
,
799 char __user
*user_buf
,
800 size_t count
, loff_t
*ppos
)
802 struct rtl8366rb
*rtl
= (struct rtl8366rb
*)file
->private_data
;
804 char *buf
= rtl
->buf
;
806 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "MIB Counters:\n");
807 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "Counter"
809 "Port 0 \t\t Port 1 \t\t Port 2 \t\t Port 3 \t\t "
812 for (i
= 0; i
< 33; ++i
) {
813 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "%d:%s ",
814 i
, rtl8366rb_mib_counters
[i
].name
);
815 for (j
= 0; j
< RTL8366_NUM_PORTS
; ++j
) {
816 unsigned long long counter
= 0;
818 if (!rtl8366_get_mib_counter(rtl
, i
, j
, &counter
))
819 len
+= snprintf(buf
+ len
,
820 sizeof(rtl
->buf
) - len
,
823 len
+= snprintf(buf
+ len
,
824 sizeof(rtl
->buf
) - len
,
827 if (j
!= RTL8366_NUM_PORTS
- 1) {
828 if (counter
< 100000)
829 len
+= snprintf(buf
+ len
,
830 sizeof(rtl
->buf
) - len
,
833 len
+= snprintf(buf
+ len
,
834 sizeof(rtl
->buf
) - len
,
838 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "\n");
841 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "\n");
843 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, len
);
846 static ssize_t
rtl8366rb_read_debugfs_vlan(struct file
*file
,
847 char __user
*user_buf
,
848 size_t count
, loff_t
*ppos
)
850 struct rtl8366rb
*rtl
= (struct rtl8366rb
*)file
->private_data
;
852 char *buf
= rtl
->buf
;
854 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
855 "VLAN Member Config:\n");
856 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
857 "\t id \t vid \t prio \t member \t untag \t fid "
860 for (i
= 0; i
< RTL8366_NUM_VLANS
; ++i
) {
861 struct rtl8366_vlan_mc vlanmc
;
863 rtl8366rb_get_vlan_mc(rtl
, i
, &vlanmc
);
865 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
866 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
867 "\t", i
, vlanmc
.vid
, vlanmc
.priority
,
868 vlanmc
.member
, vlanmc
.untag
, vlanmc
.fid
);
870 for (j
= 0; j
< RTL8366_NUM_PORTS
; ++j
) {
872 if (!rtl8366rb_get_port_vlan_index(rtl
, j
, &index
)) {
874 len
+= snprintf(buf
+ len
,
875 sizeof(rtl
->buf
) - len
,
879 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "\n");
882 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, len
);
885 static ssize_t
rtl8366rb_read_debugfs_reg(struct file
*file
,
886 char __user
*user_buf
,
887 size_t count
, loff_t
*ppos
)
889 struct rtl8366rb
*rtl
= (struct rtl8366rb
*)file
->private_data
;
890 struct rtl8366_smi
*smi
= &rtl
->smi
;
891 u32 t
, reg
= gl_dbg_reg
;
893 char *buf
= rtl
->buf
;
895 memset(buf
, '\0', sizeof(rtl
->buf
));
897 err
= rtl8366_smi_read_reg(smi
, reg
, &t
);
899 len
+= snprintf(buf
, sizeof(rtl
->buf
),
900 "Read failed (reg: 0x%04x)\n", reg
);
901 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, len
);
904 len
+= snprintf(buf
, sizeof(rtl
->buf
), "reg = 0x%04x, val = 0x%04x\n",
907 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, len
);
910 static ssize_t
rtl8366rb_write_debugfs_reg(struct file
*file
,
911 const char __user
*user_buf
,
912 size_t count
, loff_t
*ppos
)
914 struct rtl8366rb
*rtl
= (struct rtl8366rb
*)file
->private_data
;
915 struct rtl8366_smi
*smi
= &rtl
->smi
;
917 u32 reg
= gl_dbg_reg
;
920 char *buf
= rtl
->buf
;
922 len
= min(count
, sizeof(rtl
->buf
) - 1);
923 if (copy_from_user(buf
, user_buf
, len
)) {
924 dev_err(rtl
->parent
, "copy from user failed\n");
929 if (len
> 0 && buf
[len
- 1] == '\n')
933 if (strict_strtoul(buf
, 16, &data
)) {
934 dev_err(rtl
->parent
, "Invalid reg value %s\n", buf
);
936 err
= rtl8366_smi_write_reg(smi
, reg
, data
);
939 "writing reg 0x%04x val 0x%04lx failed\n",
947 static const struct file_operations fops_rtl8366rb_regs
= {
948 .read
= rtl8366rb_read_debugfs_reg
,
949 .write
= rtl8366rb_write_debugfs_reg
,
950 .open
= rtl8366rb_debugfs_open
,
954 static const struct file_operations fops_rtl8366rb_vlan
= {
955 .read
= rtl8366rb_read_debugfs_vlan
,
956 .open
= rtl8366rb_debugfs_open
,
960 static const struct file_operations fops_rtl8366rb_mibs
= {
961 .read
= rtl8366rb_read_debugfs_mibs
,
962 .open
= rtl8366rb_debugfs_open
,
966 static void rtl8366rb_debugfs_init(struct rtl8366rb
*rtl
)
971 if (!rtl
->debugfs_root
)
972 rtl
->debugfs_root
= debugfs_create_dir("rtl8366rb", NULL
);
974 if (!rtl
->debugfs_root
) {
975 dev_err(rtl
->parent
, "Unable to create debugfs dir\n");
978 root
= rtl
->debugfs_root
;
980 node
= debugfs_create_x16("reg", S_IRUGO
| S_IWUSR
, root
, &gl_dbg_reg
);
982 dev_err(rtl
->parent
, "Creating debugfs file '%s' failed\n",
987 node
= debugfs_create_file("val", S_IRUGO
| S_IWUSR
, root
, rtl
,
988 &fops_rtl8366rb_regs
);
990 dev_err(rtl
->parent
, "Creating debugfs file '%s' failed\n",
995 node
= debugfs_create_file("vlan", S_IRUSR
, root
, rtl
,
996 &fops_rtl8366rb_vlan
);
998 dev_err(rtl
->parent
, "Creating debugfs file '%s' failed\n",
1003 node
= debugfs_create_file("mibs", S_IRUSR
, root
, rtl
,
1004 &fops_rtl8366rb_mibs
);
1006 dev_err(rtl
->parent
, "Creating debugfs file '%s' failed\n",
1012 static void rtl8366rb_debugfs_remove(struct rtl8366rb
*rtl
)
1014 if (rtl
->debugfs_root
) {
1015 debugfs_remove_recursive(rtl
->debugfs_root
);
1016 rtl
->debugfs_root
= NULL
;
1021 static inline void rtl8366rb_debugfs_init(struct rtl8366rb
*rtl
) {}
1022 static inline void rtl8366rb_debugfs_remove(struct rtl8366rb
*rtl
) {}
1023 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
1025 static int rtl8366rb_sw_reset_mibs(struct switch_dev
*dev
,
1026 const struct switch_attr
*attr
,
1027 struct switch_val
*val
)
1029 struct rtl8366rb
*rtl
= sw_to_rtl8366rb(dev
);
1030 struct rtl8366_smi
*smi
= &rtl
->smi
;
1033 if (val
->value
.i
== 1) {
1034 rtl8366_smi_read_reg(smi
, RTL8366S_MIB_CTRL_REG
, &data
);
1036 rtl8366_smi_write_reg(smi
, RTL8366S_MIB_CTRL_REG
, data
);
1042 static int rtl8366rb_sw_get_vlan_enable(struct switch_dev
*dev
,
1043 const struct switch_attr
*attr
,
1044 struct switch_val
*val
)
1046 struct rtl8366rb
*rtl
= sw_to_rtl8366rb(dev
);
1047 struct rtl8366_smi
*smi
= &rtl
->smi
;
1050 if (attr
->ofs
== 1) {
1051 rtl8366_smi_read_reg(smi
, RTL8366_CHIP_GLOBAL_CTRL_REG
, &data
);
1053 if (data
& RTL8366_CHIP_CTRL_VLAN
)
1057 } else if (attr
->ofs
== 2) {
1058 rtl8366_smi_read_reg(smi
, RTL8366_CHIP_GLOBAL_CTRL_REG
, &data
);
1060 if (data
& RTL8366_CHIP_CTRL_VLAN_4KTB
)
1069 static int rtl8366rb_sw_get_blinkrate(struct switch_dev
*dev
,
1070 const struct switch_attr
*attr
,
1071 struct switch_val
*val
)
1073 struct rtl8366rb
*rtl
= sw_to_rtl8366rb(dev
);
1074 struct rtl8366_smi
*smi
= &rtl
->smi
;
1077 rtl8366_smi_read_reg(smi
, RTL8366_LED_BLINKRATE_REG
, &data
);
1079 val
->value
.i
= (data
& (RTL8366_LED_BLINKRATE_MASK
));
1084 static int rtl8366rb_sw_set_blinkrate(struct switch_dev
*dev
,
1085 const struct switch_attr
*attr
,
1086 struct switch_val
*val
)
1088 struct rtl8366rb
*rtl
= sw_to_rtl8366rb(dev
);
1089 struct rtl8366_smi
*smi
= &rtl
->smi
;
1092 if (val
->value
.i
>= 6)
1095 rtl8366_smi_read_reg(smi
, RTL8366_LED_BLINKRATE_REG
, &data
);
1097 data
&= ~RTL8366_LED_BLINKRATE_MASK
;
1098 data
|= val
->value
.i
;
1100 rtl8366_smi_write_reg(smi
, RTL8366_LED_BLINKRATE_REG
, data
);
1105 static int rtl8366rb_sw_set_vlan_enable(struct switch_dev
*dev
,
1106 const struct switch_attr
*attr
,
1107 struct switch_val
*val
)
1109 struct rtl8366rb
*rtl
= sw_to_rtl8366rb(dev
);
1112 return rtl8366rb_vlan_set_vlan(rtl
, val
->value
.i
);
1114 return rtl8366rb_vlan_set_4ktable(rtl
, val
->value
.i
);
1117 static const char *rtl8366rb_speed_str(unsigned speed
)
1131 static int rtl8366rb_sw_get_port_link(struct switch_dev
*dev
,
1132 const struct switch_attr
*attr
,
1133 struct switch_val
*val
)
1135 struct rtl8366rb
*rtl
= sw_to_rtl8366rb(dev
);
1136 struct rtl8366_smi
*smi
= &rtl
->smi
;
1137 u32 len
= 0, data
= 0;
1139 if (val
->port_vlan
>= RTL8366_NUM_PORTS
)
1142 memset(rtl
->buf
, '\0', sizeof(rtl
->buf
));
1143 rtl8366_smi_read_reg(smi
, RTL8366S_PORT_LINK_STATUS_BASE
+
1144 (val
->port_vlan
/ 2), &data
);
1146 if (val
->port_vlan
% 2)
1149 if (data
& RTL8366S_PORT_STATUS_LINK_MASK
) {
1150 len
= snprintf(rtl
->buf
, sizeof(rtl
->buf
),
1151 "port:%d link:up speed:%s %s-duplex %s%s%s",
1153 rtl8366rb_speed_str(data
&
1154 RTL8366S_PORT_STATUS_SPEED_MASK
),
1155 (data
& RTL8366S_PORT_STATUS_DUPLEX_MASK
) ?
1157 (data
& RTL8366S_PORT_STATUS_TXPAUSE_MASK
) ?
1159 (data
& RTL8366S_PORT_STATUS_RXPAUSE_MASK
) ?
1161 (data
& RTL8366S_PORT_STATUS_AN_MASK
) ?
1164 len
= snprintf(rtl
->buf
, sizeof(rtl
->buf
), "port:%d link: down",
1168 val
->value
.s
= rtl
->buf
;
1174 static int rtl8366rb_sw_get_vlan_info(struct switch_dev
*dev
,
1175 const struct switch_attr
*attr
,
1176 struct switch_val
*val
)
1180 struct rtl8366_vlan_mc vlanmc
;
1181 struct rtl8366_vlan_4k vlan4k
;
1182 struct rtl8366rb
*rtl
= sw_to_rtl8366rb(dev
);
1183 char *buf
= rtl
->buf
;
1185 if (val
->port_vlan
== 0 || val
->port_vlan
>= RTL8366_NUM_VLANS
)
1188 memset(buf
, '\0', sizeof(rtl
->buf
));
1190 rtl8366rb_get_vlan_mc(rtl
, val
->port_vlan
, &vlanmc
);
1191 rtl8366rb_get_vlan_4k(rtl
, vlanmc
.vid
, &vlan4k
);
1193 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "VLAN %d: Ports: ",
1196 for (i
= 0; i
< RTL8366_NUM_PORTS
; ++i
) {
1198 if (!rtl8366rb_get_port_vlan_index(rtl
, i
, &index
) &&
1199 index
== val
->port_vlan
)
1200 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1203 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "\n");
1205 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1206 "\t\t vid \t prio \t member \t untag \t fid\n");
1207 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "\tMC:\t");
1208 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1209 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1210 vlanmc
.vid
, vlanmc
.priority
, vlanmc
.member
,
1211 vlanmc
.untag
, vlanmc
.fid
);
1212 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
, "\t4K:\t");
1213 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1214 "%d \t \t 0x%04x \t 0x%04x \t %d",
1215 vlan4k
.vid
, vlan4k
.member
, vlan4k
.untag
, vlan4k
.fid
);
1223 static int rtl8366rb_sw_set_port_led(struct switch_dev
*dev
,
1224 const struct switch_attr
*attr
,
1225 struct switch_val
*val
)
1227 struct rtl8366rb
*rtl
= sw_to_rtl8366rb(dev
);
1228 struct rtl8366_smi
*smi
= &rtl
->smi
;
1231 if (val
->port_vlan
>= RTL8366_NUM_PORTS
)
1234 if (val
->port_vlan
== RTL8366_PORT_NUM_CPU
) {
1235 rtl8366_smi_read_reg(smi
, RTL8366_LED_BLINKRATE_REG
, &data
);
1236 data
= (data
& (~(0xF << 4))) | (val
->value
.i
<< 4);
1237 rtl8366_smi_write_reg(smi
, RTL8366_LED_BLINKRATE_REG
, data
);
1239 rtl8366_smi_read_reg(smi
, RTL8366_LED_CTRL_REG
, &data
);
1240 data
= (data
& (~(0xF << (val
->port_vlan
* 4)))) |
1241 (val
->value
.i
<< (val
->port_vlan
* 4));
1242 rtl8366_smi_write_reg(smi
, RTL8366_LED_CTRL_REG
, data
);
1248 static int rtl8366rb_sw_get_port_led(struct switch_dev
*dev
,
1249 const struct switch_attr
*attr
,
1250 struct switch_val
*val
)
1252 struct rtl8366rb
*rtl
= sw_to_rtl8366rb(dev
);
1253 struct rtl8366_smi
*smi
= &rtl
->smi
;
1256 if (val
->port_vlan
>= RTL8366_NUM_LEDGROUPS
)
1259 rtl8366_smi_read_reg(smi
, RTL8366_LED_CTRL_REG
, &data
);
1260 val
->value
.i
= (data
>> (val
->port_vlan
* 4)) & 0x000F;
1265 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev
*dev
,
1266 const struct switch_attr
*attr
,
1267 struct switch_val
*val
)
1269 struct rtl8366rb
*rtl
= sw_to_rtl8366rb(dev
);
1270 struct rtl8366_smi
*smi
= &rtl
->smi
;
1273 if (val
->port_vlan
>= RTL8366_NUM_PORTS
)
1276 rtl8366_smi_read_reg(smi
, RTL8366S_MIB_CTRL_REG
, &data
);
1277 data
|= (1 << (val
->port_vlan
+ 3));
1278 rtl8366_smi_write_reg(smi
, RTL8366S_MIB_CTRL_REG
, data
);
1283 static int rtl8366rb_sw_get_port_mib(struct switch_dev
*dev
,
1284 const struct switch_attr
*attr
,
1285 struct switch_val
*val
)
1287 struct rtl8366rb
*rtl
= sw_to_rtl8366rb(dev
);
1289 unsigned long long counter
= 0;
1290 char *buf
= rtl
->buf
;
1292 if (val
->port_vlan
>= RTL8366_NUM_PORTS
)
1295 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1296 "Port %d MIB counters\n",
1299 for (i
= 0; i
< RTL8366S_MIB_COUNT
; ++i
) {
1300 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1301 "%d:%s\t", i
, rtl8366rb_mib_counters
[i
].name
);
1302 if (!rtl8366_get_mib_counter(rtl
, i
, val
->port_vlan
, &counter
))
1303 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1304 "[%llu]\n", counter
);
1306 len
+= snprintf(buf
+ len
, sizeof(rtl
->buf
) - len
,
1315 static int rtl8366rb_sw_get_vlan_ports(struct switch_dev
*dev
,
1316 struct switch_val
*val
)
1318 struct rtl8366_vlan_mc vlanmc
;
1319 struct rtl8366rb
*rtl
= sw_to_rtl8366rb(dev
);
1320 struct switch_port
*port
;
1323 if (val
->port_vlan
== 0 || val
->port_vlan
>= RTL8366_NUM_VLANS
)
1326 rtl8366rb_get_vlan_mc(rtl
, val
->port_vlan
, &vlanmc
);
1328 port
= &val
->value
.ports
[0];
1330 for (i
= 0; i
< RTL8366_NUM_PORTS
; i
++) {
1331 if (!(vlanmc
.member
& BIT(i
)))
1335 port
->flags
= (vlanmc
.untag
& BIT(i
)) ?
1336 0 : BIT(SWITCH_PORT_FLAG_TAGGED
);
1343 static int rtl8366rb_sw_set_vlan_ports(struct switch_dev
*dev
,
1344 struct switch_val
*val
)
1346 struct rtl8366_vlan_mc vlanmc
;
1347 struct rtl8366_vlan_4k vlan4k
;
1348 struct rtl8366rb
*rtl
= sw_to_rtl8366rb(dev
);
1349 struct switch_port
*port
;
1352 if (val
->port_vlan
== 0 || val
->port_vlan
>= RTL8366_NUM_VLANS
)
1355 rtl8366rb_get_vlan_mc(rtl
, val
->port_vlan
, &vlanmc
);
1356 rtl8366rb_get_vlan_4k(rtl
, vlanmc
.vid
, &vlan4k
);
1361 port
= &val
->value
.ports
[0];
1362 for (i
= 0; i
< val
->len
; i
++, port
++) {
1363 vlanmc
.member
|= BIT(port
->id
);
1365 if (!(port
->flags
& BIT(SWITCH_PORT_FLAG_TAGGED
)))
1366 vlanmc
.untag
|= BIT(port
->id
);
1369 vlan4k
.member
= vlanmc
.member
;
1370 vlan4k
.untag
= vlanmc
.untag
;
1372 rtl8366rb_set_vlan_mc(rtl
, val
->port_vlan
, &vlanmc
);
1373 rtl8366rb_set_vlan_4k(rtl
, &vlan4k
);
1377 static int rtl8366rb_sw_get_port_pvid(struct switch_dev
*dev
, int port
, int *val
)
1379 struct rtl8366rb
*rtl
= sw_to_rtl8366rb(dev
);
1380 return rtl8366rb_get_vlan_port_pvid(rtl
, port
, val
);
1383 static int rtl8366rb_sw_set_port_pvid(struct switch_dev
*dev
, int port
, int val
)
1385 struct rtl8366rb
*rtl
= sw_to_rtl8366rb(dev
);
1386 return rtl8366rb_set_vlan_port_pvid(rtl
, port
, val
);
1389 static int rtl8366rb_sw_reset_switch(struct switch_dev
*dev
)
1391 struct rtl8366rb
*rtl
= sw_to_rtl8366rb(dev
);
1394 err
= rtl8366rb_reset_chip(rtl
);
1398 return rtl8366rb_reset_vlan(rtl
);
1401 static struct switch_attr rtl8366rb_globals
[] = {
1403 .type
= SWITCH_TYPE_INT
,
1404 .name
= "enable_vlan",
1405 .description
= "Enable VLAN mode",
1406 .set
= rtl8366rb_sw_set_vlan_enable
,
1407 .get
= rtl8366rb_sw_get_vlan_enable
,
1411 .type
= SWITCH_TYPE_INT
,
1412 .name
= "enable_vlan4k",
1413 .description
= "Enable VLAN 4K mode",
1414 .set
= rtl8366rb_sw_set_vlan_enable
,
1415 .get
= rtl8366rb_sw_get_vlan_enable
,
1419 .type
= SWITCH_TYPE_INT
,
1420 .name
= "reset_mibs",
1421 .description
= "Reset all MIB counters",
1422 .set
= rtl8366rb_sw_reset_mibs
,
1426 .type
= SWITCH_TYPE_INT
,
1427 .name
= "blinkrate",
1428 .description
= "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1429 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1430 .set
= rtl8366rb_sw_set_blinkrate
,
1431 .get
= rtl8366rb_sw_get_blinkrate
,
1436 static struct switch_attr rtl8366rb_port
[] = {
1438 .type
= SWITCH_TYPE_STRING
,
1440 .description
= "Get port link information",
1443 .get
= rtl8366rb_sw_get_port_link
,
1445 .type
= SWITCH_TYPE_INT
,
1446 .name
= "reset_mib",
1447 .description
= "Reset single port MIB counters",
1449 .set
= rtl8366rb_sw_reset_port_mibs
,
1452 .type
= SWITCH_TYPE_STRING
,
1454 .description
= "Get MIB counters for port",
1457 .get
= rtl8366rb_sw_get_port_mib
,
1459 .type
= SWITCH_TYPE_INT
,
1461 .description
= "Get/Set port group (0 - 3) led mode (0 - 15)",
1463 .set
= rtl8366rb_sw_set_port_led
,
1464 .get
= rtl8366rb_sw_get_port_led
,
1468 static struct switch_attr rtl8366rb_vlan
[] = {
1470 .type
= SWITCH_TYPE_STRING
,
1472 .description
= "Get vlan information",
1475 .get
= rtl8366rb_sw_get_vlan_info
,
1480 static struct switch_dev rtl8366_switch_dev
= {
1482 .cpu_port
= RTL8366_PORT_NUM_CPU
,
1483 .ports
= RTL8366_NUM_PORTS
,
1484 .vlans
= RTL8366_NUM_VLANS
,
1486 .attr
= rtl8366rb_globals
,
1487 .n_attr
= ARRAY_SIZE(rtl8366rb_globals
),
1490 .attr
= rtl8366rb_port
,
1491 .n_attr
= ARRAY_SIZE(rtl8366rb_port
),
1494 .attr
= rtl8366rb_vlan
,
1495 .n_attr
= ARRAY_SIZE(rtl8366rb_vlan
),
1498 .get_vlan_ports
= rtl8366rb_sw_get_vlan_ports
,
1499 .set_vlan_ports
= rtl8366rb_sw_set_vlan_ports
,
1500 .get_port_pvid
= rtl8366rb_sw_get_port_pvid
,
1501 .set_port_pvid
= rtl8366rb_sw_set_port_pvid
,
1502 .reset_switch
= rtl8366rb_sw_reset_switch
,
1505 static int rtl8366rb_switch_init(struct rtl8366rb
*rtl
)
1507 struct switch_dev
*dev
= &rtl
->dev
;
1510 memcpy(dev
, &rtl8366_switch_dev
, sizeof(struct switch_dev
));
1512 dev
->devname
= dev_name(rtl
->parent
);
1514 err
= register_switch(dev
, NULL
);
1516 dev_err(rtl
->parent
, "switch registration failed\n");
1521 static void rtl8366rb_switch_cleanup(struct rtl8366rb
*rtl
)
1523 unregister_switch(&rtl
->dev
);
1526 static int rtl8366rb_mii_read(struct mii_bus
*bus
, int addr
, int reg
)
1528 struct rtl8366_smi
*smi
= bus
->priv
;
1532 err
= rtl8366rb_read_phy_reg(smi
, addr
, 0, reg
, &val
);
1539 static int rtl8366rb_mii_write(struct mii_bus
*bus
, int addr
, int reg
, u16 val
)
1541 struct rtl8366_smi
*smi
= bus
->priv
;
1545 err
= rtl8366rb_write_phy_reg(smi
, addr
, 0, reg
, val
);
1547 (void) rtl8366rb_read_phy_reg(smi
, addr
, 0, reg
, &t
);
1552 static int rtl8366rb_mii_bus_match(struct mii_bus
*bus
)
1554 return (bus
->read
== rtl8366rb_mii_read
&&
1555 bus
->write
== rtl8366rb_mii_write
);
1558 static int rtl8366rb_setup(struct rtl8366rb
*rtl
)
1562 ret
= rtl8366rb_reset_chip(rtl
);
1566 rtl8366rb_debugfs_init(rtl
);
1570 static int rtl8366rb_detect(struct rtl8366_smi
*smi
)
1576 ret
= rtl8366_smi_read_reg(smi
, RTL8366S_CHIP_ID_REG
, &chip_id
);
1578 dev_err(smi
->parent
, "unable to read chip id\n");
1583 case RTL8366S_CHIP_ID_8366
:
1586 dev_err(smi
->parent
, "unknown chip id (%04x)\n", chip_id
);
1590 ret
= rtl8366_smi_read_reg(smi
, RTL8366S_CHIP_VERSION_CTRL_REG
,
1593 dev_err(smi
->parent
, "unable to read chip version\n");
1597 dev_info(smi
->parent
, "RTL%04x ver. %u chip found\n",
1598 chip_id
, chip_ver
& RTL8366S_CHIP_VERSION_MASK
);
1603 static struct rtl8366_smi_ops rtl8366rb_smi_ops
= {
1604 .detect
= rtl8366rb_detect
,
1605 .mii_read
= rtl8366rb_mii_read
,
1606 .mii_write
= rtl8366rb_mii_write
,
1609 static int __init
rtl8366rb_probe(struct platform_device
*pdev
)
1611 static int rtl8366_smi_version_printed
;
1612 struct rtl8366rb_platform_data
*pdata
;
1613 struct rtl8366rb
*rtl
;
1614 struct rtl8366_smi
*smi
;
1617 if (!rtl8366_smi_version_printed
++)
1618 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1619 " version " RTL8366S_DRIVER_VER
"\n");
1621 pdata
= pdev
->dev
.platform_data
;
1623 dev_err(&pdev
->dev
, "no platform data specified\n");
1628 rtl
= kzalloc(sizeof(*rtl
), GFP_KERNEL
);
1630 dev_err(&pdev
->dev
, "no memory for private data\n");
1635 rtl
->parent
= &pdev
->dev
;
1638 smi
->parent
= &pdev
->dev
;
1639 smi
->gpio_sda
= pdata
->gpio_sda
;
1640 smi
->gpio_sck
= pdata
->gpio_sck
;
1641 smi
->ops
= &rtl8366rb_smi_ops
;
1643 err
= rtl8366_smi_init(smi
);
1647 platform_set_drvdata(pdev
, rtl
);
1649 err
= rtl8366rb_setup(rtl
);
1651 goto err_clear_drvdata
;
1653 err
= rtl8366rb_switch_init(rtl
);
1655 goto err_clear_drvdata
;
1660 platform_set_drvdata(pdev
, NULL
);
1661 rtl8366_smi_cleanup(smi
);
1668 static int rtl8366rb_phy_config_init(struct phy_device
*phydev
)
1670 if (!rtl8366rb_mii_bus_match(phydev
->bus
))
1676 static int rtl8366rb_phy_config_aneg(struct phy_device
*phydev
)
1681 static struct phy_driver rtl8366rb_phy_driver
= {
1682 .phy_id
= 0x001cc960,
1683 .name
= "Realtek RTL8366RB",
1684 .phy_id_mask
= 0x1ffffff0,
1685 .features
= PHY_GBIT_FEATURES
,
1686 .config_aneg
= rtl8366rb_phy_config_aneg
,
1687 .config_init
= rtl8366rb_phy_config_init
,
1688 .read_status
= genphy_read_status
,
1690 .owner
= THIS_MODULE
,
1694 static int __devexit
rtl8366rb_remove(struct platform_device
*pdev
)
1696 struct rtl8366rb
*rtl
= platform_get_drvdata(pdev
);
1699 rtl8366rb_switch_cleanup(rtl
);
1700 rtl8366rb_debugfs_remove(rtl
);
1701 platform_set_drvdata(pdev
, NULL
);
1702 rtl8366_smi_cleanup(&rtl
->smi
);
1709 static struct platform_driver rtl8366rb_driver
= {
1711 .name
= RTL8366RB_DRIVER_NAME
,
1712 .owner
= THIS_MODULE
,
1714 .probe
= rtl8366rb_probe
,
1715 .remove
= __devexit_p(rtl8366rb_remove
),
1718 static int __init
rtl8366rb_module_init(void)
1721 ret
= platform_driver_register(&rtl8366rb_driver
);
1725 ret
= phy_driver_register(&rtl8366rb_phy_driver
);
1727 goto err_platform_unregister
;
1731 err_platform_unregister
:
1732 platform_driver_unregister(&rtl8366rb_driver
);
1735 module_init(rtl8366rb_module_init
);
1737 static void __exit
rtl8366rb_module_exit(void)
1739 phy_driver_unregister(&rtl8366rb_phy_driver
);
1740 platform_driver_unregister(&rtl8366rb_driver
);
1742 module_exit(rtl8366rb_module_exit
);
1744 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC
);
1745 MODULE_VERSION(RTL8366S_DRIVER_VER
);
1746 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1747 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1748 MODULE_LICENSE("GPL v2");
1749 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME
);