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[openwrt/openwrt.git] / target / linux / generic-2.6 / files / drivers / net / phy / rtl8366rb.c
1 /*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/rtl8366rb.h>
20
21 #include "rtl8366_smi.h"
22
23 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
24 #include <linux/debugfs.h>
25 #endif
26
27 #define RTL8366S_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
28 #define RTL8366S_DRIVER_VER "0.2.2"
29
30 #define RTL8366S_PHY_NO_MAX 4
31 #define RTL8366S_PHY_PAGE_MAX 7
32 #define RTL8366S_PHY_ADDR_MAX 31
33
34 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
35 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
36 #define RTL8366_CHIP_CTRL_VLAN_4KTB (1 << 14)
37
38 /* Switch Global Configuration register */
39 #define RTL8366_SGCR 0x0000
40 #define RTL8366_SGCR_EN_BC_STORM_CTRL BIT(0)
41 #define RTL8366_SGCR_MAX_LENGTH(_x) (_x << 4)
42 #define RTL8366_SGCR_MAX_LENGTH_MASK RTL8366_SGCR_MAX_LENGTH(0x3)
43 #define RTL8366_SGCR_MAX_LENGTH_1522 RTL8366_SGCR_MAX_LENGTH(0x0)
44 #define RTL8366_SGCR_MAX_LENGTH_1536 RTL8366_SGCR_MAX_LENGTH(0x1)
45 #define RTL8366_SGCR_MAX_LENGTH_1552 RTL8366_SGCR_MAX_LENGTH(0x2)
46 #define RTL8366_SGCR_MAX_LENGTH_9216 RTL8366_SGCR_MAX_LENGTH(0x3)
47
48 /* Port Enable Control register */
49 #define RTL8366_PECR 0x0001
50
51 /* Switch Security Control registers */
52 #define RTL8366_SSCR0 0x0002
53 #define RTL8366_SSCR1 0x0003
54 #define RTL8366_SSCR2 0x0004
55 #define RTL8366_SSCR2_DROP_UNKNOWN_DA BIT(0)
56
57 #define RTL8366_RESET_CTRL_REG 0x0100
58 #define RTL8366_CHIP_CTRL_RESET_HW 1
59 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
60
61 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x050A
62 #define RTL8366S_CHIP_VERSION_MASK 0xf
63 #define RTL8366S_CHIP_ID_REG 0x0509
64 #define RTL8366S_CHIP_ID_8366 0x5937
65
66 /* PHY registers control */
67 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8000
68 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8002
69
70 #define RTL8366S_PHY_CTRL_READ 1
71 #define RTL8366S_PHY_CTRL_WRITE 0
72
73 #define RTL8366S_PHY_REG_MASK 0x1f
74 #define RTL8366S_PHY_PAGE_OFFSET 5
75 #define RTL8366S_PHY_PAGE_MASK (0xf << 5)
76 #define RTL8366S_PHY_NO_OFFSET 9
77 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
78
79 /* LED control registers */
80 #define RTL8366_LED_BLINKRATE_REG 0x0430
81 #define RTL8366_LED_BLINKRATE_BIT 0
82 #define RTL8366_LED_BLINKRATE_MASK 0x0007
83
84 #define RTL8366_LED_CTRL_REG 0x0431
85 #define RTL8366_LED_0_1_CTRL_REG 0x0432
86 #define RTL8366_LED_2_3_CTRL_REG 0x0433
87
88 #define RTL8366S_MIB_COUNT 33
89 #define RTL8366S_GLOBAL_MIB_COUNT 1
90 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0050
91 #define RTL8366S_MIB_COUNTER_BASE 0x1000
92 #define RTL8366S_MIB_CTRL_REG 0x13F0
93 #define RTL8366S_MIB_CTRL_USER_MASK 0x0FFC
94 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
95 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0001
96
97 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
98 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
99 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
100
101
102 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0063
103 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
104 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
105 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
106 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
107
108
109 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018C
110 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
111
112
113 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
114 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
115 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
116
117 #define RTL8366S_VLAN_MEMCONF_BASE 0x0020
118
119
120 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0014
121 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
122 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
123 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
124 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
125 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
126 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
127
128
129 #define RTL8366_PORT_NUM_CPU 5
130 #define RTL8366_NUM_PORTS 6
131 #define RTL8366_NUM_VLANS 16
132 #define RTL8366_NUM_LEDGROUPS 4
133 #define RTL8366_NUM_VIDS 4096
134 #define RTL8366S_PRIORITYMAX 7
135 #define RTL8366S_FIDMAX 7
136
137
138 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
139 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
140 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
141 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
142 #define RTL8366_PORT_5 (1 << 4) /* In userspace port 4 */
143
144 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
145
146 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
147 RTL8366_PORT_2 | \
148 RTL8366_PORT_3 | \
149 RTL8366_PORT_4 | \
150 RTL8366_PORT_5 | \
151 RTL8366_PORT_CPU)
152
153 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
154 RTL8366_PORT_2 | \
155 RTL8366_PORT_3 | \
156 RTL8366_PORT_4 | \
157 RTL8366_PORT_5)
158
159 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
160 RTL8366_PORT_2 | \
161 RTL8366_PORT_3 | \
162 RTL8366_PORT_4)
163
164 #define RTL8366_PORT_ALL_INTERNAL RTL8366_PORT_CPU
165
166 struct rtl8366rb {
167 struct device *parent;
168 struct rtl8366_smi smi;
169 struct switch_dev dev;
170 char buf[4096];
171 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
172 struct dentry *debugfs_root;
173 #endif
174 };
175
176 struct rtl8366rb_vlan_mc {
177 u16 reserved2:1;
178 u16 priority:3;
179 u16 vid:12;
180 u16 untag:8;
181 u16 member:8;
182 u16 stag_mbr:8;
183 u16 stag_idx:3;
184 u16 reserved1:2;
185 u16 fid:3;
186 };
187
188 struct rtl8366rb_vlan_4k {
189 u16 reserved1:4;
190 u16 vid:12;
191 u16 untag:8;
192 u16 member:8;
193 u16 reserved2:13;
194 u16 fid:3;
195 };
196
197 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
198 u16 gl_dbg_reg;
199 #endif
200
201 struct mib_counter {
202 unsigned offset;
203 unsigned length;
204 const char *name;
205 };
206
207 static struct mib_counter rtl8366rb_mib_counters[RTL8366S_MIB_COUNT] = {
208 { 0, 4, "IfInOctets" },
209 { 4, 4, "EtherStatsOctets" },
210 { 8, 2, "EtherStatsUnderSizePkts" },
211 { 10, 2, "EtherFragments" },
212 { 12, 2, "EtherStatsPkts64Octets" },
213 { 14, 2, "EtherStatsPkts65to127Octets" },
214 { 16, 2, "EtherStatsPkts128to255Octets" },
215 { 18, 2, "EtherStatsPkts256to511Octets" },
216 { 20, 2, "EtherStatsPkts512to1023Octets" },
217 { 22, 2, "EtherStatsPkts1024to1518Octets" },
218 { 24, 2, "EtherOversizeStats" },
219 { 26, 2, "EtherStatsJabbers" },
220 { 28, 2, "IfInUcastPkts" },
221 { 30, 2, "EtherStatsMulticastPkts" },
222 { 32, 2, "EtherStatsBroadcastPkts" },
223 { 34, 2, "EtherStatsDropEvents" },
224 { 36, 2, "Dot3StatsFCSErrors" },
225 { 38, 2, "Dot3StatsSymbolErrors" },
226 { 40, 2, "Dot3InPauseFrames" },
227 { 42, 2, "Dot3ControlInUnknownOpcodes" },
228 { 44, 4, "IfOutOctets" },
229 { 48, 2, "Dot3StatsSingleCollisionFrames" },
230 { 50, 2, "Dot3StatMultipleCollisionFrames" },
231 { 52, 2, "Dot3sDeferredTransmissions" },
232 { 54, 2, "Dot3StatsLateCollisions" },
233 { 56, 2, "EtherStatsCollisions" },
234 { 58, 2, "Dot3StatsExcessiveCollisions" },
235 { 60, 2, "Dot3OutPauseFrames" },
236 { 62, 2, "Dot1dBasePortDelayExceededDiscards" },
237 { 64, 2, "Dot1dTpPortInDiscards" },
238 { 66, 2, "IfOutUcastPkts" },
239 { 68, 2, "IfOutMulticastPkts" },
240 { 70, 2, "IfOutBroadcastPkts" },
241 };
242
243 #define REG_WR(_smi, _reg, _val) \
244 do { \
245 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
246 if (err) \
247 return err; \
248 } while (0)
249
250 #define REG_RMW(_smi, _reg, _mask, _val) \
251 do { \
252 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
253 if (err) \
254 return err; \
255 } while (0)
256
257 static inline struct rtl8366rb *smi_to_rtl8366rb(struct rtl8366_smi *smi)
258 {
259 return container_of(smi, struct rtl8366rb, smi);
260 }
261
262 static inline struct rtl8366rb *sw_to_rtl8366rb(struct switch_dev *sw)
263 {
264 return container_of(sw, struct rtl8366rb, dev);
265 }
266
267 static inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw)
268 {
269 struct rtl8366rb *rtl = sw_to_rtl8366rb(sw);
270 return &rtl->smi;
271 }
272
273 static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
274 {
275 int timeout = 10;
276 u32 data;
277
278 rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
279 RTL8366_CHIP_CTRL_RESET_HW);
280 do {
281 msleep(1);
282 if (rtl8366_smi_read_reg(smi, RTL8366_RESET_CTRL_REG, &data))
283 return -EIO;
284
285 if (!(data & RTL8366_CHIP_CTRL_RESET_HW))
286 break;
287 } while (--timeout);
288
289 if (!timeout) {
290 printk("Timeout waiting for the switch to reset\n");
291 return -EIO;
292 }
293
294 return 0;
295 }
296
297 static int rtl8366rb_hw_init(struct rtl8366_smi *smi)
298 {
299 int err;
300
301 /* set maximum packet length to 1536 bytes */
302 REG_RMW(smi, RTL8366_SGCR, RTL8366_SGCR_MAX_LENGTH_MASK,
303 RTL8366_SGCR_MAX_LENGTH_1536);
304
305 /* enable all ports */
306 REG_WR(smi, RTL8366_PECR, 0);
307
308 /* disable learning for all ports */
309 REG_WR(smi, RTL8366_SSCR0, RTL8366_PORT_ALL);
310
311 /* disable auto ageing for all ports */
312 REG_WR(smi, RTL8366_SSCR1, RTL8366_PORT_ALL);
313
314 /* don't drop packets whose DA has not been learned */
315 REG_RMW(smi, RTL8366_SSCR2, RTL8366_SSCR2_DROP_UNKNOWN_DA, 0);
316
317 return 0;
318 }
319
320 static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
321 u32 phy_no, u32 page, u32 addr, u32 *data)
322 {
323 u32 reg;
324 int ret;
325
326 if (phy_no > RTL8366S_PHY_NO_MAX)
327 return -EINVAL;
328
329 if (page > RTL8366S_PHY_PAGE_MAX)
330 return -EINVAL;
331
332 if (addr > RTL8366S_PHY_ADDR_MAX)
333 return -EINVAL;
334
335 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
336 RTL8366S_PHY_CTRL_READ);
337 if (ret)
338 return ret;
339
340 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
341 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
342 (addr & RTL8366S_PHY_REG_MASK);
343
344 ret = rtl8366_smi_write_reg(smi, reg, 0);
345 if (ret)
346 return ret;
347
348 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
349 if (ret)
350 return ret;
351
352 return 0;
353 }
354
355 static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
356 u32 phy_no, u32 page, u32 addr, u32 data)
357 {
358 u32 reg;
359 int ret;
360
361 if (phy_no > RTL8366S_PHY_NO_MAX)
362 return -EINVAL;
363
364 if (page > RTL8366S_PHY_PAGE_MAX)
365 return -EINVAL;
366
367 if (addr > RTL8366S_PHY_ADDR_MAX)
368 return -EINVAL;
369
370 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
371 RTL8366S_PHY_CTRL_WRITE);
372 if (ret)
373 return ret;
374
375 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
376 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
377 (addr & RTL8366S_PHY_REG_MASK);
378
379 ret = rtl8366_smi_write_reg(smi, reg, data);
380 if (ret)
381 return ret;
382
383 return 0;
384 }
385
386 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
387 int port, unsigned long long *val)
388 {
389 int i;
390 int err;
391 u32 addr, data;
392 u64 mibvalue;
393
394 if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
395 return -EINVAL;
396
397 addr = RTL8366S_MIB_COUNTER_BASE +
398 RTL8366S_MIB_COUNTER_PORT_OFFSET * (port) +
399 rtl8366rb_mib_counters[counter].offset;
400
401 /*
402 * Writing access counter address first
403 * then ASIC will prepare 64bits counter wait for being retrived
404 */
405 data = 0; /* writing data will be discard by ASIC */
406 err = rtl8366_smi_write_reg(smi, addr, data);
407 if (err)
408 return err;
409
410 /* read MIB control register */
411 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
412 if (err)
413 return err;
414
415 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
416 return -EBUSY;
417
418 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
419 return -EIO;
420
421 mibvalue = 0;
422 for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
423 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
424 if (err)
425 return err;
426
427 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
428 }
429
430 *val = mibvalue;
431 return 0;
432 }
433
434 static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
435 struct rtl8366_vlan_4k *vlan4k)
436 {
437 struct rtl8366rb_vlan_4k vlan4k_priv;
438 int err;
439 u32 data;
440 u16 *tableaddr;
441
442 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
443 vlan4k_priv.vid = vid;
444
445 if (vid >= RTL8366_NUM_VIDS)
446 return -EINVAL;
447
448 tableaddr = (u16 *)&vlan4k_priv;
449
450 /* write VID */
451 data = *tableaddr;
452 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
453 if (err)
454 return err;
455
456 /* write table access control word */
457 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
458 RTL8366S_TABLE_VLAN_READ_CTRL);
459 if (err)
460 return err;
461
462 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
463 if (err)
464 return err;
465
466 *tableaddr = data;
467 tableaddr++;
468
469 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
470 &data);
471 if (err)
472 return err;
473
474 *tableaddr = data;
475 tableaddr++;
476
477 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 2,
478 &data);
479 if (err)
480 return err;
481 *tableaddr = data;
482
483 vlan4k->vid = vid;
484 vlan4k->untag = vlan4k_priv.untag;
485 vlan4k->member = vlan4k_priv.member;
486 vlan4k->fid = vlan4k_priv.fid;
487
488 return 0;
489 }
490
491 static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
492 const struct rtl8366_vlan_4k *vlan4k)
493 {
494 struct rtl8366rb_vlan_4k vlan4k_priv;
495 int err;
496 u32 data;
497 u16 *tableaddr;
498
499 if (vlan4k->vid >= RTL8366_NUM_VIDS ||
500 vlan4k->member > RTL8366_PORT_ALL ||
501 vlan4k->untag > RTL8366_PORT_ALL ||
502 vlan4k->fid > RTL8366S_FIDMAX)
503 return -EINVAL;
504
505 vlan4k_priv.vid = vlan4k->vid;
506 vlan4k_priv.untag = vlan4k->untag;
507 vlan4k_priv.member = vlan4k->member;
508 vlan4k_priv.fid = vlan4k->fid;
509
510 tableaddr = (u16 *)&vlan4k_priv;
511
512 data = *tableaddr;
513
514 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
515 if (err)
516 return err;
517
518 tableaddr++;
519
520 data = *tableaddr;
521
522 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
523 data);
524 if (err)
525 return err;
526
527 tableaddr++;
528
529 data = *tableaddr;
530
531 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 2,
532 data);
533 if (err)
534 return err;
535
536 /* write table access control word */
537 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
538 RTL8366S_TABLE_VLAN_WRITE_CTRL);
539
540 return err;
541 }
542
543 static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
544 struct rtl8366_vlan_mc *vlanmc)
545 {
546 struct rtl8366rb_vlan_mc vlanmc_priv;
547 int err;
548 u32 addr;
549 u32 data;
550 u16 *tableaddr;
551
552 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
553
554 if (index >= RTL8366_NUM_VLANS)
555 return -EINVAL;
556
557 tableaddr = (u16 *)&vlanmc_priv;
558
559 addr = RTL8366S_VLAN_MEMCONF_BASE + (index * 3);
560 err = rtl8366_smi_read_reg(smi, addr, &data);
561 if (err)
562 return err;
563
564 *tableaddr = data;
565 tableaddr++;
566
567 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index * 3);
568 err = rtl8366_smi_read_reg(smi, addr, &data);
569 if (err)
570 return err;
571
572 *tableaddr = data;
573 tableaddr++;
574
575 addr = RTL8366S_VLAN_MEMCONF_BASE + 2 + (index * 3);
576 err = rtl8366_smi_read_reg(smi, addr, &data);
577 if (err)
578 return err;
579
580 *tableaddr = data;
581
582 vlanmc->vid = vlanmc_priv.vid;
583 vlanmc->priority = vlanmc_priv.priority;
584 vlanmc->untag = vlanmc_priv.untag;
585 vlanmc->member = vlanmc_priv.member;
586 vlanmc->fid = vlanmc_priv.fid;
587
588 return 0;
589 }
590
591 static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
592 const struct rtl8366_vlan_mc *vlanmc)
593 {
594 struct rtl8366rb_vlan_mc vlanmc_priv;
595 int err;
596 u32 addr;
597 u32 data;
598 u16 *tableaddr;
599
600 if (index >= RTL8366_NUM_VLANS ||
601 vlanmc->vid >= RTL8366_NUM_VIDS ||
602 vlanmc->priority > RTL8366S_PRIORITYMAX ||
603 vlanmc->member > RTL8366_PORT_ALL ||
604 vlanmc->untag > RTL8366_PORT_ALL ||
605 vlanmc->fid > RTL8366S_FIDMAX)
606 return -EINVAL;
607
608 vlanmc_priv.vid = vlanmc->vid;
609 vlanmc_priv.priority = vlanmc->priority;
610 vlanmc_priv.untag = vlanmc->untag;
611 vlanmc_priv.member = vlanmc->member;
612 vlanmc_priv.stag_mbr = 0;
613 vlanmc_priv.stag_idx = 0;
614 vlanmc_priv.fid = vlanmc->fid;
615
616 addr = RTL8366S_VLAN_MEMCONF_BASE + (index * 3);
617
618 tableaddr = (u16 *)&vlanmc_priv;
619 data = *tableaddr;
620
621 err = rtl8366_smi_write_reg(smi, addr, data);
622 if (err)
623 return err;
624
625 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index * 3);
626
627 tableaddr++;
628 data = *tableaddr;
629
630 err = rtl8366_smi_write_reg(smi, addr, data);
631 if (err)
632 return err;
633
634 addr = RTL8366S_VLAN_MEMCONF_BASE + 2 + (index * 3);
635
636 tableaddr++;
637 data = *tableaddr;
638
639 err = rtl8366_smi_write_reg(smi, addr, data);
640 if (err)
641 return err;
642 return 0;
643 }
644
645 static int rtl8366rb_get_port_vlan_index(struct rtl8366_smi *smi, int port,
646 int *val)
647 {
648 u32 data;
649 int err;
650
651 if (port >= RTL8366_NUM_PORTS)
652 return -EINVAL;
653
654 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
655 &data);
656 if (err)
657 return err;
658
659 *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
660 RTL8366S_PORT_VLAN_CTRL_MASK;
661
662 return 0;
663
664 }
665
666 static int rtl8366rb_get_vlan_port_pvid(struct rtl8366_smi *smi, int port,
667 int *val)
668 {
669 struct rtl8366_vlan_mc vlanmc;
670 int err;
671 int index;
672
673 err = rtl8366rb_get_port_vlan_index(smi, port, &index);
674 if (err)
675 return err;
676
677 err = rtl8366rb_get_vlan_mc(smi, index, &vlanmc);
678 if (err)
679 return err;
680
681 *val = vlanmc.vid;
682 return 0;
683 }
684
685 static int rtl8366rb_set_port_vlan_index(struct rtl8366_smi *smi, int port,
686 int index)
687 {
688 if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
689 return -EINVAL;
690
691 return rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
692 RTL8366S_PORT_VLAN_CTRL_MASK <<
693 RTL8366S_PORT_VLAN_CTRL_SHIFT(port),
694 (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
695 RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
696 }
697
698 static int rtl8366rb_set_vlan_port_pvid(struct rtl8366_smi *smi, int port,
699 int val)
700 {
701 int i;
702 struct rtl8366_vlan_mc vlanmc;
703 struct rtl8366_vlan_4k vlan4k;
704
705 if (port >= RTL8366_NUM_PORTS || val >= RTL8366_NUM_VIDS)
706 return -EINVAL;
707
708 /* Updating the 4K entry; lookup it and change the port member set */
709 rtl8366rb_get_vlan_4k(smi, val, &vlan4k);
710 vlan4k.member |= ((1 << port) | RTL8366_PORT_CPU);
711 vlan4k.untag = RTL8366_PORT_ALL_BUT_CPU;
712 rtl8366rb_set_vlan_4k(smi, &vlan4k);
713
714 /*
715 * For the 16 entries more work needs to be done. First see if such
716 * VID is already there and change it
717 */
718 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
719 rtl8366rb_get_vlan_mc(smi, i, &vlanmc);
720
721 /* Try to find an existing vid and update port member set */
722 if (val == vlanmc.vid) {
723 vlanmc.member |= ((1 << port) | RTL8366_PORT_CPU);
724 rtl8366rb_set_vlan_mc(smi, i, &vlanmc);
725
726 /* Now update PVID register settings */
727 rtl8366rb_set_port_vlan_index(smi, port, i);
728
729 return 0;
730 }
731 }
732
733 /*
734 * PVID could not be found from vlan table. Replace unused (one that
735 * has no member ports) with new one
736 */
737 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
738 rtl8366rb_get_vlan_mc(smi, i, &vlanmc);
739
740 /*
741 * See if this vlan member configuration is unused. It is
742 * unused if member set contains no ports or CPU port only
743 */
744 if (!vlanmc.member || vlanmc.member == RTL8366_PORT_CPU) {
745 vlanmc.vid = val;
746 vlanmc.priority = 0;
747 vlanmc.untag = RTL8366_PORT_ALL_BUT_CPU;
748 vlanmc.member = ((1 << port) | RTL8366_PORT_CPU);
749 vlanmc.fid = 0;
750
751 rtl8366rb_set_vlan_mc(smi, i, &vlanmc);
752
753 /* Now update PVID register settings */
754 rtl8366rb_set_port_vlan_index(smi, port, i);
755
756 return 0;
757 }
758 }
759
760 dev_err(smi->parent,
761 "All 16 vlan member configurations are in use\n");
762
763 return -EINVAL;
764 }
765
766
767 static int rtl8366rb_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
768 {
769 return rtl8366_smi_rmwr(smi, RTL8366_CHIP_GLOBAL_CTRL_REG,
770 RTL8366_CHIP_CTRL_VLAN,
771 (enable) ? RTL8366_CHIP_CTRL_VLAN : 0);
772 }
773
774 static int rtl8366rb_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
775 {
776 return rtl8366_smi_rmwr(smi, RTL8366_CHIP_GLOBAL_CTRL_REG,
777 RTL8366_CHIP_CTRL_VLAN_4KTB,
778 (enable) ? RTL8366_CHIP_CTRL_VLAN_4KTB : 0);
779 }
780
781 static int rtl8366rb_reset_vlan(struct rtl8366_smi *smi)
782 {
783 struct rtl8366_vlan_4k vlan4k;
784 struct rtl8366_vlan_mc vlanmc;
785 int err;
786 int i;
787
788 /* clear 16 VLAN member configuration */
789 vlanmc.vid = 0;
790 vlanmc.priority = 0;
791 vlanmc.member = 0;
792 vlanmc.untag = 0;
793 vlanmc.fid = 0;
794 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
795 err = rtl8366rb_set_vlan_mc(smi, i, &vlanmc);
796 if (err)
797 return err;
798 }
799
800 /* Set a default VLAN with vid 1 to 4K table for all ports */
801 vlan4k.vid = 1;
802 vlan4k.member = RTL8366_PORT_ALL;
803 vlan4k.untag = RTL8366_PORT_ALL;
804 vlan4k.fid = 0;
805 err = rtl8366rb_set_vlan_4k(smi, &vlan4k);
806 if (err)
807 return err;
808
809 /* Set all ports PVID to default VLAN */
810 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
811 err = rtl8366rb_set_vlan_port_pvid(smi, i, 0);
812 if (err)
813 return err;
814 }
815
816 return 0;
817 }
818
819 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
820 static int rtl8366rb_debugfs_open(struct inode *inode, struct file *file)
821 {
822 file->private_data = inode->i_private;
823 return 0;
824 }
825
826 static ssize_t rtl8366rb_read_debugfs_mibs(struct file *file,
827 char __user *user_buf,
828 size_t count, loff_t *ppos)
829 {
830 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
831 struct rtl8366_smi *smi = &rtl->smi;
832 int i, j, len = 0;
833 char *buf = rtl->buf;
834
835 len += snprintf(buf + len, sizeof(rtl->buf) - len,
836 "%-36s %12s %12s %12s %12s %12s %12s\n",
837 "Counter",
838 "Port 0", "Port 1", "Port 2",
839 "Port 3", "Port 4", "Port 5");
840
841 for (i = 0; i < ARRAY_SIZE(rtl8366rb_mib_counters); ++i) {
842 len += snprintf(buf + len, sizeof(rtl->buf) - len, "%-36s ",
843 rtl8366rb_mib_counters[i].name);
844 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
845 unsigned long long counter = 0;
846
847 if (!rtl8366_get_mib_counter(smi, i, j, &counter))
848 len += snprintf(buf + len,
849 sizeof(rtl->buf) - len,
850 "%12llu ", counter);
851 else
852 len += snprintf(buf + len,
853 sizeof(rtl->buf) - len,
854 "%12s ", "error");
855 }
856 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
857 }
858
859 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
860 }
861
862 static ssize_t rtl8366rb_read_debugfs_vlan(struct file *file,
863 char __user *user_buf,
864 size_t count, loff_t *ppos)
865 {
866 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
867 struct rtl8366_smi *smi = &rtl->smi;
868 int i, j, len = 0;
869 char *buf = rtl->buf;
870
871 len += snprintf(buf + len, sizeof(rtl->buf) - len,
872 "VLAN Member Config:\n");
873 len += snprintf(buf + len, sizeof(rtl->buf) - len,
874 "\t id \t vid \t prio \t member \t untag \t fid "
875 "\tports\n");
876
877 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
878 struct rtl8366_vlan_mc vlanmc;
879
880 rtl8366rb_get_vlan_mc(smi, i, &vlanmc);
881
882 len += snprintf(buf + len, sizeof(rtl->buf) - len,
883 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
884 "\t", i, vlanmc.vid, vlanmc.priority,
885 vlanmc.member, vlanmc.untag, vlanmc.fid);
886
887 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
888 int index = 0;
889 if (!rtl8366rb_get_port_vlan_index(smi, j, &index)) {
890 if (index == i)
891 len += snprintf(buf + len,
892 sizeof(rtl->buf) - len,
893 "%d", j);
894 }
895 }
896 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
897 }
898
899 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
900 }
901
902 static ssize_t rtl8366rb_read_debugfs_reg(struct file *file,
903 char __user *user_buf,
904 size_t count, loff_t *ppos)
905 {
906 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
907 struct rtl8366_smi *smi = &rtl->smi;
908 u32 t, reg = gl_dbg_reg;
909 int err, len = 0;
910 char *buf = rtl->buf;
911
912 memset(buf, '\0', sizeof(rtl->buf));
913
914 err = rtl8366_smi_read_reg(smi, reg, &t);
915 if (err) {
916 len += snprintf(buf, sizeof(rtl->buf),
917 "Read failed (reg: 0x%04x)\n", reg);
918 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
919 }
920
921 len += snprintf(buf, sizeof(rtl->buf), "reg = 0x%04x, val = 0x%04x\n",
922 reg, t);
923
924 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
925 }
926
927 static ssize_t rtl8366rb_write_debugfs_reg(struct file *file,
928 const char __user *user_buf,
929 size_t count, loff_t *ppos)
930 {
931 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
932 struct rtl8366_smi *smi = &rtl->smi;
933 unsigned long data;
934 u32 reg = gl_dbg_reg;
935 int err;
936 size_t len;
937 char *buf = rtl->buf;
938
939 len = min(count, sizeof(rtl->buf) - 1);
940 if (copy_from_user(buf, user_buf, len)) {
941 dev_err(rtl->parent, "copy from user failed\n");
942 return -EFAULT;
943 }
944
945 buf[len] = '\0';
946 if (len > 0 && buf[len - 1] == '\n')
947 buf[len - 1] = '\0';
948
949
950 if (strict_strtoul(buf, 16, &data)) {
951 dev_err(rtl->parent, "Invalid reg value %s\n", buf);
952 } else {
953 err = rtl8366_smi_write_reg(smi, reg, data);
954 if (err) {
955 dev_err(rtl->parent,
956 "writing reg 0x%04x val 0x%04lx failed\n",
957 reg, data);
958 }
959 }
960
961 return count;
962 }
963
964 static const struct file_operations fops_rtl8366rb_regs = {
965 .read = rtl8366rb_read_debugfs_reg,
966 .write = rtl8366rb_write_debugfs_reg,
967 .open = rtl8366rb_debugfs_open,
968 .owner = THIS_MODULE
969 };
970
971 static const struct file_operations fops_rtl8366rb_vlan = {
972 .read = rtl8366rb_read_debugfs_vlan,
973 .open = rtl8366rb_debugfs_open,
974 .owner = THIS_MODULE
975 };
976
977 static const struct file_operations fops_rtl8366rb_mibs = {
978 .read = rtl8366rb_read_debugfs_mibs,
979 .open = rtl8366rb_debugfs_open,
980 .owner = THIS_MODULE
981 };
982
983 static void rtl8366rb_debugfs_init(struct rtl8366rb *rtl)
984 {
985 struct dentry *node;
986 struct dentry *root;
987
988 if (!rtl->debugfs_root)
989 rtl->debugfs_root = debugfs_create_dir("rtl8366rb", NULL);
990
991 if (!rtl->debugfs_root) {
992 dev_err(rtl->parent, "Unable to create debugfs dir\n");
993 return;
994 }
995 root = rtl->debugfs_root;
996
997 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &gl_dbg_reg);
998 if (!node) {
999 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
1000 "reg");
1001 return;
1002 }
1003
1004 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, rtl,
1005 &fops_rtl8366rb_regs);
1006 if (!node) {
1007 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
1008 "val");
1009 return;
1010 }
1011
1012 node = debugfs_create_file("vlan", S_IRUSR, root, rtl,
1013 &fops_rtl8366rb_vlan);
1014 if (!node) {
1015 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
1016 "vlan");
1017 return;
1018 }
1019
1020 node = debugfs_create_file("mibs", S_IRUSR, root, rtl,
1021 &fops_rtl8366rb_mibs);
1022 if (!node) {
1023 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
1024 "mibs");
1025 return;
1026 }
1027 }
1028
1029 static void rtl8366rb_debugfs_remove(struct rtl8366rb *rtl)
1030 {
1031 if (rtl->debugfs_root) {
1032 debugfs_remove_recursive(rtl->debugfs_root);
1033 rtl->debugfs_root = NULL;
1034 }
1035 }
1036
1037 #else
1038 static inline void rtl8366rb_debugfs_init(struct rtl8366rb *rtl) {}
1039 static inline void rtl8366rb_debugfs_remove(struct rtl8366rb *rtl) {}
1040 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
1041
1042 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
1043 const struct switch_attr *attr,
1044 struct switch_val *val)
1045 {
1046 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1047 int err = 0;
1048
1049 if (val->value.i == 1)
1050 err = rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, (1 << 2));
1051
1052 return err;
1053 }
1054
1055 static int rtl8366rb_sw_get_vlan_enable(struct switch_dev *dev,
1056 const struct switch_attr *attr,
1057 struct switch_val *val)
1058 {
1059 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1060 u32 data;
1061
1062 if (attr->ofs == 1) {
1063 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1064
1065 if (data & RTL8366_CHIP_CTRL_VLAN)
1066 val->value.i = 1;
1067 else
1068 val->value.i = 0;
1069 } else if (attr->ofs == 2) {
1070 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1071
1072 if (data & RTL8366_CHIP_CTRL_VLAN_4KTB)
1073 val->value.i = 1;
1074 else
1075 val->value.i = 0;
1076 }
1077
1078 return 0;
1079 }
1080
1081 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
1082 const struct switch_attr *attr,
1083 struct switch_val *val)
1084 {
1085 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1086 u32 data;
1087
1088 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1089
1090 val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
1091
1092 return 0;
1093 }
1094
1095 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
1096 const struct switch_attr *attr,
1097 struct switch_val *val)
1098 {
1099 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1100
1101 if (val->value.i >= 6)
1102 return -EINVAL;
1103
1104 return rtl8366_smi_rmwr(smi, RTL8366_LED_BLINKRATE_REG,
1105 RTL8366_LED_BLINKRATE_MASK,
1106 val->value.i);
1107 }
1108
1109 static int rtl8366rb_sw_set_vlan_enable(struct switch_dev *dev,
1110 const struct switch_attr *attr,
1111 struct switch_val *val)
1112 {
1113 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1114
1115 if (attr->ofs == 1)
1116 return rtl8366rb_vlan_set_vlan(smi, val->value.i);
1117 else
1118 return rtl8366rb_vlan_set_4ktable(smi, val->value.i);
1119 }
1120
1121 static const char *rtl8366rb_speed_str(unsigned speed)
1122 {
1123 switch (speed) {
1124 case 0:
1125 return "10baseT";
1126 case 1:
1127 return "100baseT";
1128 case 2:
1129 return "1000baseT";
1130 }
1131
1132 return "unknown";
1133 }
1134
1135 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
1136 const struct switch_attr *attr,
1137 struct switch_val *val)
1138 {
1139 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1140 struct rtl8366_smi *smi = &rtl->smi;
1141 u32 len = 0, data = 0;
1142
1143 if (val->port_vlan >= RTL8366_NUM_PORTS)
1144 return -EINVAL;
1145
1146 memset(rtl->buf, '\0', sizeof(rtl->buf));
1147 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
1148 (val->port_vlan / 2), &data);
1149
1150 if (val->port_vlan % 2)
1151 data = data >> 8;
1152
1153 if (data & RTL8366S_PORT_STATUS_LINK_MASK) {
1154 len = snprintf(rtl->buf, sizeof(rtl->buf),
1155 "port:%d link:up speed:%s %s-duplex %s%s%s",
1156 val->port_vlan,
1157 rtl8366rb_speed_str(data &
1158 RTL8366S_PORT_STATUS_SPEED_MASK),
1159 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
1160 "full" : "half",
1161 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
1162 "tx-pause ": "",
1163 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
1164 "rx-pause " : "",
1165 (data & RTL8366S_PORT_STATUS_AN_MASK) ?
1166 "nway ": "");
1167 } else {
1168 len = snprintf(rtl->buf, sizeof(rtl->buf), "port:%d link: down",
1169 val->port_vlan);
1170 }
1171
1172 val->value.s = rtl->buf;
1173 val->len = len;
1174
1175 return 0;
1176 }
1177
1178 static int rtl8366rb_sw_get_vlan_info(struct switch_dev *dev,
1179 const struct switch_attr *attr,
1180 struct switch_val *val)
1181 {
1182 int i;
1183 u32 len = 0;
1184 struct rtl8366_vlan_mc vlanmc;
1185 struct rtl8366_vlan_4k vlan4k;
1186 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1187 struct rtl8366_smi *smi = &rtl->smi;
1188 char *buf = rtl->buf;
1189
1190 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1191 return -EINVAL;
1192
1193 memset(buf, '\0', sizeof(rtl->buf));
1194
1195 rtl8366rb_get_vlan_mc(smi, val->port_vlan, &vlanmc);
1196 rtl8366rb_get_vlan_4k(smi, vlanmc.vid, &vlan4k);
1197
1198 len += snprintf(buf + len, sizeof(rtl->buf) - len, "VLAN %d: Ports: ",
1199 val->port_vlan);
1200
1201 for (i = 0; i < RTL8366_NUM_PORTS; ++i) {
1202 int index = 0;
1203 if (!rtl8366rb_get_port_vlan_index(smi, i, &index) &&
1204 index == val->port_vlan)
1205 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1206 "%d", i);
1207 }
1208 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
1209
1210 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1211 "\t\t vid \t prio \t member \t untag \t fid\n");
1212 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\tMC:\t");
1213 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1214 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1215 vlanmc.vid, vlanmc.priority, vlanmc.member,
1216 vlanmc.untag, vlanmc.fid);
1217 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\t4K:\t");
1218 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1219 "%d \t \t 0x%04x \t 0x%04x \t %d",
1220 vlan4k.vid, vlan4k.member, vlan4k.untag, vlan4k.fid);
1221
1222 val->value.s = buf;
1223 val->len = len;
1224
1225 return 0;
1226 }
1227
1228 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
1229 const struct switch_attr *attr,
1230 struct switch_val *val)
1231 {
1232 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1233 u32 data;
1234 u32 mask;
1235 u32 reg;
1236
1237 if (val->port_vlan >= RTL8366_NUM_PORTS)
1238 return -EINVAL;
1239
1240 if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
1241 reg = RTL8366_LED_BLINKRATE_REG;
1242 mask = 0xF << 4;
1243 data = val->value.i << 4;
1244 } else {
1245 reg = RTL8366_LED_CTRL_REG;
1246 mask = 0xF << (val->port_vlan * 4),
1247 data = val->value.i << (val->port_vlan * 4);
1248 }
1249
1250 return rtl8366_smi_rmwr(smi, RTL8366_LED_BLINKRATE_REG, mask, data);
1251 }
1252
1253 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
1254 const struct switch_attr *attr,
1255 struct switch_val *val)
1256 {
1257 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1258 u32 data = 0;
1259
1260 if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
1261 return -EINVAL;
1262
1263 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1264 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1265
1266 return 0;
1267 }
1268
1269 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
1270 const struct switch_attr *attr,
1271 struct switch_val *val)
1272 {
1273 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1274
1275 if (val->port_vlan >= RTL8366_NUM_PORTS)
1276 return -EINVAL;
1277
1278 return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG,
1279 0, (1 << (val->port_vlan + 3)));
1280 }
1281
1282 static int rtl8366rb_sw_get_port_mib(struct switch_dev *dev,
1283 const struct switch_attr *attr,
1284 struct switch_val *val)
1285 {
1286 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1287 struct rtl8366_smi *smi = &rtl->smi;
1288 int i, len = 0;
1289 unsigned long long counter = 0;
1290 char *buf = rtl->buf;
1291
1292 if (val->port_vlan >= RTL8366_NUM_PORTS)
1293 return -EINVAL;
1294
1295 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1296 "Port %d MIB counters\n",
1297 val->port_vlan);
1298
1299 for (i = 0; i < ARRAY_SIZE(rtl8366rb_mib_counters); ++i) {
1300 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1301 "%-36s: ", rtl8366rb_mib_counters[i].name);
1302 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
1303 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1304 "%llu\n", counter);
1305 else
1306 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1307 "%s\n", "error");
1308 }
1309
1310 val->value.s = buf;
1311 val->len = len;
1312 return 0;
1313 }
1314
1315 static int rtl8366rb_sw_get_vlan_ports(struct switch_dev *dev,
1316 struct switch_val *val)
1317 {
1318 struct rtl8366_vlan_mc vlanmc;
1319 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1320 struct switch_port *port;
1321 int i;
1322
1323 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1324 return -EINVAL;
1325
1326 rtl8366rb_get_vlan_mc(smi, val->port_vlan, &vlanmc);
1327
1328 port = &val->value.ports[0];
1329 val->len = 0;
1330 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
1331 if (!(vlanmc.member & BIT(i)))
1332 continue;
1333
1334 port->id = i;
1335 port->flags = (vlanmc.untag & BIT(i)) ?
1336 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1337 val->len++;
1338 port++;
1339 }
1340 return 0;
1341 }
1342
1343 static int rtl8366rb_sw_set_vlan_ports(struct switch_dev *dev,
1344 struct switch_val *val)
1345 {
1346 struct rtl8366_vlan_mc vlanmc;
1347 struct rtl8366_vlan_4k vlan4k;
1348 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1349 struct switch_port *port;
1350 int i;
1351
1352 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1353 return -EINVAL;
1354
1355 rtl8366rb_get_vlan_mc(smi, val->port_vlan, &vlanmc);
1356 rtl8366rb_get_vlan_4k(smi, vlanmc.vid, &vlan4k);
1357
1358 vlanmc.untag = 0;
1359 vlanmc.member = 0;
1360
1361 port = &val->value.ports[0];
1362 for (i = 0; i < val->len; i++, port++) {
1363 vlanmc.member |= BIT(port->id);
1364
1365 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1366 vlanmc.untag |= BIT(port->id);
1367 }
1368
1369 vlan4k.member = vlanmc.member;
1370 vlan4k.untag = vlanmc.untag;
1371
1372 rtl8366rb_set_vlan_mc(smi, val->port_vlan, &vlanmc);
1373 rtl8366rb_set_vlan_4k(smi, &vlan4k);
1374 return 0;
1375 }
1376
1377 static int rtl8366rb_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1378 {
1379 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1380 return rtl8366rb_get_vlan_port_pvid(smi, port, val);
1381 }
1382
1383 static int rtl8366rb_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1384 {
1385 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1386 return rtl8366rb_set_vlan_port_pvid(smi, port, val);
1387 }
1388
1389 static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
1390 {
1391 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1392 int err;
1393
1394 err = rtl8366rb_reset_chip(smi);
1395 if (err)
1396 return err;
1397
1398 err = rtl8366rb_hw_init(smi);
1399 if (err)
1400 return err;
1401
1402 return rtl8366rb_reset_vlan(smi);
1403 }
1404
1405 static struct switch_attr rtl8366rb_globals[] = {
1406 {
1407 .type = SWITCH_TYPE_INT,
1408 .name = "enable_vlan",
1409 .description = "Enable VLAN mode",
1410 .set = rtl8366rb_sw_set_vlan_enable,
1411 .get = rtl8366rb_sw_get_vlan_enable,
1412 .max = 1,
1413 .ofs = 1
1414 }, {
1415 .type = SWITCH_TYPE_INT,
1416 .name = "enable_vlan4k",
1417 .description = "Enable VLAN 4K mode",
1418 .set = rtl8366rb_sw_set_vlan_enable,
1419 .get = rtl8366rb_sw_get_vlan_enable,
1420 .max = 1,
1421 .ofs = 2
1422 }, {
1423 .type = SWITCH_TYPE_INT,
1424 .name = "reset_mibs",
1425 .description = "Reset all MIB counters",
1426 .set = rtl8366rb_sw_reset_mibs,
1427 .get = NULL,
1428 .max = 1
1429 }, {
1430 .type = SWITCH_TYPE_INT,
1431 .name = "blinkrate",
1432 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1433 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1434 .set = rtl8366rb_sw_set_blinkrate,
1435 .get = rtl8366rb_sw_get_blinkrate,
1436 .max = 5
1437 },
1438 };
1439
1440 static struct switch_attr rtl8366rb_port[] = {
1441 {
1442 .type = SWITCH_TYPE_STRING,
1443 .name = "link",
1444 .description = "Get port link information",
1445 .max = 1,
1446 .set = NULL,
1447 .get = rtl8366rb_sw_get_port_link,
1448 }, {
1449 .type = SWITCH_TYPE_INT,
1450 .name = "reset_mib",
1451 .description = "Reset single port MIB counters",
1452 .max = 1,
1453 .set = rtl8366rb_sw_reset_port_mibs,
1454 .get = NULL,
1455 }, {
1456 .type = SWITCH_TYPE_STRING,
1457 .name = "mib",
1458 .description = "Get MIB counters for port",
1459 .max = 33,
1460 .set = NULL,
1461 .get = rtl8366rb_sw_get_port_mib,
1462 }, {
1463 .type = SWITCH_TYPE_INT,
1464 .name = "led",
1465 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1466 .max = 15,
1467 .set = rtl8366rb_sw_set_port_led,
1468 .get = rtl8366rb_sw_get_port_led,
1469 },
1470 };
1471
1472 static struct switch_attr rtl8366rb_vlan[] = {
1473 {
1474 .type = SWITCH_TYPE_STRING,
1475 .name = "info",
1476 .description = "Get vlan information",
1477 .max = 1,
1478 .set = NULL,
1479 .get = rtl8366rb_sw_get_vlan_info,
1480 },
1481 };
1482
1483 /* template */
1484 static struct switch_dev rtl8366_switch_dev = {
1485 .name = "RTL8366S",
1486 .cpu_port = RTL8366_PORT_NUM_CPU,
1487 .ports = RTL8366_NUM_PORTS,
1488 .vlans = RTL8366_NUM_VLANS,
1489 .attr_global = {
1490 .attr = rtl8366rb_globals,
1491 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
1492 },
1493 .attr_port = {
1494 .attr = rtl8366rb_port,
1495 .n_attr = ARRAY_SIZE(rtl8366rb_port),
1496 },
1497 .attr_vlan = {
1498 .attr = rtl8366rb_vlan,
1499 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
1500 },
1501
1502 .get_vlan_ports = rtl8366rb_sw_get_vlan_ports,
1503 .set_vlan_ports = rtl8366rb_sw_set_vlan_ports,
1504 .get_port_pvid = rtl8366rb_sw_get_port_pvid,
1505 .set_port_pvid = rtl8366rb_sw_set_port_pvid,
1506 .reset_switch = rtl8366rb_sw_reset_switch,
1507 };
1508
1509 static int rtl8366rb_switch_init(struct rtl8366rb *rtl)
1510 {
1511 struct switch_dev *dev = &rtl->dev;
1512 int err;
1513
1514 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1515 dev->priv = rtl;
1516 dev->devname = dev_name(rtl->parent);
1517
1518 err = register_switch(dev, NULL);
1519 if (err)
1520 dev_err(rtl->parent, "switch registration failed\n");
1521
1522 return err;
1523 }
1524
1525 static void rtl8366rb_switch_cleanup(struct rtl8366rb *rtl)
1526 {
1527 unregister_switch(&rtl->dev);
1528 }
1529
1530 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
1531 {
1532 struct rtl8366_smi *smi = bus->priv;
1533 u32 val = 0;
1534 int err;
1535
1536 err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
1537 if (err)
1538 return 0xffff;
1539
1540 return val;
1541 }
1542
1543 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1544 {
1545 struct rtl8366_smi *smi = bus->priv;
1546 u32 t;
1547 int err;
1548
1549 err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
1550 /* flush write */
1551 (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
1552
1553 return err;
1554 }
1555
1556 static int rtl8366rb_mii_bus_match(struct mii_bus *bus)
1557 {
1558 return (bus->read == rtl8366rb_mii_read &&
1559 bus->write == rtl8366rb_mii_write);
1560 }
1561
1562 static int rtl8366rb_setup(struct rtl8366rb *rtl)
1563 {
1564 struct rtl8366_smi *smi = &rtl->smi;
1565 int ret;
1566
1567 rtl8366rb_debugfs_init(rtl);
1568
1569 ret = rtl8366rb_reset_chip(smi);
1570 if (ret)
1571 return ret;
1572
1573 ret = rtl8366rb_hw_init(smi);
1574 return ret;
1575 }
1576
1577 static int rtl8366rb_detect(struct rtl8366_smi *smi)
1578 {
1579 u32 chip_id = 0;
1580 u32 chip_ver = 0;
1581 int ret;
1582
1583 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1584 if (ret) {
1585 dev_err(smi->parent, "unable to read chip id\n");
1586 return ret;
1587 }
1588
1589 switch (chip_id) {
1590 case RTL8366S_CHIP_ID_8366:
1591 break;
1592 default:
1593 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1594 return -ENODEV;
1595 }
1596
1597 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1598 &chip_ver);
1599 if (ret) {
1600 dev_err(smi->parent, "unable to read chip version\n");
1601 return ret;
1602 }
1603
1604 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1605 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1606
1607 return 0;
1608 }
1609
1610 static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
1611 .detect = rtl8366rb_detect,
1612 .mii_read = rtl8366rb_mii_read,
1613 .mii_write = rtl8366rb_mii_write,
1614 };
1615
1616 static int __init rtl8366rb_probe(struct platform_device *pdev)
1617 {
1618 static int rtl8366_smi_version_printed;
1619 struct rtl8366rb_platform_data *pdata;
1620 struct rtl8366rb *rtl;
1621 struct rtl8366_smi *smi;
1622 int err;
1623
1624 if (!rtl8366_smi_version_printed++)
1625 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1626 " version " RTL8366S_DRIVER_VER"\n");
1627
1628 pdata = pdev->dev.platform_data;
1629 if (!pdata) {
1630 dev_err(&pdev->dev, "no platform data specified\n");
1631 err = -EINVAL;
1632 goto err_out;
1633 }
1634
1635 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1636 if (!rtl) {
1637 dev_err(&pdev->dev, "no memory for private data\n");
1638 err = -ENOMEM;
1639 goto err_out;
1640 }
1641
1642 rtl->parent = &pdev->dev;
1643
1644 smi = &rtl->smi;
1645 smi->parent = &pdev->dev;
1646 smi->gpio_sda = pdata->gpio_sda;
1647 smi->gpio_sck = pdata->gpio_sck;
1648 smi->ops = &rtl8366rb_smi_ops;
1649
1650 err = rtl8366_smi_init(smi);
1651 if (err)
1652 goto err_free_rtl;
1653
1654 platform_set_drvdata(pdev, rtl);
1655
1656 err = rtl8366rb_setup(rtl);
1657 if (err)
1658 goto err_clear_drvdata;
1659
1660 err = rtl8366rb_switch_init(rtl);
1661 if (err)
1662 goto err_clear_drvdata;
1663
1664 return 0;
1665
1666 err_clear_drvdata:
1667 platform_set_drvdata(pdev, NULL);
1668 rtl8366_smi_cleanup(smi);
1669 err_free_rtl:
1670 kfree(rtl);
1671 err_out:
1672 return err;
1673 }
1674
1675 static int rtl8366rb_phy_config_init(struct phy_device *phydev)
1676 {
1677 if (!rtl8366rb_mii_bus_match(phydev->bus))
1678 return -EINVAL;
1679
1680 return 0;
1681 }
1682
1683 static int rtl8366rb_phy_config_aneg(struct phy_device *phydev)
1684 {
1685 return 0;
1686 }
1687
1688 static struct phy_driver rtl8366rb_phy_driver = {
1689 .phy_id = 0x001cc960,
1690 .name = "Realtek RTL8366RB",
1691 .phy_id_mask = 0x1ffffff0,
1692 .features = PHY_GBIT_FEATURES,
1693 .config_aneg = rtl8366rb_phy_config_aneg,
1694 .config_init = rtl8366rb_phy_config_init,
1695 .read_status = genphy_read_status,
1696 .driver = {
1697 .owner = THIS_MODULE,
1698 },
1699 };
1700
1701 static int __devexit rtl8366rb_remove(struct platform_device *pdev)
1702 {
1703 struct rtl8366rb *rtl = platform_get_drvdata(pdev);
1704
1705 if (rtl) {
1706 rtl8366rb_switch_cleanup(rtl);
1707 rtl8366rb_debugfs_remove(rtl);
1708 platform_set_drvdata(pdev, NULL);
1709 rtl8366_smi_cleanup(&rtl->smi);
1710 kfree(rtl);
1711 }
1712
1713 return 0;
1714 }
1715
1716 static struct platform_driver rtl8366rb_driver = {
1717 .driver = {
1718 .name = RTL8366RB_DRIVER_NAME,
1719 .owner = THIS_MODULE,
1720 },
1721 .probe = rtl8366rb_probe,
1722 .remove = __devexit_p(rtl8366rb_remove),
1723 };
1724
1725 static int __init rtl8366rb_module_init(void)
1726 {
1727 int ret;
1728 ret = platform_driver_register(&rtl8366rb_driver);
1729 if (ret)
1730 return ret;
1731
1732 ret = phy_driver_register(&rtl8366rb_phy_driver);
1733 if (ret)
1734 goto err_platform_unregister;
1735
1736 return 0;
1737
1738 err_platform_unregister:
1739 platform_driver_unregister(&rtl8366rb_driver);
1740 return ret;
1741 }
1742 module_init(rtl8366rb_module_init);
1743
1744 static void __exit rtl8366rb_module_exit(void)
1745 {
1746 phy_driver_unregister(&rtl8366rb_phy_driver);
1747 platform_driver_unregister(&rtl8366rb_driver);
1748 }
1749 module_exit(rtl8366rb_module_exit);
1750
1751 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1752 MODULE_VERSION(RTL8366S_DRIVER_VER);
1753 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1754 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1755 MODULE_LICENSE("GPL v2");
1756 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);
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