target/linux/generic/backport-5.10/610-v5.13-51-net-ethernet-mtk_eth_soc-use-iopoll.h-macro-for-DMA-.patch

   1 From 3bc8e0aff23be0526af0dbc7973a8866a08d73f1 Mon Sep 17 00:00:00 2001
   2 From: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
   3 Date: Thu, 22 Apr 2021 22:21:08 -0700
   4 Subject: [PATCH] net: ethernet: mtk_eth_soc: use iopoll.h macro for DMA init
   5
   6 Replace a tight busy-wait loop without a pause with a standard
   7 readx_poll_timeout_atomic routine with a 5 us poll period.
   8
   9 Tested by booting a MT7621 device to ensure the driver initializes
  10 properly.
  11
  12 Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
  13 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
  14 Signed-off-by: David S. Miller <davem@davemloft.net>
  15 ---
  16  drivers/net/ethernet/mediatek/mtk_eth_soc.c | 29 +++++++++------------
  17  drivers/net/ethernet/mediatek/mtk_eth_soc.h |  2 +-
  18  2 files changed, 14 insertions(+), 17 deletions(-)
  19
  20 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  21 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  22 @@ -2054,25 +2054,22 @@ static int mtk_set_features(struct net_d
  23  /* wait for DMA to finish whatever it is doing before we start using it again */
  24  static int mtk_dma_busy_wait(struct mtk_eth *eth)
  25  {
  26 -       unsigned long t_start = jiffies;
  27 +       unsigned int reg;
  28 +       int ret;
  29 +       u32 val;
  30
  31 -       while (1) {
  32 -               if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA)) {
  33 -                       if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &
  34 -                             (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
  35 -                               return 0;
  36 -               } else {
  37 -                       if (!(mtk_r32(eth, MTK_PDMA_GLO_CFG) &
  38 -                             (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
  39 -                               return 0;
  40 -               }
  41 +       if (MTK_HAS_CAPS(eth->soc->caps, MTK_QDMA))
  42 +               reg = MTK_QDMA_GLO_CFG;
  43 +       else
  44 +               reg = MTK_PDMA_GLO_CFG;
  45
  46 -               if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))
  47 -                       break;
  48 -       }
  49 +       ret = readx_poll_timeout_atomic(__raw_readl, eth->base + reg, val,
  50 +                                       !(val & (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)),
  51 +                                       5, MTK_DMA_BUSY_TIMEOUT_US);
  52 +       if (ret)
  53 +               dev_err(eth->dev, "DMA init timeout\n");
  54
  55 -       dev_err(eth->dev, "DMA init timeout\n");
  56 -       return -1;
  57 +       return ret;
  58  }
  59
  60  static int mtk_dma_init(struct mtk_eth *eth)
  61 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  62 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  63 @@ -213,7 +213,7 @@
  64  #define MTK_TX_DMA_BUSY                BIT(1)
  65  #define MTK_RX_DMA_EN          BIT(2)
  66  #define MTK_TX_DMA_EN          BIT(0)
  67 -#define MTK_DMA_BUSY_TIMEOUT   HZ
  68 +#define MTK_DMA_BUSY_TIMEOUT_US        1000000
  69
  70  /* QDMA Reset Index Register */
  71  #define MTK_QDMA_RST_IDX       0x1A08